[u-boot.git] / drivers / video / da8xx-fb.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Porting to u-boot:
 *
 * (C) Copyright 2011
 * Stefano Babic, DENX Software Engineering, [email protected].
 *
 * Copyright (C) 2008-2009 MontaVista Software Inc.
 * Copyright (C) 2008-2009 Texas Instruments Inc
 *
 * Based on the LCD driver for TI Avalanche processors written by
 * Ajay Singh and Shalom Hai.
 */

#ifndef DA8XX_FB_H
#define DA8XX_FB_H

enum panel_type {
	QVGA = 0,
	WVGA
};

enum panel_shade {
	MONOCHROME = 0,
	COLOR_ACTIVE,
	COLOR_PASSIVE,
};

enum raster_load_mode {
	LOAD_DATA = 1,
	LOAD_PALETTE,
};

struct display_panel {
	enum panel_type panel_type; /* QVGA */
	int max_bpp;
	int min_bpp;
	enum panel_shade panel_shade;
};

struct da8xx_panel {
	const char	name[25];	/* Full name <vendor>_<model> */
	unsigned short	width;
	unsigned short	height;
	int		hfp;		/* Horizontal front porch */
	int		hbp;		/* Horizontal back porch */
	int		hsw;		/* Horizontal Sync Pulse Width */
	int		vfp;		/* Vertical front porch */
	int		vbp;		/* Vertical back porch */
	int		vsw;		/* Vertical Sync Pulse Width */
	unsigned int	pxl_clk;	/* Pixel clock */
	unsigned char	invert_pxl_clk;	/* Invert Pixel clock */
};

struct da8xx_lcdc_platform_data {
	const char manu_name[10];
	void *controller_data;
	const char type[25];
	void (*panel_power_ctrl)(int);
};

struct lcd_ctrl_config {
	const struct display_panel *p_disp_panel;

	/* AC Bias Pin Frequency */
	int ac_bias;

	/* AC Bias Pin Transitions per Interrupt */
	int ac_bias_intrpt;

	/* DMA burst size */
	int dma_burst_sz;

	/* Bits per pixel */
	int bpp;

	/* FIFO DMA Request Delay */
	int fdd;

	/* TFT Alternative Signal Mapping (Only for active) */
	unsigned char tft_alt_mode;

	/* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */
	unsigned char stn_565_mode;

	/* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
	unsigned char mono_8bit_mode;

	/* Invert line clock */
	unsigned char invert_line_clock;

	/* Invert frame clock  */
	unsigned char invert_frm_clock;

	/* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
	unsigned char sync_edge;

	/* Horizontal and Vertical Sync: Control: 0=ignore */
	unsigned char sync_ctrl;

	/* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
	unsigned char raster_order;
};

struct lcd_sync_arg {
	int back_porch;
	int front_porch;
	int pulse_width;
};

void da8xx_video_init(const struct da8xx_panel *panel,
		      const struct lcd_ctrl_config *lcd_cfg,
		      int bits_pixel);

#endif  /* ifndef DA8XX_FB_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
13402868 SB	2	/*
	3	* Porting to u-boot:
	4	*
	5	* (C) Copyright 2011
	6	* Stefano Babic, DENX Software Engineering, [email protected].
	7	*
	8	* Copyright (C) 2008-2009 MontaVista Software Inc.
	9	* Copyright (C) 2008-2009 Texas Instruments Inc
	10	*
	11	* Based on the LCD driver for TI Avalanche processors written by
	12	* Ajay Singh and Shalom Hai.
13402868 SB	13	*/
	14
	15	#ifndef DA8XX_FB_H
	16	#define DA8XX_FB_H
	17
	18	enum panel_type {
0017f9ee HS	19	QVGA = 0,
0017f9ee HS	20	WVGA
13402868 SB	21	};
	22
	23	enum panel_shade {
	24	MONOCHROME = 0,
	25	COLOR_ACTIVE,
	26	COLOR_PASSIVE,
	27	};
	28
	29	enum raster_load_mode {
	30	LOAD_DATA = 1,
	31	LOAD_PALETTE,
	32	};
	33
	34	struct display_panel {
	35	enum panel_type panel_type; /* QVGA */
	36	int max_bpp;
	37	int min_bpp;
	38	enum panel_shade panel_shade;
	39	};
	40
	41	struct da8xx_panel {
	42	const char name[25]; /* Full name <vendor>_<model> */
	43	unsigned short width;
	44	unsigned short height;
	45	int hfp; /* Horizontal front porch */
	46	int hbp; /* Horizontal back porch */
	47	int hsw; /* Horizontal Sync Pulse Width */
	48	int vfp; /* Vertical front porch */
	49	int vbp; /* Vertical back porch */
	50	int vsw; /* Vertical Sync Pulse Width */
	51	unsigned int pxl_clk; /* Pixel clock */
	52	unsigned char invert_pxl_clk; /* Invert Pixel clock */
	53	};
	54
	55	struct da8xx_lcdc_platform_data {
	56	const char manu_name[10];
	57	void *controller_data;
	58	const char type[25];
	59	void (*panel_power_ctrl)(int);
	60	};
	61
	62	struct lcd_ctrl_config {
	63	const struct display_panel *p_disp_panel;
	64
	65	/* AC Bias Pin Frequency */
	66	int ac_bias;
	67
	68	/* AC Bias Pin Transitions per Interrupt */
	69	int ac_bias_intrpt;
	70
	71	/* DMA burst size */
	72	int dma_burst_sz;
	73
	74	/* Bits per pixel */
	75	int bpp;
	76
	77	/* FIFO DMA Request Delay */
	78	int fdd;
	79
	80	/* TFT Alternative Signal Mapping (Only for active) */
	81	unsigned char tft_alt_mode;
	82
	83	/* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */
	84	unsigned char stn_565_mode;
85
86	/* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
87	unsigned char mono_8bit_mode;
88
89	/* Invert line clock */
90	unsigned char invert_line_clock;
91
92	/* Invert frame clock */
93	unsigned char invert_frm_clock;
94
95	/* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
96	unsigned char sync_edge;
97
98	/* Horizontal and Vertical Sync: Control: 0=ignore */
99	unsigned char sync_ctrl;
100
101	/* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
102	unsigned char raster_order;
103	};
104
105	struct lcd_sync_arg {
106	int back_porch;
107	int front_porch;
108	int pulse_width;
109	};
110
765f2f08 HS	111	void da8xx_video_init(const struct da8xx_panel *panel,
	112	const struct lcd_ctrl_config *lcd_cfg,
	113	int bits_pixel);
13402868 SB	114
13402868 SB	115	#endif /* ifndef DA8XX_FB_H */