[u-boot.git] / drivers / phy / phy-mtk-tphy.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2015 - 2019 MediaTek Inc.
 * Author: Chunfeng Yun <[email protected]>
 *	   Ryder Lee <[email protected]>
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <generic-phy.h>
#include <malloc.h>
#include <mapmem.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <dm/devres.h>

#include <dt-bindings/phy/phy.h>

/* version V1 sub-banks offset base address */
/* banks shared by multiple phys */
#define SSUSB_SIFSLV_V1_SPLLC		0x000	/* shared by u3 phys */
#define SSUSB_SIFSLV_V1_U2FREQ		0x100	/* shared by u2 phys */
#define SSUSB_SIFSLV_V1_CHIP		0x300	/* shared by u3 phys */
/* u2 phy bank */
#define SSUSB_SIFSLV_V1_U2PHY_COM	0x000
/* u3/pcie/sata phy banks */
#define SSUSB_SIFSLV_V1_U3PHYD		0x000
#define SSUSB_SIFSLV_V1_U3PHYA		0x200

/* version V2 sub-banks offset base address */
/* u2 phy banks */
#define SSUSB_SIFSLV_V2_MISC		0x000
#define SSUSB_SIFSLV_V2_U2FREQ		0x100
#define SSUSB_SIFSLV_V2_U2PHY_COM	0x300
/* u3/pcie/sata phy banks */
#define SSUSB_SIFSLV_V2_SPLLC		0x000
#define SSUSB_SIFSLV_V2_CHIP		0x100
#define SSUSB_SIFSLV_V2_U3PHYD		0x200
#define SSUSB_SIFSLV_V2_U3PHYA		0x400

#define U3P_USBPHYACR0			0x000
#define PA0_RG_U2PLL_FORCE_ON		BIT(15)
#define PA0_RG_USB20_INTR_EN		BIT(5)

#define U3P_USBPHYACR5			0x014
#define PA5_RG_U2_HSTX_SRCAL_EN		BIT(15)
#define PA5_RG_U2_HSTX_SRCTRL		GENMASK(14, 12)
#define PA5_RG_U2_HSTX_SRCTRL_VAL(x)	((0x7 & (x)) << 12)
#define PA5_RG_U2_HS_100U_U3_EN		BIT(11)

#define U3P_USBPHYACR6			0x018
#define PA6_RG_U2_BC11_SW_EN		BIT(23)
#define PA6_RG_U2_OTG_VBUSCMP_EN	BIT(20)
#define PA6_RG_U2_SQTH			GENMASK(3, 0)
#define PA6_RG_U2_SQTH_VAL(x)		(0xf & (x))

#define U3P_U2PHYACR4			0x020
#define P2C_RG_USB20_GPIO_CTL		BIT(9)
#define P2C_USB20_GPIO_MODE		BIT(8)
#define P2C_U2_GPIO_CTR_MSK	\
		(P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)

#define U3P_U2PHYDTM0			0x068
#define P2C_FORCE_UART_EN		BIT(26)
#define P2C_FORCE_DATAIN		BIT(23)
#define P2C_FORCE_DM_PULLDOWN		BIT(21)
#define P2C_FORCE_DP_PULLDOWN		BIT(20)
#define P2C_FORCE_XCVRSEL		BIT(19)
#define P2C_FORCE_SUSPENDM		BIT(18)
#define P2C_FORCE_TERMSEL		BIT(17)
#define P2C_RG_DATAIN			GENMASK(13, 10)
#define P2C_RG_DATAIN_VAL(x)		((0xf & (x)) << 10)
#define P2C_RG_DMPULLDOWN		BIT(7)
#define P2C_RG_DPPULLDOWN		BIT(6)
#define P2C_RG_XCVRSEL			GENMASK(5, 4)
#define P2C_RG_XCVRSEL_VAL(x)		((0x3 & (x)) << 4)
#define P2C_RG_SUSPENDM			BIT(3)
#define P2C_RG_TERMSEL			BIT(2)
#define P2C_DTM0_PART_MASK	\
		(P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
		P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
		P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
		P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)

#define U3P_U2PHYDTM1			0x06C
#define P2C_RG_UART_EN			BIT(16)
#define P2C_FORCE_IDDIG			BIT(9)
#define P2C_RG_VBUSVALID		BIT(5)
#define P2C_RG_SESSEND			BIT(4)
#define P2C_RG_AVALID			BIT(2)
#define P2C_RG_IDDIG			BIT(1)

#define U3P_U3_CHIP_GPIO_CTLD		0x0c
#define P3C_REG_IP_SW_RST		BIT(31)
#define P3C_MCU_BUS_CK_GATE_EN		BIT(30)
#define P3C_FORCE_IP_SW_RST		BIT(29)

#define U3P_U3_CHIP_GPIO_CTLE		0x10
#define P3C_RG_SWRST_U3_PHYD		BIT(25)
#define P3C_RG_SWRST_U3_PHYD_FORCE_EN	BIT(24)

#define U3P_U3_PHYA_REG0		0x000
#define P3A_RG_CLKDRV_OFF		GENMASK(3, 2)
#define P3A_RG_CLKDRV_OFF_VAL(x)	((0x3 & (x)) << 2)

#define U3P_U3_PHYA_REG1		0x004
#define P3A_RG_CLKDRV_AMP		GENMASK(31, 29)
#define P3A_RG_CLKDRV_AMP_VAL(x)	((0x7 & (x)) << 29)

#define U3P_U3_PHYA_REG6		0x018
#define P3A_RG_TX_EIDLE_CM		GENMASK(31, 28)
#define P3A_RG_TX_EIDLE_CM_VAL(x)	((0xf & (x)) << 28)

#define U3P_U3_PHYA_REG9		0x024
#define P3A_RG_RX_DAC_MUX		GENMASK(5, 1)
#define P3A_RG_RX_DAC_MUX_VAL(x)	((0x1f & (x)) << 1)

#define U3P_U3_PHYA_DA_REG0		0x100
#define P3A_RG_XTAL_EXT_PE2H		GENMASK(17, 16)
#define P3A_RG_XTAL_EXT_PE2H_VAL(x)	((0x3 & (x)) << 16)
#define P3A_RG_XTAL_EXT_PE1H		GENMASK(13, 12)
#define P3A_RG_XTAL_EXT_PE1H_VAL(x)	((0x3 & (x)) << 12)
#define P3A_RG_XTAL_EXT_EN_U3		GENMASK(11, 10)
#define P3A_RG_XTAL_EXT_EN_U3_VAL(x)	((0x3 & (x)) << 10)

#define U3P_U3_PHYA_DA_REG4		0x108
#define P3A_RG_PLL_DIVEN_PE2H		GENMASK(21, 19)
#define P3A_RG_PLL_BC_PE2H		GENMASK(7, 6)
#define P3A_RG_PLL_BC_PE2H_VAL(x)	((0x3 & (x)) << 6)

#define U3P_U3_PHYA_DA_REG5		0x10c
#define P3A_RG_PLL_BR_PE2H		GENMASK(29, 28)
#define P3A_RG_PLL_BR_PE2H_VAL(x)	((0x3 & (x)) << 28)
#define P3A_RG_PLL_IC_PE2H		GENMASK(15, 12)
#define P3A_RG_PLL_IC_PE2H_VAL(x)	((0xf & (x)) << 12)

#define U3P_U3_PHYA_DA_REG6		0x110
#define P3A_RG_PLL_IR_PE2H		GENMASK(19, 16)
#define P3A_RG_PLL_IR_PE2H_VAL(x)	((0xf & (x)) << 16)

#define U3P_U3_PHYA_DA_REG7		0x114
#define P3A_RG_PLL_BP_PE2H		GENMASK(19, 16)
#define P3A_RG_PLL_BP_PE2H_VAL(x)	((0xf & (x)) << 16)

#define U3P_U3_PHYA_DA_REG20		0x13c
#define P3A_RG_PLL_DELTA1_PE2H		GENMASK(31, 16)
#define P3A_RG_PLL_DELTA1_PE2H_VAL(x)	((0xffff & (x)) << 16)

#define U3P_U3_PHYA_DA_REG25		0x148
#define P3A_RG_PLL_DELTA_PE2H		GENMASK(15, 0)
#define P3A_RG_PLL_DELTA_PE2H_VAL(x)	(0xffff & (x))

#define U3P_U3_PHYD_LFPS1		0x00c
#define P3D_RG_FWAKE_TH			GENMASK(21, 16)
#define P3D_RG_FWAKE_TH_VAL(x)		((0x3f & (x)) << 16)

#define U3P_U3_PHYD_CDR1		0x05c
#define P3D_RG_CDR_BIR_LTD1		GENMASK(28, 24)
#define P3D_RG_CDR_BIR_LTD1_VAL(x)	((0x1f & (x)) << 24)
#define P3D_RG_CDR_BIR_LTD0		GENMASK(12, 8)
#define P3D_RG_CDR_BIR_LTD0_VAL(x)	((0x1f & (x)) << 8)

#define U3P_U3_PHYD_RXDET1		0x128
#define P3D_RG_RXDET_STB2_SET		GENMASK(17, 9)
#define P3D_RG_RXDET_STB2_SET_VAL(x)	((0x1ff & (x)) << 9)

#define U3P_U3_PHYD_RXDET2		0x12c
#define P3D_RG_RXDET_STB2_SET_P3	GENMASK(8, 0)
#define P3D_RG_RXDET_STB2_SET_P3_VAL(x)	(0x1ff & (x))

#define U3P_SPLLC_XTALCTL3		0x018
#define XC3_RG_U3_XTAL_RX_PWD		BIT(9)
#define XC3_RG_U3_FRC_XTAL_RX_PWD	BIT(8)

enum mtk_phy_version {
	MTK_TPHY_V1 = 1,
	MTK_TPHY_V2,
};

struct u2phy_banks {
	void __iomem *misc;
	void __iomem *fmreg;
	void __iomem *com;
};

struct u3phy_banks {
	void __iomem *spllc;
	void __iomem *chip;
	void __iomem *phyd; /* include u3phyd_bank2 */
	void __iomem *phya; /* include u3phya_da */
};

struct mtk_phy_instance {
	void __iomem *port_base;
	const struct device_node *np;
	union {
		struct u2phy_banks u2_banks;
		struct u3phy_banks u3_banks;
	};

	/* reference clock of anolog phy */
	struct clk ref_clk;
	u32 index;
	u32 type;
};

struct mtk_tphy {
	struct udevice *dev;
	void __iomem *sif_base;
	enum mtk_phy_version version;
	struct mtk_phy_instance **phys;
	int nphys;
};

static void u2_phy_instance_init(struct mtk_tphy *tphy,
				 struct mtk_phy_instance *instance)
{
	struct u2phy_banks *u2_banks = &instance->u2_banks;

	/* switch to USB function, and enable usb pll */
	clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM0,
			P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM,
			P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0));

	clrbits_le32(u2_banks->com + U3P_U2PHYDTM1, P2C_RG_UART_EN);
	setbits_le32(u2_banks->com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN);

	/* disable switch 100uA current to SSUSB */
	clrbits_le32(u2_banks->com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);

	clrbits_le32(u2_banks->com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);

	/* DP/DM BC1.1 path Disable */
	clrsetbits_le32(u2_banks->com + U3P_USBPHYACR6,
			PA6_RG_U2_BC11_SW_EN | PA6_RG_U2_SQTH,
			PA6_RG_U2_SQTH_VAL(2));

	/* set HS slew rate */
	clrsetbits_le32(u2_banks->com + U3P_USBPHYACR5,
			PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4));

	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
}

static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
				     struct mtk_phy_instance *instance)
{
	struct u2phy_banks *u2_banks = &instance->u2_banks;

	clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
		     P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);

	/* OTG Enable */
	setbits_le32(u2_banks->com + U3P_USBPHYACR6,
		     PA6_RG_U2_OTG_VBUSCMP_EN);

	clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
			P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID);

	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
}

static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
				      struct mtk_phy_instance *instance)
{
	struct u2phy_banks *u2_banks = &instance->u2_banks;

	clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
		     P2C_RG_XCVRSEL | P2C_RG_DATAIN);

	/* OTG Disable */
	clrbits_le32(u2_banks->com + U3P_USBPHYACR6,
		     PA6_RG_U2_OTG_VBUSCMP_EN);

	clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
			P2C_RG_VBUSVALID | P2C_RG_AVALID, P2C_RG_SESSEND);

	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
}

static void u3_phy_instance_init(struct mtk_tphy *tphy,
				 struct mtk_phy_instance *instance)
{
	struct u3phy_banks *u3_banks = &instance->u3_banks;

	/* gating PCIe Analog XTAL clock */
	setbits_le32(u3_banks->spllc + U3P_SPLLC_XTALCTL3,
		     XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD);

	/* gating XSQ */
	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
			P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2));

	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG9,
			P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4));

	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG6,
			P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe));

	clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_CDR1,
			P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1,
			P3D_RG_CDR_BIR_LTD0_VAL(0xc) |
			P3D_RG_CDR_BIR_LTD1_VAL(0x3));

	clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_LFPS1,
			P3D_RG_FWAKE_TH, P3D_RG_FWAKE_TH_VAL(0x34));

	clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
			P3D_RG_RXDET_STB2_SET, P3D_RG_RXDET_STB2_SET_VAL(0x10));

	clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
			P3D_RG_RXDET_STB2_SET_P3,
			P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));

	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
}

static void pcie_phy_instance_init(struct mtk_tphy *tphy,
				   struct mtk_phy_instance *instance)
{
	struct u3phy_banks *u3_banks = &instance->u3_banks;

	if (tphy->version != MTK_TPHY_V1)
		return;

	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
			P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
			P3A_RG_XTAL_EXT_PE1H_VAL(0x2) |
			P3A_RG_XTAL_EXT_PE2H_VAL(0x2));

	/* ref clk drive */
	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP,
			P3A_RG_CLKDRV_AMP_VAL(0x4));
	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF,
			P3A_RG_CLKDRV_OFF_VAL(0x1));

	/* SSC delta -5000ppm */
	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG20,
			P3A_RG_PLL_DELTA1_PE2H,
			P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c));

	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG25,
			P3A_RG_PLL_DELTA_PE2H,
			P3A_RG_PLL_DELTA_PE2H_VAL(0x36));

	/* change pll BW 0.6M */
	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG5,
			P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H,
			P3A_RG_PLL_BR_PE2H_VAL(0x1) |
			P3A_RG_PLL_IC_PE2H_VAL(0x1));
	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG4,
			P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H,
			P3A_RG_PLL_BC_PE2H_VAL(0x3));

	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG6,
			P3A_RG_PLL_IR_PE2H, P3A_RG_PLL_IR_PE2H_VAL(0x2));
	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG7,
			P3A_RG_PLL_BP_PE2H, P3A_RG_PLL_BP_PE2H_VAL(0xa));

	/* Tx Detect Rx Timing: 10us -> 5us */
	clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
			P3D_RG_RXDET_STB2_SET,
			P3D_RG_RXDET_STB2_SET_VAL(0x10));
	clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
			P3D_RG_RXDET_STB2_SET_P3,
			P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));

	/* wait for PCIe subsys register to active */
	udelay(3000);
}

static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
				       struct mtk_phy_instance *instance)
{
	struct u3phy_banks *bank = &instance->u3_banks;

	clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
		     P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
	clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
		     P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
}

static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
					struct mtk_phy_instance *instance)

{
	struct u3phy_banks *bank = &instance->u3_banks;

	setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
		     P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
	setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
		     P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
}

static void phy_v1_banks_init(struct mtk_tphy *tphy,
			      struct mtk_phy_instance *instance)
{
	struct u2phy_banks *u2_banks = &instance->u2_banks;
	struct u3phy_banks *u3_banks = &instance->u3_banks;

	switch (instance->type) {
	case PHY_TYPE_USB2:
		u2_banks->misc = NULL;
		u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
		break;
	case PHY_TYPE_USB3:
	case PHY_TYPE_PCIE:
		u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
		u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
		break;
	default:
		dev_err(tphy->dev, "incompatible PHY type\n");
		return;
	}
}

static void phy_v2_banks_init(struct mtk_tphy *tphy,
			      struct mtk_phy_instance *instance)
{
	struct u2phy_banks *u2_banks = &instance->u2_banks;
	struct u3phy_banks *u3_banks = &instance->u3_banks;

	switch (instance->type) {
	case PHY_TYPE_USB2:
		u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
		u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
		break;
	case PHY_TYPE_USB3:
	case PHY_TYPE_PCIE:
		u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
		u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
		break;
	default:
		dev_err(tphy->dev, "incompatible PHY type\n");
		return;
	}
}

static int mtk_phy_init(struct phy *phy)
{
	struct mtk_tphy *tphy = dev_get_priv(phy->dev);
	struct mtk_phy_instance *instance = tphy->phys[phy->id];
	int ret;

	ret = clk_enable(&instance->ref_clk);
	if (ret)
		return ret;

	switch (instance->type) {
	case PHY_TYPE_USB2:
		u2_phy_instance_init(tphy, instance);
		break;
	case PHY_TYPE_USB3:
		u3_phy_instance_init(tphy, instance);
		break;
	case PHY_TYPE_PCIE:
		pcie_phy_instance_init(tphy, instance);
		break;
	default:
		dev_err(tphy->dev, "incompatible PHY type\n");
		return -EINVAL;
	}

	return 0;
}

static int mtk_phy_power_on(struct phy *phy)
{
	struct mtk_tphy *tphy = dev_get_priv(phy->dev);
	struct mtk_phy_instance *instance = tphy->phys[phy->id];

	if (instance->type == PHY_TYPE_USB2)
		u2_phy_instance_power_on(tphy, instance);
	else if (instance->type == PHY_TYPE_PCIE)
		pcie_phy_instance_power_on(tphy, instance);

	return 0;
}

static int mtk_phy_power_off(struct phy *phy)
{
	struct mtk_tphy *tphy = dev_get_priv(phy->dev);
	struct mtk_phy_instance *instance = tphy->phys[phy->id];

	if (instance->type == PHY_TYPE_USB2)
		u2_phy_instance_power_off(tphy, instance);
	else if (instance->type == PHY_TYPE_PCIE)
		pcie_phy_instance_power_off(tphy, instance);

	return 0;
}

static int mtk_phy_exit(struct phy *phy)
{
	struct mtk_tphy *tphy = dev_get_priv(phy->dev);
	struct mtk_phy_instance *instance = tphy->phys[phy->id];

	clk_disable(&instance->ref_clk);

	return 0;
}

static int mtk_phy_xlate(struct phy *phy,
			 struct ofnode_phandle_args *args)
{
	struct mtk_tphy *tphy = dev_get_priv(phy->dev);
	struct mtk_phy_instance *instance = NULL;
	const struct device_node *phy_np = ofnode_to_np(args->node);
	u32 index;

	if (!phy_np) {
		dev_err(phy->dev, "null pointer phy node\n");
		return -EINVAL;
	}

	if (args->args_count < 1) {
		dev_err(phy->dev, "invalid number of cells in 'phy' property\n");
		return -EINVAL;
	}

	for (index = 0; index < tphy->nphys; index++)
		if (phy_np == tphy->phys[index]->np) {
			instance = tphy->phys[index];
			break;
		}

	if (!instance) {
		dev_err(phy->dev, "failed to find appropriate phy\n");
		return -EINVAL;
	}

	phy->id = index;
	instance->type = args->args[1];
	if (!(instance->type == PHY_TYPE_USB2 ||
	      instance->type == PHY_TYPE_USB3 ||
	      instance->type == PHY_TYPE_PCIE)) {
		dev_err(phy->dev, "unsupported device type\n");
		return -EINVAL;
	}

	if (tphy->version == MTK_TPHY_V1) {
		phy_v1_banks_init(tphy, instance);
	} else if (tphy->version == MTK_TPHY_V2) {
		phy_v2_banks_init(tphy, instance);
	} else {
		dev_err(phy->dev, "phy version is not supported\n");
		return -EINVAL;
	}

	return 0;
}

static const struct phy_ops mtk_tphy_ops = {
	.init		= mtk_phy_init,
	.exit		= mtk_phy_exit,
	.power_on	= mtk_phy_power_on,
	.power_off	= mtk_phy_power_off,
	.of_xlate	= mtk_phy_xlate,
};

static int mtk_tphy_probe(struct udevice *dev)
{
	struct mtk_tphy *tphy = dev_get_priv(dev);
	ofnode subnode;
	int index = 0;

	tphy->nphys = dev_get_child_count(dev);

	tphy->phys = devm_kcalloc(dev, tphy->nphys, sizeof(*tphy->phys),
				  GFP_KERNEL);
	if (!tphy->phys)
		return -ENOMEM;

	tphy->dev = dev;
	tphy->version = dev_get_driver_data(dev);

	/* v1 has shared banks */
	if (tphy->version == MTK_TPHY_V1) {
		tphy->sif_base = dev_read_addr_ptr(dev);
		if (!tphy->sif_base)
			return -ENOENT;
	}

	dev_for_each_subnode(subnode, dev) {
		struct mtk_phy_instance *instance;
		fdt_addr_t addr;
		int err;

		instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
		if (!instance)
			return -ENOMEM;

		addr = ofnode_get_addr(subnode);
		if (addr == FDT_ADDR_T_NONE)
			return -ENOMEM;

		instance->port_base = map_sysmem(addr, 0);
		instance->index = index;
		instance->np = ofnode_to_np(subnode);
		tphy->phys[index] = instance;
		index++;

		err = clk_get_optional_nodev(subnode, "ref",
					     &instance->ref_clk);
		if (err)
			return err;
	}

	return 0;
}

static const struct udevice_id mtk_tphy_id_table[] = {
	{ .compatible = "mediatek,generic-tphy-v1", .data = MTK_TPHY_V1, },
	{ .compatible = "mediatek,generic-tphy-v2", .data = MTK_TPHY_V2, },
	{ }
};

U_BOOT_DRIVER(mtk_tphy) = {
	.name		= "mtk-tphy",
	.id		= UCLASS_PHY,
	.of_match	= mtk_tphy_id_table,
	.ops		= &mtk_tphy_ops,
	.probe		= mtk_tphy_probe,
	.priv_auto_alloc_size = sizeof(struct mtk_tphy),
};
Commit	Line	Data
235bad02 RL	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (c) 2015 - 2019 MediaTek Inc.
	4	* Author: Chunfeng Yun <[email protected]>
	5	* Ryder Lee <[email protected]>
	6	*/
	7
	8	#include <common.h>
	9	#include <clk.h>
	10	#include <dm.h>
	11	#include <generic-phy.h>
336d4615	12	#include <malloc.h>
235bad02 RL	13	#include <mapmem.h>
235bad02 RL	14	#include <asm/io.h>
336d4615	15	#include <dm/device_compat.h>
61b29b82	16	#include <dm/devres.h>
235bad02 RL	17
	18	#include <dt-bindings/phy/phy.h>
	19
	20	/* version V1 sub-banks offset base address */
	21	/* banks shared by multiple phys */
	22	#define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */
ee6eabbe	23	#define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */
235bad02	24	#define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */
ee6eabbe CY	25	/* u2 phy bank */
ee6eabbe CY	26	#define SSUSB_SIFSLV_V1_U2PHY_COM 0x000
235bad02 RL	27	/* u3/pcie/sata phy banks */
	28	#define SSUSB_SIFSLV_V1_U3PHYD 0x000
	29	#define SSUSB_SIFSLV_V1_U3PHYA 0x200
	30
d1ae8445 CY	31	/* version V2 sub-banks offset base address */
	32	/* u2 phy banks */
	33	#define SSUSB_SIFSLV_V2_MISC 0x000
	34	#define SSUSB_SIFSLV_V2_U2FREQ 0x100
	35	#define SSUSB_SIFSLV_V2_U2PHY_COM 0x300
	36	/* u3/pcie/sata phy banks */
	37	#define SSUSB_SIFSLV_V2_SPLLC 0x000
	38	#define SSUSB_SIFSLV_V2_CHIP 0x100
	39	#define SSUSB_SIFSLV_V2_U3PHYD 0x200
	40	#define SSUSB_SIFSLV_V2_U3PHYA 0x400
	41
ee6eabbe CY	42	#define U3P_USBPHYACR0 0x000
	43	#define PA0_RG_U2PLL_FORCE_ON BIT(15)
	44	#define PA0_RG_USB20_INTR_EN BIT(5)
	45
	46	#define U3P_USBPHYACR5 0x014
	47	#define PA5_RG_U2_HSTX_SRCAL_EN BIT(15)
	48	#define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12)
	49	#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
	50	#define PA5_RG_U2_HS_100U_U3_EN BIT(11)
	51
	52	#define U3P_USBPHYACR6 0x018
	53	#define PA6_RG_U2_BC11_SW_EN BIT(23)
	54	#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
	55	#define PA6_RG_U2_SQTH GENMASK(3, 0)
	56	#define PA6_RG_U2_SQTH_VAL(x) (0xf & (x))
	57
	58	#define U3P_U2PHYACR4 0x020
	59	#define P2C_RG_USB20_GPIO_CTL BIT(9)
	60	#define P2C_USB20_GPIO_MODE BIT(8)
	61	#define P2C_U2_GPIO_CTR_MSK \
	62	(P2C_RG_USB20_GPIO_CTL \| P2C_USB20_GPIO_MODE)
	63
	64	#define U3P_U2PHYDTM0 0x068
	65	#define P2C_FORCE_UART_EN BIT(26)
	66	#define P2C_FORCE_DATAIN BIT(23)
	67	#define P2C_FORCE_DM_PULLDOWN BIT(21)
	68	#define P2C_FORCE_DP_PULLDOWN BIT(20)
	69	#define P2C_FORCE_XCVRSEL BIT(19)
	70	#define P2C_FORCE_SUSPENDM BIT(18)
	71	#define P2C_FORCE_TERMSEL BIT(17)
	72	#define P2C_RG_DATAIN GENMASK(13, 10)
	73	#define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10)
	74	#define P2C_RG_DMPULLDOWN BIT(7)
	75	#define P2C_RG_DPPULLDOWN BIT(6)
	76	#define P2C_RG_XCVRSEL GENMASK(5, 4)
	77	#define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4)
	78	#define P2C_RG_SUSPENDM BIT(3)
	79	#define P2C_RG_TERMSEL BIT(2)
	80	#define P2C_DTM0_PART_MASK \
	81	(P2C_FORCE_DATAIN \| P2C_FORCE_DM_PULLDOWN \| \
	82	P2C_FORCE_DP_PULLDOWN \| P2C_FORCE_XCVRSEL \| \
	83	P2C_FORCE_TERMSEL \| P2C_RG_DMPULLDOWN \| \
	84	P2C_RG_DPPULLDOWN \| P2C_RG_TERMSEL)
	85
	86	#define U3P_U2PHYDTM1 0x06C
	87	#define P2C_RG_UART_EN BIT(16)
	88	#define P2C_FORCE_IDDIG BIT(9)
	89	#define P2C_RG_VBUSVALID BIT(5)
	90	#define P2C_RG_SESSEND BIT(4)
	91	#define P2C_RG_AVALID BIT(2)
	92	#define P2C_RG_IDDIG BIT(1)
	93
235bad02 RL	94	#define U3P_U3_CHIP_GPIO_CTLD 0x0c
	95	#define P3C_REG_IP_SW_RST BIT(31)
	96	#define P3C_MCU_BUS_CK_GATE_EN BIT(30)
	97	#define P3C_FORCE_IP_SW_RST BIT(29)
	98
	99	#define U3P_U3_CHIP_GPIO_CTLE 0x10
	100	#define P3C_RG_SWRST_U3_PHYD BIT(25)
	101	#define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24)
	102
	103	#define U3P_U3_PHYA_REG0 0x000
	104	#define P3A_RG_CLKDRV_OFF GENMASK(3, 2)
	105	#define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2)
	106
	107	#define U3P_U3_PHYA_REG1 0x004
	108	#define P3A_RG_CLKDRV_AMP GENMASK(31, 29)
	109	#define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29)
	110
ee6eabbe CY	111	#define U3P_U3_PHYA_REG6 0x018
	112	#define P3A_RG_TX_EIDLE_CM GENMASK(31, 28)
	113	#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
	114
	115	#define U3P_U3_PHYA_REG9 0x024
	116	#define P3A_RG_RX_DAC_MUX GENMASK(5, 1)
	117	#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
	118
235bad02 RL	119	#define U3P_U3_PHYA_DA_REG0 0x100
	120	#define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16)
	121	#define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16)
	122	#define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12)
	123	#define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12)
	124	#define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10)
	125	#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
	126
	127	#define U3P_U3_PHYA_DA_REG4 0x108
	128	#define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19)
	129	#define P3A_RG_PLL_BC_PE2H GENMASK(7, 6)
	130	#define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6)
	131
	132	#define U3P_U3_PHYA_DA_REG5 0x10c
	133	#define P3A_RG_PLL_BR_PE2H GENMASK(29, 28)
	134	#define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28)
	135	#define P3A_RG_PLL_IC_PE2H GENMASK(15, 12)
	136	#define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12)
	137
	138	#define U3P_U3_PHYA_DA_REG6 0x110
	139	#define P3A_RG_PLL_IR_PE2H GENMASK(19, 16)
	140	#define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16)
	141
	142	#define U3P_U3_PHYA_DA_REG7 0x114
	143	#define P3A_RG_PLL_BP_PE2H GENMASK(19, 16)
	144	#define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16)
	145
	146	#define U3P_U3_PHYA_DA_REG20 0x13c
	147	#define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16)
	148	#define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16)
	149
	150	#define U3P_U3_PHYA_DA_REG25 0x148
	151	#define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0)
	152	#define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x))
	153
ee6eabbe CY	154	#define U3P_U3_PHYD_LFPS1 0x00c
	155	#define P3D_RG_FWAKE_TH GENMASK(21, 16)
	156	#define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16)
	157
	158	#define U3P_U3_PHYD_CDR1 0x05c
	159	#define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24)
	160	#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)
	161	#define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8)
	162	#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)
	163
235bad02 RL	164	#define U3P_U3_PHYD_RXDET1 0x128
	165	#define P3D_RG_RXDET_STB2_SET GENMASK(17, 9)
	166	#define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9)
	167
	168	#define U3P_U3_PHYD_RXDET2 0x12c
	169	#define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0)
	170	#define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x))
	171
ee6eabbe CY	172	#define U3P_SPLLC_XTALCTL3 0x018
	173	#define XC3_RG_U3_XTAL_RX_PWD BIT(9)
	174	#define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8)
	175
d1ae8445 CY	176	enum mtk_phy_version {
	177	MTK_TPHY_V1 = 1,
	178	MTK_TPHY_V2,
	179	};
	180
ee6eabbe CY	181	struct u2phy_banks {
	182	void __iomem *misc;
	183	void __iomem *fmreg;
	184	void __iomem *com;
	185	};
	186
235bad02 RL	187	struct u3phy_banks {
	188	void __iomem *spllc;
	189	void __iomem *chip;
	190	void __iomem phyd; / include u3phyd_bank2 */
	191	void __iomem phya; / include u3phya_da */
	192	};
	193
	194	struct mtk_phy_instance {
	195	void __iomem *port_base;
	196	const struct device_node *np;
ee6eabbe CY	197	union {
	198	struct u2phy_banks u2_banks;
	199	struct u3phy_banks u3_banks;
	200	};
235bad02 RL	201
	202	/* reference clock of anolog phy */
	203	struct clk ref_clk;
	204	u32 index;
ee6eabbe	205	u32 type;
235bad02 RL	206	};
	207
	208	struct mtk_tphy {
ee6eabbe	209	struct udevice *dev;
235bad02	210	void __iomem *sif_base;
d1ae8445	211	enum mtk_phy_version version;
235bad02 RL	212	struct mtk_phy_instance **phys;
	213	int nphys;
	214	};
	215
ee6eabbe CY	216	static void u2_phy_instance_init(struct mtk_tphy *tphy,
	217	struct mtk_phy_instance *instance)
	218	{
	219	struct u2phy_banks *u2_banks = &instance->u2_banks;
	220
	221	/* switch to USB function, and enable usb pll */
	222	clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM0,
	223	P2C_FORCE_UART_EN \| P2C_FORCE_SUSPENDM,
	224	P2C_RG_XCVRSEL_VAL(1) \| P2C_RG_DATAIN_VAL(0));
	225
	226	clrbits_le32(u2_banks->com + U3P_U2PHYDTM1, P2C_RG_UART_EN);
	227	setbits_le32(u2_banks->com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN);
	228
	229	/* disable switch 100uA current to SSUSB */
	230	clrbits_le32(u2_banks->com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
	231
	232	clrbits_le32(u2_banks->com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
	233
	234	/* DP/DM BC1.1 path Disable */
	235	clrsetbits_le32(u2_banks->com + U3P_USBPHYACR6,
	236	PA6_RG_U2_BC11_SW_EN \| PA6_RG_U2_SQTH,
	237	PA6_RG_U2_SQTH_VAL(2));
	238
	239	/* set HS slew rate */
	240	clrsetbits_le32(u2_banks->com + U3P_USBPHYACR5,
	241	PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4));
	242
	243	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
	244	}
	245
	246	static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
	247	struct mtk_phy_instance *instance)
	248	{
	249	struct u2phy_banks *u2_banks = &instance->u2_banks;
	250
	251	clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
	252	P2C_RG_XCVRSEL \| P2C_RG_DATAIN \| P2C_DTM0_PART_MASK);
	253
	254	/* OTG Enable */
	255	setbits_le32(u2_banks->com + U3P_USBPHYACR6,
	256	PA6_RG_U2_OTG_VBUSCMP_EN);
	257
	258	clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
	259	P2C_RG_SESSEND, P2C_RG_VBUSVALID \| P2C_RG_AVALID);
	260
	261	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
	262	}
	263
	264	static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
	265	struct mtk_phy_instance *instance)
	266	{
	267	struct u2phy_banks *u2_banks = &instance->u2_banks;
	268
	269	clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
	270	P2C_RG_XCVRSEL \| P2C_RG_DATAIN);
	271
	272	/* OTG Disable */
	273	clrbits_le32(u2_banks->com + U3P_USBPHYACR6,
	274	PA6_RG_U2_OTG_VBUSCMP_EN);
	275
	276	clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
	277	P2C_RG_VBUSVALID \| P2C_RG_AVALID, P2C_RG_SESSEND);
	278
	279	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
280	}
281
282	static void u3_phy_instance_init(struct mtk_tphy *tphy,
283	struct mtk_phy_instance *instance)
284	{
285	struct u3phy_banks *u3_banks = &instance->u3_banks;
286
287	/* gating PCIe Analog XTAL clock */
288	setbits_le32(u3_banks->spllc + U3P_SPLLC_XTALCTL3,
289	XC3_RG_U3_XTAL_RX_PWD \| XC3_RG_U3_FRC_XTAL_RX_PWD);
290
291	/* gating XSQ */
292	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
293	P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2));
294
295	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG9,
296	P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4));
297
298	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG6,
299	P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe));
300
301	clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_CDR1,
302	P3D_RG_CDR_BIR_LTD0 \| P3D_RG_CDR_BIR_LTD1,
303	P3D_RG_CDR_BIR_LTD0_VAL(0xc) \|
304	P3D_RG_CDR_BIR_LTD1_VAL(0x3));
305
306	clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_LFPS1,
307	P3D_RG_FWAKE_TH, P3D_RG_FWAKE_TH_VAL(0x34));
308
309	clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
310	P3D_RG_RXDET_STB2_SET, P3D_RG_RXDET_STB2_SET_VAL(0x10));
311
312	clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
313	P3D_RG_RXDET_STB2_SET_P3,
314	P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
315
316	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
317	}
318
235bad02 RL	319	static void pcie_phy_instance_init(struct mtk_tphy *tphy,
	320	struct mtk_phy_instance *instance)
	321	{
	322	struct u3phy_banks *u3_banks = &instance->u3_banks;
	323
d1ae8445 CY	324	if (tphy->version != MTK_TPHY_V1)
	325	return;
	326
235bad02 RL	327	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
	328	P3A_RG_XTAL_EXT_PE1H \| P3A_RG_XTAL_EXT_PE2H,
	329	P3A_RG_XTAL_EXT_PE1H_VAL(0x2) \|
	330	P3A_RG_XTAL_EXT_PE2H_VAL(0x2));
	331
	332	/* ref clk drive */
	333	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP,
	334	P3A_RG_CLKDRV_AMP_VAL(0x4));
	335	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF,
	336	P3A_RG_CLKDRV_OFF_VAL(0x1));
	337
	338	/* SSC delta -5000ppm */
	339	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG20,
	340	P3A_RG_PLL_DELTA1_PE2H,
	341	P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c));
	342
	343	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG25,
	344	P3A_RG_PLL_DELTA_PE2H,
	345	P3A_RG_PLL_DELTA_PE2H_VAL(0x36));
	346
	347	/* change pll BW 0.6M */
	348	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG5,
	349	P3A_RG_PLL_BR_PE2H \| P3A_RG_PLL_IC_PE2H,
	350	P3A_RG_PLL_BR_PE2H_VAL(0x1) \|
	351	P3A_RG_PLL_IC_PE2H_VAL(0x1));
	352	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG4,
	353	P3A_RG_PLL_DIVEN_PE2H \| P3A_RG_PLL_BC_PE2H,
	354	P3A_RG_PLL_BC_PE2H_VAL(0x3));
	355
	356	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG6,
	357	P3A_RG_PLL_IR_PE2H, P3A_RG_PLL_IR_PE2H_VAL(0x2));
	358	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG7,
	359	P3A_RG_PLL_BP_PE2H, P3A_RG_PLL_BP_PE2H_VAL(0xa));
	360
	361	/* Tx Detect Rx Timing: 10us -> 5us */
	362	clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
	363	P3D_RG_RXDET_STB2_SET,
	364	P3D_RG_RXDET_STB2_SET_VAL(0x10));
	365	clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
	366	P3D_RG_RXDET_STB2_SET_P3,
	367	P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
	368
	369	/* wait for PCIe subsys register to active */
	370	udelay(3000);
	371	}
	372
	373	static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
	374	struct mtk_phy_instance *instance)
	375	{
	376	struct u3phy_banks *bank = &instance->u3_banks;
	377
	378	clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
	379	P3C_FORCE_IP_SW_RST \| P3C_REG_IP_SW_RST);
	380	clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
	381	P3C_RG_SWRST_U3_PHYD_FORCE_EN \| P3C_RG_SWRST_U3_PHYD);
	382	}
	383
	384	static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
	385	struct mtk_phy_instance *instance)
	386
	387	{
	388	struct u3phy_banks *bank = &instance->u3_banks;
	389
	390	setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
391	P3C_FORCE_IP_SW_RST \| P3C_REG_IP_SW_RST);
392	setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
393	P3C_RG_SWRST_U3_PHYD_FORCE_EN \| P3C_RG_SWRST_U3_PHYD);
394	}
395
396	static void phy_v1_banks_init(struct mtk_tphy *tphy,
397	struct mtk_phy_instance *instance)
398	{
ee6eabbe	399	struct u2phy_banks *u2_banks = &instance->u2_banks;
235bad02 RL	400	struct u3phy_banks *u3_banks = &instance->u3_banks;
	401
	402	switch (instance->type) {
ee6eabbe CY	403	case PHY_TYPE_USB2:
	404	u2_banks->misc = NULL;
	405	u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
	406	u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
	407	break;
	408	case PHY_TYPE_USB3:
235bad02 RL	409	case PHY_TYPE_PCIE:
	410	u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
	411	u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
	412	u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
	413	u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
	414	break;
	415	default:
ee6eabbe	416	dev_err(tphy->dev, "incompatible PHY type\n");
235bad02 RL	417	return;
	418	}
	419	}
	420
d1ae8445 CY	421	static void phy_v2_banks_init(struct mtk_tphy *tphy,
	422	struct mtk_phy_instance *instance)
	423	{
	424	struct u2phy_banks *u2_banks = &instance->u2_banks;
	425	struct u3phy_banks *u3_banks = &instance->u3_banks;
	426
	427	switch (instance->type) {
	428	case PHY_TYPE_USB2:
	429	u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
	430	u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
	431	u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
	432	break;
	433	case PHY_TYPE_USB3:
	434	case PHY_TYPE_PCIE:
	435	u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
	436	u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
	437	u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
	438	u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
	439	break;
	440	default:
	441	dev_err(tphy->dev, "incompatible PHY type\n");
	442	return;
	443	}
	444	}
	445
235bad02 RL	446	static int mtk_phy_init(struct phy *phy)
	447	{
	448	struct mtk_tphy *tphy = dev_get_priv(phy->dev);
	449	struct mtk_phy_instance *instance = tphy->phys[phy->id];
	450	int ret;
	451
235bad02	452	ret = clk_enable(&instance->ref_clk);
3b6351a4	453	if (ret)
235bad02 RL	454	return ret;
	455
	456	switch (instance->type) {
ee6eabbe CY	457	case PHY_TYPE_USB2:
	458	u2_phy_instance_init(tphy, instance);
	459	break;
	460	case PHY_TYPE_USB3:
	461	u3_phy_instance_init(tphy, instance);
	462	break;
235bad02 RL	463	case PHY_TYPE_PCIE:
	464	pcie_phy_instance_init(tphy, instance);
	465	break;
	466	default:
ee6eabbe	467	dev_err(tphy->dev, "incompatible PHY type\n");
235bad02 RL	468	return -EINVAL;
	469	}
	470
	471	return 0;
	472	}
	473
	474	static int mtk_phy_power_on(struct phy *phy)
	475	{
	476	struct mtk_tphy *tphy = dev_get_priv(phy->dev);
	477	struct mtk_phy_instance *instance = tphy->phys[phy->id];
	478
ee6eabbe CY	479	if (instance->type == PHY_TYPE_USB2)
	480	u2_phy_instance_power_on(tphy, instance);
	481	else if (instance->type == PHY_TYPE_PCIE)
	482	pcie_phy_instance_power_on(tphy, instance);
235bad02 RL	483
	484	return 0;
	485	}
	486
	487	static int mtk_phy_power_off(struct phy *phy)
	488	{
	489	struct mtk_tphy *tphy = dev_get_priv(phy->dev);
	490	struct mtk_phy_instance *instance = tphy->phys[phy->id];
	491
ee6eabbe CY	492	if (instance->type == PHY_TYPE_USB2)
	493	u2_phy_instance_power_off(tphy, instance);
	494	else if (instance->type == PHY_TYPE_PCIE)
	495	pcie_phy_instance_power_off(tphy, instance);
235bad02 RL	496
	497	return 0;
	498	}
	499
	500	static int mtk_phy_exit(struct phy *phy)
	501	{
	502	struct mtk_tphy *tphy = dev_get_priv(phy->dev);
	503	struct mtk_phy_instance *instance = tphy->phys[phy->id];
	504
	505	clk_disable(&instance->ref_clk);
	506
	507	return 0;
	508	}
	509
	510	static int mtk_phy_xlate(struct phy *phy,
	511	struct ofnode_phandle_args *args)
	512	{
	513	struct mtk_tphy *tphy = dev_get_priv(phy->dev);
	514	struct mtk_phy_instance *instance = NULL;
	515	const struct device_node *phy_np = ofnode_to_np(args->node);
	516	u32 index;
	517
	518	if (!phy_np) {
	519	dev_err(phy->dev, "null pointer phy node\n");
	520	return -EINVAL;
	521	}
	522
	523	if (args->args_count < 1) {
	524	dev_err(phy->dev, "invalid number of cells in 'phy' property\n");
	525	return -EINVAL;
	526	}
	527
	528	for (index = 0; index < tphy->nphys; index++)
	529	if (phy_np == tphy->phys[index]->np) {
	530	instance = tphy->phys[index];
	531	break;
	532	}
	533
	534	if (!instance) {
	535	dev_err(phy->dev, "failed to find appropriate phy\n");
	536	return -EINVAL;
	537	}
	538
	539	phy->id = index;
	540	instance->type = args->args[1];
	541	if (!(instance->type == PHY_TYPE_USB2 \|\|
	542	instance->type == PHY_TYPE_USB3 \|\|
ee6eabbe	543	instance->type == PHY_TYPE_PCIE)) {
235bad02 RL	544	dev_err(phy->dev, "unsupported device type\n");
	545	return -EINVAL;
	546	}
	547
d1ae8445 CY	548	if (tphy->version == MTK_TPHY_V1) {
	549	phy_v1_banks_init(tphy, instance);
	550	} else if (tphy->version == MTK_TPHY_V2) {
	551	phy_v2_banks_init(tphy, instance);
	552	} else {
	553	dev_err(phy->dev, "phy version is not supported\n");
	554	return -EINVAL;
	555	}
235bad02 RL	556
	557	return 0;
	558	}
	559
	560	static const struct phy_ops mtk_tphy_ops = {
	561	.init = mtk_phy_init,
	562	.exit = mtk_phy_exit,
	563	.power_on = mtk_phy_power_on,
	564	.power_off = mtk_phy_power_off,
	565	.of_xlate = mtk_phy_xlate,
	566	};
	567
	568	static int mtk_tphy_probe(struct udevice *dev)
	569	{
	570	struct mtk_tphy *tphy = dev_get_priv(dev);
	571	ofnode subnode;
	572	int index = 0;
	573
ee6eabbe	574	tphy->nphys = dev_get_child_count(dev);
235bad02 RL	575
	576	tphy->phys = devm_kcalloc(dev, tphy->nphys, sizeof(*tphy->phys),
	577	GFP_KERNEL);
	578	if (!tphy->phys)
	579	return -ENOMEM;
	580
ee6eabbe	581	tphy->dev = dev;
d1ae8445 CY	582	tphy->version = dev_get_driver_data(dev);
	583
	584	/* v1 has shared banks */
	585	if (tphy->version == MTK_TPHY_V1) {
	586	tphy->sif_base = dev_read_addr_ptr(dev);
	587	if (!tphy->sif_base)
	588	return -ENOENT;
	589	}
235bad02 RL	590
	591	dev_for_each_subnode(subnode, dev) {
	592	struct mtk_phy_instance *instance;
	593	fdt_addr_t addr;
	594	int err;
	595
	596	instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
	597	if (!instance)
	598	return -ENOMEM;
	599
	600	addr = ofnode_get_addr(subnode);
	601	if (addr == FDT_ADDR_T_NONE)
	602	return -ENOMEM;
	603
	604	instance->port_base = map_sysmem(addr, 0);
	605	instance->index = index;
	606	instance->np = ofnode_to_np(subnode);
	607	tphy->phys[index] = instance;
	608	index++;
	609
ce0069ed CY	610	err = clk_get_optional_nodev(subnode, "ref",
ce0069ed CY	611	&instance->ref_clk);
235bad02 RL	612	if (err)
	613	return err;
	614	}
	615
	616	return 0;
	617	}
	618
	619	static const struct udevice_id mtk_tphy_id_table[] = {
d1ae8445 CY	620	{ .compatible = "mediatek,generic-tphy-v1", .data = MTK_TPHY_V1, },
d1ae8445 CY	621	{ .compatible = "mediatek,generic-tphy-v2", .data = MTK_TPHY_V2, },
235bad02 RL	622	{ }
	623	};
	624
	625	U_BOOT_DRIVER(mtk_tphy) = {
	626	.name = "mtk-tphy",
	627	.id = UCLASS_PHY,
	628	.of_match = mtk_tphy_id_table,
	629	.ops = &mtk_tphy_ops,
	630	.probe = mtk_tphy_probe,
	631	.priv_auto_alloc_size = sizeof(struct mtk_tphy),
	632	};