[u-boot.git] / board / ti / am335x / board.c

/*
 * board.c
 *
 * Board functions for TI AM335X based boards
 *
 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include <power/tps65217.h>
#include <power/tps65910.h>
#include <environment.h>
#include <watchdog.h>
#include "board.h"

DECLARE_GLOBAL_DATA_PTR;

/* GPIO that controls power to DDR on EVM-SK */
#define GPIO_DDR_VTT_EN		7

static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;

/*
 * Read header information from EEPROM into global structure.
 */
static int read_eeprom(struct am335x_baseboard_id *header)
{
	/* Check if baseboard eeprom is available */
	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
		puts("Could not probe the EEPROM; something fundamentally "
			"wrong on the I2C bus.\n");
		return -ENODEV;
	}

	/* read the eeprom using i2c */
	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
		     sizeof(struct am335x_baseboard_id))) {
		puts("Could not read the EEPROM; something fundamentally"
			" wrong on the I2C bus.\n");
		return -EIO;
	}

	if (header->magic != 0xEE3355AA) {
		/*
		 * read the eeprom using i2c again,
		 * but use only a 1 byte address
		 */
		if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
			     sizeof(struct am335x_baseboard_id))) {
			puts("Could not read the EEPROM; something "
				"fundamentally wrong on the I2C bus.\n");
			return -EIO;
		}

		if (header->magic != 0xEE3355AA) {
			printf("Incorrect magic number (0x%x) in EEPROM\n",
					header->magic);
			return -EINVAL;
		}
	}

	return 0;
}

#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
static const struct ddr_data ddr2_data = {
	.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
			  (MT47H128M16RT25E_RD_DQS<<20) |
			  (MT47H128M16RT25E_RD_DQS<<10) |
			  (MT47H128M16RT25E_RD_DQS<<0)),
	.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
			  (MT47H128M16RT25E_WR_DQS<<20) |
			  (MT47H128M16RT25E_WR_DQS<<10) |
			  (MT47H128M16RT25E_WR_DQS<<0)),
	.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
			 (MT47H128M16RT25E_PHY_WRLVL<<20) |
			 (MT47H128M16RT25E_PHY_WRLVL<<10) |
			 (MT47H128M16RT25E_PHY_WRLVL<<0)),
	.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
			 (MT47H128M16RT25E_PHY_GATELVL<<20) |
			 (MT47H128M16RT25E_PHY_GATELVL<<10) |
			 (MT47H128M16RT25E_PHY_GATELVL<<0)),
	.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
			  (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
			  (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
			  (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
	.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
			  (MT47H128M16RT25E_PHY_WR_DATA<<20) |
			  (MT47H128M16RT25E_PHY_WR_DATA<<10) |
			  (MT47H128M16RT25E_PHY_WR_DATA<<0)),
};

static const struct cmd_control ddr2_cmd_ctrl_data = {
	.cmd0csratio = MT47H128M16RT25E_RATIO,
	.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,

	.cmd1csratio = MT47H128M16RT25E_RATIO,
	.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,

	.cmd2csratio = MT47H128M16RT25E_RATIO,
	.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
};

static const struct emif_regs ddr2_emif_reg_data = {
	.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
	.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
	.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
	.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
	.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
};

static const struct ddr_data ddr3_data = {
	.datardsratio0 = MT41J128MJT125_RD_DQS,
	.datawdsratio0 = MT41J128MJT125_WR_DQS,
	.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
};

static const struct ddr_data ddr3_beagleblack_data = {
	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
};

static const struct ddr_data ddr3_evm_data = {
	.datardsratio0 = MT41J512M8RH125_RD_DQS,
	.datawdsratio0 = MT41J512M8RH125_WR_DQS,
	.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
	.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
};

static const struct cmd_control ddr3_cmd_ctrl_data = {
	.cmd0csratio = MT41J128MJT125_RATIO,
	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,

	.cmd1csratio = MT41J128MJT125_RATIO,
	.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,

	.cmd2csratio = MT41J128MJT125_RATIO,
	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
};

static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
	.cmd0csratio = MT41K256M16HA125E_RATIO,
	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,

	.cmd1csratio = MT41K256M16HA125E_RATIO,
	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,

	.cmd2csratio = MT41K256M16HA125E_RATIO,
	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};

static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
	.cmd0csratio = MT41J512M8RH125_RATIO,
	.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,

	.cmd1csratio = MT41J512M8RH125_RATIO,
	.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,

	.cmd2csratio = MT41J512M8RH125_RATIO,
	.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
};

static struct emif_regs ddr3_emif_reg_data = {
	.sdram_config = MT41J128MJT125_EMIF_SDCFG,
	.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
	.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
	.zq_config = MT41J128MJT125_ZQ_CFG,
	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
				PHY_EN_DYN_PWRDN,
};

static struct emif_regs ddr3_beagleblack_emif_reg_data = {
	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
	.zq_config = MT41K256M16HA125E_ZQ_CFG,
	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};

static struct emif_regs ddr3_evm_emif_reg_data = {
	.sdram_config = MT41J512M8RH125_EMIF_SDCFG,
	.ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
	.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
	.zq_config = MT41J512M8RH125_ZQ_CFG,
	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
				PHY_EN_DYN_PWRDN,
};

#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
	/* break into full u-boot on 'c' */
	return (serial_tstc() && serial_getc() == 'c');
}
#endif

#define OSC	(V_OSCK/1000000)
const struct dpll_params dpll_ddr = {
		266, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_ddr_evm_sk = {
		303, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_ddr_bone_black = {
		400, OSC-1, 1, -1, -1, -1, -1};

void am33xx_spl_board_init(void)
{
	struct am335x_baseboard_id header;
	int mpu_vdd;

	if (read_eeprom(&header) < 0)
		puts("Could not get board ID.\n");

	/* Get the frequency */
	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);

	if (board_is_bone(&header) || board_is_bone_lt(&header)) {
		/* BeagleBone PMIC Code */
		int usb_cur_lim;

		/*
		 * Only perform PMIC configurations if board rev > A1
		 * on Beaglebone White
		 */
		if (board_is_bone(&header) && !strncmp(header.version,
						       "00A1", 4))
			return;

		if (i2c_probe(TPS65217_CHIP_PM))
			return;

		/*
		 * On Beaglebone White we need to ensure we have AC power
		 * before increasing the frequency.
		 */
		if (board_is_bone(&header)) {
			uchar pmic_status_reg;
			if (tps65217_reg_read(TPS65217_STATUS,
					      &pmic_status_reg))
				return;
			if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
				puts("No AC power, disabling frequency switch\n");
				return;
			}
		}

		/*
		 * Override what we have detected since we know if we have
		 * a Beaglebone Black it supports 1GHz.
		 */
		if (board_is_bone_lt(&header))
			dpll_mpu_opp100.m = MPUPLL_M_1000;

		/*
		 * Increase USB current limit to 1300mA or 1800mA and set
		 * the MPU voltage controller as needed.
		 */
		if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
			usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
			mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
		} else {
			usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
			mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
		}

		if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
				       TPS65217_POWER_PATH,
				       usb_cur_lim,
				       TPS65217_USB_INPUT_CUR_LIMIT_MASK))
			puts("tps65217_reg_write failure\n");

		/* Set DCDC3 (CORE) voltage to 1.125V */
		if (tps65217_voltage_update(TPS65217_DEFDCDC3,
					    TPS65217_DCDC_VOLT_SEL_1125MV)) {
			puts("tps65217_voltage_update failure\n");
			return;
		}

		/* Set CORE Frequencies to OPP100 */
		do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);

		/* Set DCDC2 (MPU) voltage */
		if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
			puts("tps65217_voltage_update failure\n");
			return;
		}

		/*
		 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
		 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
		 */
		if (board_is_bone(&header)) {
			if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
					       TPS65217_DEFLS1,
					       TPS65217_LDO_VOLTAGE_OUT_3_3,
					       TPS65217_LDO_MASK))
				puts("tps65217_reg_write failure\n");
		} else {
			if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
					       TPS65217_DEFLS1,
					       TPS65217_LDO_VOLTAGE_OUT_1_8,
					       TPS65217_LDO_MASK))
				puts("tps65217_reg_write failure\n");
		}

		if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
				       TPS65217_DEFLS2,
				       TPS65217_LDO_VOLTAGE_OUT_3_3,
				       TPS65217_LDO_MASK))
			puts("tps65217_reg_write failure\n");
	} else {
		int sil_rev;

		/*
		 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
		 * MPU frequencies we support we use a CORE voltage of
		 * 1.1375V.  For MPU voltage we need to switch based on
		 * the frequency we are running at.
		 */
		if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
			return;

		/*
		 * Depending on MPU clock and PG we will need a different
		 * VDD to drive at that speed.
		 */
		sil_rev = readl(&cdev->deviceid) >> 28;
		mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
						      dpll_mpu_opp100.m);

		/* Tell the TPS65910 to use i2c */
		tps65910_set_i2c_control();

		/* First update MPU voltage. */
		if (tps65910_voltage_update(MPU, mpu_vdd))
			return;

		/* Second, update the CORE voltage. */
		if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
			return;

		/* Set CORE Frequencies to OPP100 */
		do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
	}

	/* Set MPU Frequency to what we detected now that voltages are set */
	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
}

const struct dpll_params *get_dpll_ddr_params(void)
{
	struct am335x_baseboard_id header;

	enable_i2c0_pin_mux();
	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
	if (read_eeprom(&header) < 0)
		puts("Could not get board ID.\n");

	if (board_is_evm_sk(&header))
		return &dpll_ddr_evm_sk;
	else if (board_is_bone_lt(&header))
		return &dpll_ddr_bone_black;
	else if (board_is_evm_15_or_later(&header))
		return &dpll_ddr_evm_sk;
	else
		return &dpll_ddr;
}

void set_uart_mux_conf(void)
{
#ifdef CONFIG_SERIAL1
	enable_uart0_pin_mux();
#endif /* CONFIG_SERIAL1 */
#ifdef CONFIG_SERIAL2
	enable_uart1_pin_mux();
#endif /* CONFIG_SERIAL2 */
#ifdef CONFIG_SERIAL3
	enable_uart2_pin_mux();
#endif /* CONFIG_SERIAL3 */
#ifdef CONFIG_SERIAL4
	enable_uart3_pin_mux();
#endif /* CONFIG_SERIAL4 */
#ifdef CONFIG_SERIAL5
	enable_uart4_pin_mux();
#endif /* CONFIG_SERIAL5 */
#ifdef CONFIG_SERIAL6
	enable_uart5_pin_mux();
#endif /* CONFIG_SERIAL6 */
}

void set_mux_conf_regs(void)
{
	__maybe_unused struct am335x_baseboard_id header;

	if (read_eeprom(&header) < 0)
		puts("Could not get board ID.\n");

	enable_board_pin_mux(&header);
}

void sdram_init(void)
{
	__maybe_unused struct am335x_baseboard_id header;

	if (read_eeprom(&header) < 0)
		puts("Could not get board ID.\n");

	if (board_is_evm_sk(&header)) {
		/*
		 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
		 * This is safe enough to do on older revs.
		 */
		gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
		gpio_direction_output(GPIO_DDR_VTT_EN, 1);
	}

	if (board_is_evm_sk(&header))
		config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
	else if (board_is_bone_lt(&header))
		config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
			   &ddr3_beagleblack_data,
			   &ddr3_beagleblack_cmd_ctrl_data,
			   &ddr3_beagleblack_emif_reg_data, 0);
	else if (board_is_evm_15_or_later(&header))
		config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
	else
		config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
}
#endif

/*
 * Basic board specific setup.  Pinmux has been handled already.
 */
int board_init(void)
{
#if defined(CONFIG_HW_WATCHDOG)
	hw_watchdog_init();
#endif

	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
	gpmc_init();
#endif
	return 0;
}

#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	char safe_string[HDR_NAME_LEN + 1];
	struct am335x_baseboard_id header;

	if (read_eeprom(&header) < 0)
		puts("Could not get board ID.\n");

	/* Now set variables based on the header. */
	strncpy(safe_string, (char *)header.name, sizeof(header.name));
	safe_string[sizeof(header.name)] = 0;
	setenv("board_name", safe_string);

	strncpy(safe_string, (char *)header.version, sizeof(header.version));
	safe_string[sizeof(header.version)] = 0;
	setenv("board_rev", safe_string);
#endif

	return 0;
}
#endif

#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
	/* VTP can be added here */

	return;
}

static struct cpsw_slave_data cpsw_slaves[] = {
	{
		.slave_reg_ofs	= 0x208,
		.sliver_reg_ofs	= 0xd80,
		.phy_id		= 0,
	},
	{
		.slave_reg_ofs	= 0x308,
		.sliver_reg_ofs	= 0xdc0,
		.phy_id		= 1,
	},
};

static struct cpsw_platform_data cpsw_data = {
	.mdio_base		= CPSW_MDIO_BASE,
	.cpsw_base		= CPSW_BASE,
	.mdio_div		= 0xff,
	.channels		= 8,
	.cpdma_reg_ofs		= 0x800,
	.slaves			= 1,
	.slave_data		= cpsw_slaves,
	.ale_reg_ofs		= 0xd00,
	.ale_entries		= 1024,
	.host_port_reg_ofs	= 0x108,
	.hw_stats_reg_ofs	= 0x900,
	.bd_ram_ofs		= 0x2000,
	.mac_control		= (1 << 5),
	.control		= cpsw_control,
	.host_port_num		= 0,
	.version		= CPSW_CTRL_VERSION_2,
};
#endif

#if defined(CONFIG_DRIVER_TI_CPSW) || \
	(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
int board_eth_init(bd_t *bis)
{
	int rv, n = 0;
	uint8_t mac_addr[6];
	uint32_t mac_hi, mac_lo;
	__maybe_unused struct am335x_baseboard_id header;

	/* try reading mac address from efuse */
	mac_lo = readl(&cdev->macid0l);
	mac_hi = readl(&cdev->macid0h);
	mac_addr[0] = mac_hi & 0xFF;
	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
	mac_addr[4] = mac_lo & 0xFF;
	mac_addr[5] = (mac_lo & 0xFF00) >> 8;

#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
	if (!getenv("ethaddr")) {
		printf("<ethaddr> not set. Validating first E-fuse MAC\n");

		if (is_valid_ether_addr(mac_addr))
			eth_setenv_enetaddr("ethaddr", mac_addr);
	}

#ifdef CONFIG_DRIVER_TI_CPSW
	if (read_eeprom(&header) < 0)
		puts("Could not get board ID.\n");

	if (board_is_bone(&header) || board_is_bone_lt(&header) ||
	    board_is_idk(&header)) {
		writel(MII_MODE_ENABLE, &cdev->miisel);
		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
				PHY_INTERFACE_MODE_MII;
	} else {
		writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
				PHY_INTERFACE_MODE_RGMII;
	}

	rv = cpsw_register(&cpsw_data);
	if (rv < 0)
		printf("Error %d registering CPSW switch\n", rv);
	else
		n += rv;
#endif

	/*
	 *
	 * CPSW RGMII Internal Delay Mode is not supported in all PVT
	 * operating points.  So we must set the TX clock delay feature
	 * in the AR8051 PHY.  Since we only support a single ethernet
	 * device in U-Boot, we only do this for the first instance.
	 */
#define AR8051_PHY_DEBUG_ADDR_REG	0x1d
#define AR8051_PHY_DEBUG_DATA_REG	0x1e
#define AR8051_DEBUG_RGMII_CLK_DLY_REG	0x5
#define AR8051_RGMII_TX_CLK_DLY		0x100

	if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
		const char *devname;
		devname = miiphy_get_current_dev();

		miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
				AR8051_DEBUG_RGMII_CLK_DLY_REG);
		miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
				AR8051_RGMII_TX_CLK_DLY);
	}
#endif
#if defined(CONFIG_USB_ETHER) && \
	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
	if (is_valid_ether_addr(mac_addr))
		eth_setenv_enetaddr("usbnet_devaddr", mac_addr);

	rv = usb_eth_initialize(bis);
	if (rv < 0)
		printf("Error %d registering USB_ETHER\n", rv);
	else
		n += rv;
#endif
	return n;
}
#endif
Commit	Line	Data
e363426e PK	1	/*
	2	* board.c
	3	*
	4	* Board functions for TI AM335X based boards
	5	*
	6	* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
e363426e PK	9	*/
	10
	11	#include <common.h>
	12	#include <errno.h>
	13	#include <spl.h>
	14	#include <asm/arch/cpu.h>
	15	#include <asm/arch/hardware.h>
	16	#include <asm/arch/omap.h>
	17	#include <asm/arch/ddr_defs.h>
	18	#include <asm/arch/clock.h>
	19	#include <asm/arch/gpio.h>
	20	#include <asm/arch/mmc_host_def.h>
	21	#include <asm/arch/sys_proto.h>
cd8845d7	22	#include <asm/arch/mem.h>
e363426e PK	23	#include <asm/io.h>
	24	#include <asm/emif.h>
	25	#include <asm/gpio.h>
	26	#include <i2c.h>
	27	#include <miiphy.h>
	28	#include <cpsw.h>
9721027a TR	29	#include <power/tps65217.h>
9721027a TR	30	#include <power/tps65910.h>
6843918e TR	31	#include <environment.h>
6843918e TR	32	#include <watchdog.h>
e363426e PK	33	#include "board.h"
	34
	35	DECLARE_GLOBAL_DATA_PTR;
	36
e363426e PK	37	/* GPIO that controls power to DDR on EVM-SK */
	38	#define GPIO_DDR_VTT_EN 7
	39
	40	static struct ctrl_dev cdev = (struct ctrl_dev )CTRL_DEVICE_BASE;
	41
e363426e PK	42	/*
	43	* Read header information from EEPROM into global structure.
	44	*/
ace4275e	45	static int read_eeprom(struct am335x_baseboard_id *header)
e363426e PK	46	{
	47	/* Check if baseboard eeprom is available */
	48	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
	49	puts("Could not probe the EEPROM; something fundamentally "
	50	"wrong on the I2C bus.\n");
	51	return -ENODEV;
	52	}
	53
	54	/* read the eeprom using i2c */
ace4275e TR	55	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
ace4275e TR	56	sizeof(struct am335x_baseboard_id))) {
e363426e PK	57	puts("Could not read the EEPROM; something fundamentally"
	58	" wrong on the I2C bus.\n");
	59	return -EIO;
	60	}
	61
ace4275e	62	if (header->magic != 0xEE3355AA) {
e363426e PK	63	/*
	64	* read the eeprom using i2c again,
	65	* but use only a 1 byte address
	66	*/
ace4275e TR	67	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
ace4275e TR	68	sizeof(struct am335x_baseboard_id))) {
e363426e PK	69	puts("Could not read the EEPROM; something "
	70	"fundamentally wrong on the I2C bus.\n");
	71	return -EIO;
	72	}
	73
ace4275e	74	if (header->magic != 0xEE3355AA) {
e363426e	75	printf("Incorrect magic number (0x%x) in EEPROM\n",
ace4275e	76	header->magic);
e363426e PK	77	return -EINVAL;
	78	}
	79	}
	80
	81	return 0;
	82	}
	83
c5c7a7c3	84	#if defined(CONFIG_SPL_BUILD) \|\| defined(CONFIG_NOR_BOOT)
c00f69db	85	static const struct ddr_data ddr2_data = {
c7d35bef PK	86	.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) \|
	87	(MT47H128M16RT25E_RD_DQS<<20) \|
	88	(MT47H128M16RT25E_RD_DQS<<10) \|
	89	(MT47H128M16RT25E_RD_DQS<<0)),
	90	.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) \|
	91	(MT47H128M16RT25E_WR_DQS<<20) \|
	92	(MT47H128M16RT25E_WR_DQS<<10) \|
	93	(MT47H128M16RT25E_WR_DQS<<0)),
	94	.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) \|
	95	(MT47H128M16RT25E_PHY_WRLVL<<20) \|
	96	(MT47H128M16RT25E_PHY_WRLVL<<10) \|
	97	(MT47H128M16RT25E_PHY_WRLVL<<0)),
	98	.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) \|
	99	(MT47H128M16RT25E_PHY_GATELVL<<20) \|
	100	(MT47H128M16RT25E_PHY_GATELVL<<10) \|
	101	(MT47H128M16RT25E_PHY_GATELVL<<0)),
	102	.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) \|
	103	(MT47H128M16RT25E_PHY_FIFO_WE<<20) \|
	104	(MT47H128M16RT25E_PHY_FIFO_WE<<10) \|
	105	(MT47H128M16RT25E_PHY_FIFO_WE<<0)),
	106	.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) \|
	107	(MT47H128M16RT25E_PHY_WR_DATA<<20) \|
	108	(MT47H128M16RT25E_PHY_WR_DATA<<10) \|
	109	(MT47H128M16RT25E_PHY_WR_DATA<<0)),
c00f69db	110	};
e363426e	111
c00f69db	112	static const struct cmd_control ddr2_cmd_ctrl_data = {
c7d35bef	113	.cmd0csratio = MT47H128M16RT25E_RATIO,
c7d35bef	114	.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
c00f69db	115
c7d35bef	116	.cmd1csratio = MT47H128M16RT25E_RATIO,
c7d35bef	117	.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
c00f69db	118
c7d35bef	119	.cmd2csratio = MT47H128M16RT25E_RATIO,
c7d35bef	120	.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
c00f69db PK	121	};
	122
	123	static const struct emif_regs ddr2_emif_reg_data = {
c7d35bef PK	124	.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
	125	.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
	126	.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
	127	.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
	128	.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
	129	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
c00f69db PK	130	};
	131
	132	static const struct ddr_data ddr3_data = {
c7d35bef PK	133	.datardsratio0 = MT41J128MJT125_RD_DQS,
	134	.datawdsratio0 = MT41J128MJT125_WR_DQS,
	135	.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
	136	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
c00f69db PK	137	};
c00f69db PK	138
c7ba18ad TR	139	static const struct ddr_data ddr3_beagleblack_data = {
	140	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
	141	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
	142	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
	143	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
c7ba18ad TR	144	};
c7ba18ad TR	145
13526f71 JL	146	static const struct ddr_data ddr3_evm_data = {
	147	.datardsratio0 = MT41J512M8RH125_RD_DQS,
	148	.datawdsratio0 = MT41J512M8RH125_WR_DQS,
	149	.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
	150	.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
13526f71 JL	151	};
13526f71 JL	152
c00f69db	153	static const struct cmd_control ddr3_cmd_ctrl_data = {
c7d35bef	154	.cmd0csratio = MT41J128MJT125_RATIO,
c7d35bef	155	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
c00f69db	156
c7d35bef	157	.cmd1csratio = MT41J128MJT125_RATIO,
c7d35bef	158	.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
c00f69db	159
c7d35bef	160	.cmd2csratio = MT41J128MJT125_RATIO,
c7d35bef	161	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
c00f69db PK	162	};
c00f69db PK	163
c7ba18ad TR	164	static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
c7ba18ad TR	165	.cmd0csratio = MT41K256M16HA125E_RATIO,
c7ba18ad TR	166	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
	167
	168	.cmd1csratio = MT41K256M16HA125E_RATIO,
c7ba18ad TR	169	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
	170
	171	.cmd2csratio = MT41K256M16HA125E_RATIO,
c7ba18ad TR	172	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
	173	};
	174
13526f71 JL	175	static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
13526f71 JL	176	.cmd0csratio = MT41J512M8RH125_RATIO,
13526f71 JL	177	.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
	178
	179	.cmd1csratio = MT41J512M8RH125_RATIO,
13526f71 JL	180	.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
	181
	182	.cmd2csratio = MT41J512M8RH125_RATIO,
13526f71 JL	183	.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
	184	};
	185
c00f69db	186	static struct emif_regs ddr3_emif_reg_data = {
c7d35bef PK	187	.sdram_config = MT41J128MJT125_EMIF_SDCFG,
	188	.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
	189	.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
	190	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
	191	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
	192	.zq_config = MT41J128MJT125_ZQ_CFG,
59dcf970 VH	193	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY \|
59dcf970 VH	194	PHY_EN_DYN_PWRDN,
c00f69db	195	};
13526f71	196
c7ba18ad TR	197	static struct emif_regs ddr3_beagleblack_emif_reg_data = {
	198	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
	199	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
	200	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
	201	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
	202	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
	203	.zq_config = MT41K256M16HA125E_ZQ_CFG,
	204	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
	205	};
	206
13526f71 JL	207	static struct emif_regs ddr3_evm_emif_reg_data = {
	208	.sdram_config = MT41J512M8RH125_EMIF_SDCFG,
	209	.ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
	210	.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
	211	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
	212	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
	213	.zq_config = MT41J512M8RH125_ZQ_CFG,
59dcf970 VH	214	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY \|
59dcf970 VH	215	PHY_EN_DYN_PWRDN,
13526f71	216	};
12d7a474 PK	217
	218	#ifdef CONFIG_SPL_OS_BOOT
	219	int spl_start_uboot(void)
	220	{
	221	/* break into full u-boot on 'c' */
	222	return (serial_tstc() && serial_getc() == 'c');
	223	}
	224	#endif
	225
94d77fb6 LV	226	#define OSC (V_OSCK/1000000)
	227	const struct dpll_params dpll_ddr = {
	228	266, OSC-1, 1, -1, -1, -1, -1};
	229	const struct dpll_params dpll_ddr_evm_sk = {
	230	303, OSC-1, 1, -1, -1, -1, -1};
	231	const struct dpll_params dpll_ddr_bone_black = {
	232	400, OSC-1, 1, -1, -1, -1, -1};
	233
9721027a TR	234	void am33xx_spl_board_init(void)
	235	{
	236	struct am335x_baseboard_id header;
9721027a TR	237	int mpu_vdd;
	238
	239	if (read_eeprom(&header) < 0)
	240	puts("Could not get board ID.\n");
	241
	242	/* Get the frequency */
52f7d844	243	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
9721027a TR	244
	245	if (board_is_bone(&header) \|\| board_is_bone_lt(&header)) {
	246	/* BeagleBone PMIC Code */
	247	int usb_cur_lim;
	248
	249	/*
	250	* Only perform PMIC configurations if board rev > A1
	251	* on Beaglebone White
	252	*/
	253	if (board_is_bone(&header) && !strncmp(header.version,
	254	"00A1", 4))
	255	return;
	256
	257	if (i2c_probe(TPS65217_CHIP_PM))
	258	return;
	259
	260	/*
	261	* On Beaglebone White we need to ensure we have AC power
	262	* before increasing the frequency.
	263	*/
	264	if (board_is_bone(&header)) {
	265	uchar pmic_status_reg;
	266	if (tps65217_reg_read(TPS65217_STATUS,
	267	&pmic_status_reg))
	268	return;
	269	if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
	270	puts("No AC power, disabling frequency switch\n");
	271	return;
	272	}
	273	}
	274
	275	/*
	276	* Override what we have detected since we know if we have
	277	* a Beaglebone Black it supports 1GHz.
	278	*/
	279	if (board_is_bone_lt(&header))
52f7d844	280	dpll_mpu_opp100.m = MPUPLL_M_1000;
9721027a TR	281
	282	/*
	283	* Increase USB current limit to 1300mA or 1800mA and set
	284	* the MPU voltage controller as needed.
	285	*/
52f7d844	286	if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
9721027a TR	287	usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
	288	mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
	289	} else {
	290	usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
	291	mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
	292	}
	293
	294	if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
	295	TPS65217_POWER_PATH,
	296	usb_cur_lim,
	297	TPS65217_USB_INPUT_CUR_LIMIT_MASK))
	298	puts("tps65217_reg_write failure\n");
	299
52f7d844 SK	300	/* Set DCDC3 (CORE) voltage to 1.125V */
	301	if (tps65217_voltage_update(TPS65217_DEFDCDC3,
	302	TPS65217_DCDC_VOLT_SEL_1125MV)) {
	303	puts("tps65217_voltage_update failure\n");
	304	return;
	305	}
	306
	307	/* Set CORE Frequencies to OPP100 */
	308	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
9721027a TR	309
	310	/* Set DCDC2 (MPU) voltage */
	311	if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
	312	puts("tps65217_voltage_update failure\n");
	313	return;
	314	}
	315
	316	/*
	317	* Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
	318	* Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
	319	*/
	320	if (board_is_bone(&header)) {
	321	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
	322	TPS65217_DEFLS1,
	323	TPS65217_LDO_VOLTAGE_OUT_3_3,
	324	TPS65217_LDO_MASK))
	325	puts("tps65217_reg_write failure\n");
	326	} else {
	327	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
	328	TPS65217_DEFLS1,
	329	TPS65217_LDO_VOLTAGE_OUT_1_8,
	330	TPS65217_LDO_MASK))
	331	puts("tps65217_reg_write failure\n");
	332	}
	333
	334	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
	335	TPS65217_DEFLS2,
	336	TPS65217_LDO_VOLTAGE_OUT_3_3,
	337	TPS65217_LDO_MASK))
	338	puts("tps65217_reg_write failure\n");
	339	} else {
	340	int sil_rev;
	341
	342	/*
	343	* The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
	344	* MPU frequencies we support we use a CORE voltage of
	345	* 1.1375V. For MPU voltage we need to switch based on
	346	* the frequency we are running at.
	347	*/
	348	if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
	349	return;
	350
	351	/*
	352	* Depending on MPU clock and PG we will need a different
	353	* VDD to drive at that speed.
	354	*/
	355	sil_rev = readl(&cdev->deviceid) >> 28;
52f7d844 SK	356	mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
52f7d844 SK	357	dpll_mpu_opp100.m);
9721027a TR	358
	359	/* Tell the TPS65910 to use i2c */
	360	tps65910_set_i2c_control();
	361
	362	/* First update MPU voltage. */
	363	if (tps65910_voltage_update(MPU, mpu_vdd))
	364	return;
	365
	366	/* Second, update the CORE voltage. */
	367	if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
	368	return;
52f7d844 SK	369
	370	/* Set CORE Frequencies to OPP100 */
	371	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
9721027a TR	372	}
	373
	374	/* Set MPU Frequency to what we detected now that voltages are set */
52f7d844	375	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
9721027a TR	376	}
9721027a TR	377
94d77fb6 LV	378	const struct dpll_params *get_dpll_ddr_params(void)
	379	{
	380	struct am335x_baseboard_id header;
	381
	382	enable_i2c0_pin_mux();
6789e84e	383	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
94d77fb6 LV	384	if (read_eeprom(&header) < 0)
	385	puts("Could not get board ID.\n");
	386
	387	if (board_is_evm_sk(&header))
	388	return &dpll_ddr_evm_sk;
	389	else if (board_is_bone_lt(&header))
	390	return &dpll_ddr_bone_black;
	391	else if (board_is_evm_15_or_later(&header))
	392	return &dpll_ddr_evm_sk;
	393	else
	394	return &dpll_ddr;
	395	}
	396
0660481a	397	void set_uart_mux_conf(void)
e363426e	398	{
6422b70b	399	#ifdef CONFIG_SERIAL1
e363426e	400	enable_uart0_pin_mux();
6422b70b AB	401	#endif /* CONFIG_SERIAL1 */
	402	#ifdef CONFIG_SERIAL2
	403	enable_uart1_pin_mux();
	404	#endif /* CONFIG_SERIAL2 */
	405	#ifdef CONFIG_SERIAL3
	406	enable_uart2_pin_mux();
	407	#endif /* CONFIG_SERIAL3 */
	408	#ifdef CONFIG_SERIAL4
	409	enable_uart3_pin_mux();
	410	#endif /* CONFIG_SERIAL4 */
	411	#ifdef CONFIG_SERIAL5
	412	enable_uart4_pin_mux();
	413	#endif /* CONFIG_SERIAL5 */
	414	#ifdef CONFIG_SERIAL6
	415	enable_uart5_pin_mux();
	416	#endif /* CONFIG_SERIAL6 */
0660481a	417	}
e363426e	418
0660481a HS	419	void set_mux_conf_regs(void)
	420	{
	421	__maybe_unused struct am335x_baseboard_id header;
e363426e	422
0660481a HS	423	if (read_eeprom(&header) < 0)
0660481a HS	424	puts("Could not get board ID.\n");
e363426e	425
0660481a HS	426	enable_board_pin_mux(&header);
0660481a HS	427	}
e363426e	428
0660481a HS	429	void sdram_init(void)
	430	{
	431	__maybe_unused struct am335x_baseboard_id header;
95cb69fa	432
ace4275e	433	if (read_eeprom(&header) < 0)
e363426e PK	434	puts("Could not get board ID.\n");
e363426e PK	435
ace4275e	436	if (board_is_evm_sk(&header)) {
e363426e PK	437	/*
	438	* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
	439	* This is safe enough to do on older revs.
	440	*/
	441	gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
	442	gpio_direction_output(GPIO_DDR_VTT_EN, 1);
	443	}
	444
ace4275e	445	if (board_is_evm_sk(&header))
c7d35bef	446	config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
3ba65f97	447	&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
ace4275e	448	else if (board_is_bone_lt(&header))
b996a3e9	449	config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
c7ba18ad TR	450	&ddr3_beagleblack_data,
	451	&ddr3_beagleblack_cmd_ctrl_data,
	452	&ddr3_beagleblack_emif_reg_data, 0);
ace4275e	453	else if (board_is_evm_15_or_later(&header))
13526f71	454	config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
3ba65f97	455	&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
c00f69db	456	else
c7d35bef	457	config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
3ba65f97	458	&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
e363426e	459	}
0660481a	460	#endif
e363426e PK	461
	462	/*
	463	* Basic board specific setup. Pinmux has been handled already.
	464	*/
	465	int board_init(void)
	466	{
6843918e TR	467	#if defined(CONFIG_HW_WATCHDOG)
	468	hw_watchdog_init();
	469	#endif
	470
73feefdc	471	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
2c17e6d1	472	#if defined(CONFIG_NOR) \|\| defined(CONFIG_NAND)
98b5c269	473	gpmc_init();
cd8845d7	474	#endif
e363426e PK	475	return 0;
	476	}
	477
044fc14b TR	478	#ifdef CONFIG_BOARD_LATE_INIT
	479	int board_late_init(void)
	480	{
	481	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	482	char safe_string[HDR_NAME_LEN + 1];
ace4275e TR	483	struct am335x_baseboard_id header;
	484
	485	if (read_eeprom(&header) < 0)
	486	puts("Could not get board ID.\n");
044fc14b TR	487
	488	/* Now set variables based on the header. */
	489	strncpy(safe_string, (char *)header.name, sizeof(header.name));
	490	safe_string[sizeof(header.name)] = 0;
	491	setenv("board_name", safe_string);
	492
	493	strncpy(safe_string, (char *)header.version, sizeof(header.version));
	494	safe_string[sizeof(header.version)] = 0;
	495	setenv("board_rev", safe_string);
	496	#endif
	497
	498	return 0;
	499	}
	500	#endif
	501
c0e66793 IY	502	#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) \|\| \
c0e66793 IY	503	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
e363426e PK	504	static void cpsw_control(int enabled)
	505	{
	506	/* VTP can be added here */
	507
	508	return;
	509	}
	510
	511	static struct cpsw_slave_data cpsw_slaves[] = {
	512	{
	513	.slave_reg_ofs = 0x208,
	514	.sliver_reg_ofs = 0xd80,
	515	.phy_id = 0,
	516	},
	517	{
	518	.slave_reg_ofs = 0x308,
	519	.sliver_reg_ofs = 0xdc0,
	520	.phy_id = 1,
	521	},
	522	};
	523
	524	static struct cpsw_platform_data cpsw_data = {
81df2bab MP	525	.mdio_base = CPSW_MDIO_BASE,
81df2bab MP	526	.cpsw_base = CPSW_BASE,
e363426e PK	527	.mdio_div = 0xff,
	528	.channels = 8,
	529	.cpdma_reg_ofs = 0x800,
	530	.slaves = 1,
	531	.slave_data = cpsw_slaves,
	532	.ale_reg_ofs = 0xd00,
	533	.ale_entries = 1024,
	534	.host_port_reg_ofs = 0x108,
	535	.hw_stats_reg_ofs = 0x900,
2bf36ac6	536	.bd_ram_ofs = 0x2000,
e363426e PK	537	.mac_control = (1 << 5),
	538	.control = cpsw_control,
	539	.host_port_num = 0,
	540	.version = CPSW_CTRL_VERSION_2,
	541	};
d2aa1154	542	#endif
e363426e	543
d2aa1154 IY	544	#if defined(CONFIG_DRIVER_TI_CPSW) \|\| \
d2aa1154 IY	545	(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
e363426e PK	546	int board_eth_init(bd_t *bis)
e363426e PK	547	{
d2aa1154	548	int rv, n = 0;
e363426e PK	549	uint8_t mac_addr[6];
e363426e PK	550	uint32_t mac_hi, mac_lo;
ace4275e	551	__maybe_unused struct am335x_baseboard_id header;
e363426e	552
c0e66793 IY	553	/* try reading mac address from efuse */
	554	mac_lo = readl(&cdev->macid0l);
	555	mac_hi = readl(&cdev->macid0h);
	556	mac_addr[0] = mac_hi & 0xFF;
	557	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	558	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
	559	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
	560	mac_addr[4] = mac_lo & 0xFF;
	561	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
	562
	563	#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) \|\| \
	564	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
	565	if (!getenv("ethaddr")) {
	566	printf("<ethaddr> not set. Validating first E-fuse MAC\n");
e363426e PK	567
	568	if (is_valid_ether_addr(mac_addr))
	569	eth_setenv_enetaddr("ethaddr", mac_addr);
e363426e PK	570	}
e363426e PK	571
a662e0c3	572	#ifdef CONFIG_DRIVER_TI_CPSW
ace4275e TR	573	if (read_eeprom(&header) < 0)
	574	puts("Could not get board ID.\n");
	575
	576	if (board_is_bone(&header) \|\| board_is_bone_lt(&header) \|\|
	577	board_is_idk(&header)) {
e363426e PK	578	writel(MII_MODE_ENABLE, &cdev->miisel);
	579	cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
	580	PHY_INTERFACE_MODE_MII;
	581	} else {
dafd4db3	582	writel((RGMII_MODE_ENABLE \| RGMII_INT_DELAY), &cdev->miisel);
e363426e PK	583	cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
	584	PHY_INTERFACE_MODE_RGMII;
	585	}
	586
d2aa1154 IY	587	rv = cpsw_register(&cpsw_data);
	588	if (rv < 0)
	589	printf("Error %d registering CPSW switch\n", rv);
	590	else
	591	n += rv;
a662e0c3	592	#endif
1634e969 TR	593
	594	/*
	595	*
	596	* CPSW RGMII Internal Delay Mode is not supported in all PVT
	597	* operating points. So we must set the TX clock delay feature
	598	* in the AR8051 PHY. Since we only support a single ethernet
	599	* device in U-Boot, we only do this for the first instance.
	600	*/
	601	#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
	602	#define AR8051_PHY_DEBUG_DATA_REG 0x1e
	603	#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
	604	#define AR8051_RGMII_TX_CLK_DLY 0x100
	605
ace4275e	606	if (board_is_evm_sk(&header) \|\| board_is_gp_evm(&header)) {
1634e969 TR	607	const char *devname;
	608	devname = miiphy_get_current_dev();
	609
	610	miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
	611	AR8051_DEBUG_RGMII_CLK_DLY_REG);
	612	miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
	613	AR8051_RGMII_TX_CLK_DLY);
	614	}
d2aa1154	615	#endif
c0e66793 IY	616	#if defined(CONFIG_USB_ETHER) && \
	617	(!defined(CONFIG_SPL_BUILD) \|\| defined(CONFIG_SPL_USBETH_SUPPORT))
	618	if (is_valid_ether_addr(mac_addr))
	619	eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
	620
d2aa1154 IY	621	rv = usb_eth_initialize(bis);
	622	if (rv < 0)
	623	printf("Error %d registering USB_ETHER\n", rv);
	624	else
	625	n += rv;
	626	#endif
	627	return n;
e363426e PK	628	}
e363426e PK	629	#endif