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ti814x_evm: enable CPSW support
[u-boot.git] / board / cm_t35 / cm_t35.c
CommitLineData
36b4e2dd 1/*
ce15ec9f 2 * (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il>
36b4e2dd 3 *
dccd9a0b
IG		 4 * Authors: Mike Rapoport <[email protected]>
5 * Igor Grinberg <[email protected]>
36b4e2dd
MR		 6 *
7 * Derived from omap3evm and Beagle Board by
8 * Manikandan Pillai <[email protected]>
9 * Richard Woodruff <[email protected]>
10 * Syed Mohammed Khasim <[email protected]>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
dccd9a0b 27 * Foundation, Inc.
36b4e2dd
MR		 28 */
29
30#include <common.h>
2b8754b2 31#include <status_led.h>
36b4e2dd
MR		 32#include <netdev.h>
33#include <net.h>
34#include <i2c.h>
854a7836 35#include <usb.h>
5c1214de 36#include <mmc.h>
f35034fe 37#include <nand.h>
36b4e2dd 38#include <twl4030.h>
f35034fe 39#include <bmp_layout.h>
82309250 40#include <linux/compiler.h>
36b4e2dd
MR		 41
42#include <asm/io.h>
43#include <asm/arch/mem.h>
44#include <asm/arch/mux.h>
45#include <asm/arch/mmc_host_def.h>
46#include <asm/arch/sys_proto.h>
47#include <asm/mach-types.h>
854a7836
NK		 48#include <asm/ehci-omap.h>
49#include <asm/gpio.h>
36b4e2dd 50
e4e2bf5e
NK		 51#include "eeprom.h"
52
557aa155
IG		 53DECLARE_GLOBAL_DATA_PTR;
54
36b4e2dd
MR		 55const omap3_sysinfo sysinfo = {
56 DDR_DISCRETE,
b65a77a8 57 "CM-T3x board",
36b4e2dd
MR		 58 "NAND",
59};
60
61static u32 gpmc_net_config[GPMC_MAX_REG] = {
62 NET_GPMC_CONFIG1,
63 NET_GPMC_CONFIG2,
64 NET_GPMC_CONFIG3,
65 NET_GPMC_CONFIG4,
66 NET_GPMC_CONFIG5,
67 NET_GPMC_CONFIG6,
68 0
69};
70
71static u32 gpmc_nand_config[GPMC_MAX_REG] = {
72 SMNAND_GPMC_CONFIG1,
73 SMNAND_GPMC_CONFIG2,
74 SMNAND_GPMC_CONFIG3,
75 SMNAND_GPMC_CONFIG4,
76 SMNAND_GPMC_CONFIG5,
77 SMNAND_GPMC_CONFIG6,
78 0,
79};
80
f35034fe
NK		 81#ifdef CONFIG_LCD
82#ifdef CONFIG_CMD_NAND
83static int splash_load_from_nand(u32 bmp_load_addr)
84{
85 struct bmp_header *bmp_hdr;
86 int res, splash_screen_nand_offset = 0x100000;
87 size_t bmp_size, bmp_header_size = sizeof(struct bmp_header);
88
89 if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp)
90 goto splash_address_too_high;
91
92 res = nand_read_skip_bad(&nand_info[nand_curr_device],
93 splash_screen_nand_offset, &bmp_header_size,
c39d6a0e 94 NULL, nand_info[nand_curr_device].size,
f35034fe
NK		 95 (u_char *)bmp_load_addr);
96 if (res < 0)
97 return res;
98
99 bmp_hdr = (struct bmp_header *)bmp_load_addr;
100 bmp_size = le32_to_cpu(bmp_hdr->file_size);
101
102 if (bmp_load_addr + bmp_size >= gd->start_addr_sp)
103 goto splash_address_too_high;
104
105 return nand_read_skip_bad(&nand_info[nand_curr_device],
106 splash_screen_nand_offset, &bmp_size,
c39d6a0e 107 NULL, nand_info[nand_curr_device].size,
f35034fe
NK		 108 (u_char *)bmp_load_addr);
109
110splash_address_too_high:
111 printf("Error: splashimage address too high. Data overwrites U-Boot "
112 "and/or placed beyond DRAM boundaries.\n");
113
114 return -1;
115}
116#else
117static inline int splash_load_from_nand(void)
118{
119 return -1;
120}
121#endif /* CONFIG_CMD_NAND */
122
123int board_splash_screen_prepare(void)
124{
125 char *env_splashimage_value;
126 u32 bmp_load_addr;
127
128 env_splashimage_value = getenv("splashimage");
129 if (env_splashimage_value == NULL)
130 return -1;
131
132 bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16);
133 if (bmp_load_addr == 0) {
134 printf("Error: bad splashimage address specified\n");
135 return -1;
136 }
137
138 return splash_load_from_nand(bmp_load_addr);
139}
140#endif /* CONFIG_LCD */
141
36b4e2dd
MR		 142/*
143 * Routine: board_init
64f10847 144 * Description: hardware init.
36b4e2dd
MR		 145 */
146int board_init(void)
147{
36b4e2dd
MR		 148 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
149
150 enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0],
151 CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M);
152
153 /* board id for Linux */
b65a77a8
IG		 154 if (get_cpu_family() == CPU_OMAP34XX)
155 gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
156 else
157 gd->bd->bi_arch_number = MACH_TYPE_CM_T3730;
158
36b4e2dd
MR		 159 /* boot param addr */
160 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
161
2b8754b2
IG		 162#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
163 status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
164#endif
165
36b4e2dd
MR		 166 return 0;
167}
168
8c318eb3
NK		 169static u32 cm_t3x_rev;
170
171/*
172 * Routine: get_board_rev
173 * Description: read system revision
174 */
175u32 get_board_rev(void)
176{
177 if (!cm_t3x_rev)
178 cm_t3x_rev = cm_t3x_eeprom_get_board_rev();
179
180 return cm_t3x_rev;
181};
182
183/*
184 * Routine: misc_init_r
185 * Description: display die ID
186 */
187int misc_init_r(void)
188{
189 u32 board_rev = get_board_rev();
190 u32 rev_major = board_rev / 100;
191 u32 rev_minor = board_rev - (rev_major * 100);
192
193 if ((rev_minor / 10) * 10 == rev_minor)
194 rev_minor = rev_minor / 10;
195
196 printf("PCB: %u.%u\n", rev_major, rev_minor);
197 dieid_num_r();
198
199 return 0;
200}
201
36b4e2dd
MR		 202/*
203 * Routine: set_muxconf_regs
204 * Description: Setting up the configuration Mux registers specific to the
205 * hardware. Many pins need to be moved from protect to primary
206 * mode.
207 */
b65a77a8 208static void cm_t3x_set_common_muxconf(void)
36b4e2dd
MR		 209{
210 /* SDRC */
211 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/
212 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/
213 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/
214 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/
215 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/
216 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/
217 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/
218 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/
219 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/
220 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/
221 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/
222 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/
223 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/
224 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/
225 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/
226 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/
227 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/
228 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/
229 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/
230 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/
231 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/
232 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/
233 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/
234 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/
235 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/
236 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/
237 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/
238 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/
239 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/
240 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/
241 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/
242 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/
243 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/
244 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/
245 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/
246 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/
247 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/
248 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/
249 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/
250
251 /* GPMC */
252 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/
253 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/
254 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/
255 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/
256 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/
257 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/
258 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/
259 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/
260 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/
261 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/
262 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/
263 MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/
264 MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/
265 MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/
266 MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/
267 MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/
268 MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/
269 MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/
270 MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/
271 MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/
272 MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/
273 MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/
274 MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/
275 MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/
276 MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/
277 MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/
278 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/
279
280 /* SB-T35 Ethernet */
281 MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
282
7878ca51
NK		 283 /* DVI enable */
284 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/
285
b65a77a8 286 /* CM-T3x Ethernet */
36b4e2dd
MR		 287 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
288 MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/
289 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/
290 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/
291 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/
292 MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/
293 MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/
294 MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/
295 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/
296
297 /* DSS */
298 MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/
299 MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/
300 MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/
301 MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/
36b4e2dd
MR		 302 MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/
303 MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/
304 MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/
305 MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/
306 MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/
307 MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/
308 MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/
309 MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/
310 MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/
311 MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/
312 MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/
313 MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/
36b4e2dd
MR		 314
315 /* serial interface */
316 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/
317 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/
318
319 /* mUSB */
320 MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/
321 MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/
322 MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/
323 MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/
324 MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/
325 MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/
326 MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/
327 MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/
328 MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/
329 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/
330 MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/
331 MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/
332
854a7836
NK		 333 /* USB EHCI */
334 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/
335 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/
336 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/
337 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/
338 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/
339 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/
340 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/
341 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/
342 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/
343 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/
344 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/
345 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/
346
347 MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/
348 MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/
349 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/
350 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/
351 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/
352 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/
353 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/
354 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/
355 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/
356 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/
357 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/
358 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
359
360 /* SB_T35_USB_HUB_RESET_GPIO */
361 MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)); /*GPIO_167*/
362
36b4e2dd
MR		 363 /* I2C1 */
364 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/
365 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/
79874ae9
NK		 366 /* I2C2 */
367 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/
368 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/
369 /* I2C3 */
370 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/
371 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/
36b4e2dd
MR		 372
373 /* control and debug */
374 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/
375 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/
376 MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/
377 MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/
378 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/
2b8754b2 379 MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/
36b4e2dd
MR		 380 MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/
381 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
382 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
383 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
eec70c2d
IG		 384
385 /* MMC1 */
386 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/
387 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/
388 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/
389 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
390 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
391 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
b65a77a8
IG		 392}
393
394static void cm_t35_set_muxconf(void)
395{
396 /* DSS */
397 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/
398 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/
399 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/
400 MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/
401 MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/
402 MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/
403
404 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/
405 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/
406 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/
407 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/
408 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/
409 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/
410
411 /* MMC1 */
eec70c2d
IG		 412 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/
413 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/
414 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/
415 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/
36b4e2dd
MR		 416}
417
b65a77a8
IG		 418static void cm_t3730_set_muxconf(void)
419{
420 /* DSS */
421 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/
422 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/
423 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/
424 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/
425 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/
426 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/
427
428 MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/
429 MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/
430 MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/
431 MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/
432 MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/
433 MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/
434}
435
436void set_muxconf_regs(void)
437{
438 cm_t3x_set_common_muxconf();
439
440 if (get_cpu_family() == CPU_OMAP34XX)
441 cm_t35_set_muxconf();
442 else
443 cm_t3730_set_muxconf();
444}
445
28fed362 446#ifdef CONFIG_GENERIC_MMC
5c1214de
NK		 447int board_mmc_getcd(struct mmc *mmc)
448{
449 u8 val;
450
451 if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, &val, TWL4030_BASEADD_GPIO))
452 return -1;
453
454 return !(val & 1);
455}
456
28fed362
TR		 457int board_mmc_init(bd_t *bis)
458{
e3913f56 459 return omap_mmc_init(0, 0, 0, -1, 59);
28fed362
TR		 460}
461#endif
462
36b4e2dd
MR		 463/*
464 * Routine: setup_net_chip_gmpc
465 * Description: Setting up the configuration GPMC registers specific to the
466 * Ethernet hardware.
467 */
468static void setup_net_chip_gmpc(void)
469{
470 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
471
472 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5],
b65a77a8 473 CM_T3X_SMC911X_BASE, GPMC_SIZE_16M);
36b4e2dd
MR		 474 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4],
475 SB_T35_SMC911X_BASE, GPMC_SIZE_16M);
476
477 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
478 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
479
480 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
481 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
482
483 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
484 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
485 &ctrl_base->gpmc_nadv_ale);
486}
487
488#ifdef CONFIG_DRIVER_OMAP34XX_I2C
489/*
490 * Routine: reset_net_chip
491 * Description: reset the Ethernet controller via TPS65930 GPIO
492 */
493static void reset_net_chip(void)
494{
495 /* Set GPIO1 of TPS65930 as output */
496 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
07277e74 497 TWL4030_BASEADD_GPIO + 0x03);
36b4e2dd
MR		 498 /* Send a pulse on the GPIO pin */
499 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
07277e74 500 TWL4030_BASEADD_GPIO + 0x0C);
36b4e2dd
MR		 501 udelay(1);
502 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
07277e74
IG		 503 TWL4030_BASEADD_GPIO + 0x09);
504 mdelay(40);
36b4e2dd 505 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
07277e74
IG		 506 TWL4030_BASEADD_GPIO + 0x0C);
507 mdelay(1);
36b4e2dd
MR		 508}
509#else
510static inline void reset_net_chip(void) {}
511#endif
512
ce15ec9f 513#ifdef CONFIG_SMC911X
36b4e2dd
MR		 514/*
515 * Routine: handle_mac_address
516 * Description: prepare MAC address for on-board Ethernet.
517 */
518static int handle_mac_address(void)
519{
520 unsigned char enetaddr[6];
521 int rc;
522
523 rc = eth_getenv_enetaddr("ethaddr", enetaddr);
524 if (rc)
525 return 0;
526
e4e2bf5e 527 rc = cm_t3x_eeprom_read_mac_addr(enetaddr);
36b4e2dd
MR		 528 if (rc)
529 return rc;
36b4e2dd
MR		 530
531 if (!is_valid_ether_addr(enetaddr))
532 return -1;
533
534 return eth_setenv_enetaddr("ethaddr", enetaddr);
535}
536
537
538/*
539 * Routine: board_eth_init
540 * Description: initialize module and base-board Ethernet chips
541 */
542int board_eth_init(bd_t *bis)
543{
544 int rc = 0, rc1 = 0;
545
36b4e2dd
MR		 546 setup_net_chip_gmpc();
547 reset_net_chip();
548
549 rc1 = handle_mac_address();
550 if (rc1)
64f10847 551 printf("No MAC address found! ");
36b4e2dd 552
b65a77a8 553 rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE);
36b4e2dd
MR		 554 if (rc1 > 0)
555 rc++;
556
557 rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE);
558 if (rc1 > 0)
559 rc++;
36b4e2dd
MR		 560
561 return rc;
562}
ce15ec9f 563#endif
82309250
NK		 564
565void __weak get_board_serial(struct tag_serialnr *serialnr)
566{
567 /*
568 * This corresponds to what happens when we can communicate with the
569 * eeprom but don't get a valid board serial value.
570 */
571 serialnr->low = 0;
572 serialnr->high = 0;
573};
854a7836
NK		 574
575#ifdef CONFIG_USB_EHCI_OMAP
576struct omap_usbhs_board_data usbhs_bdata = {
577 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
578 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
579 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
580};
581
582#define SB_T35_USB_HUB_RESET_GPIO 167
41984e71 583int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
854a7836
NK		 584{
585 u8 val;
586 int offset;
587
588 if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) {
589 printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset",
590 SB_T35_USB_HUB_RESET_GPIO);
591 return -1;
592 }
593
594 gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0);
595 udelay(10);
596 gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
597 udelay(1000);
598
599 offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1;
600 twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, &val, offset);
601 /* Set GPIO6 and GPIO7 of TPS65930 as output */
602 val |= 0xC0;
603 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, val, offset);
604 offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1;
605 /* Take both PHYs out of reset */
606 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0xC0, offset);
607 udelay(1);
608
41984e71 609 return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
854a7836
NK		 610}
611
612int ehci_hcd_stop(void)
613{
614 return omap_ehci_hcd_stop();
615}
616
617#endif /* CONFIG_USB_EHCI_OMAP */
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