[u-boot.git] / arch / arm / mach-rockchip / board.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
 */
#include <common.h>
#include <clk.h>
#include <cpu_func.h>
#include <dm.h>
#include <efi_loader.h>
#include <fastboot.h>
#include <init.h>
#include <log.h>
#include <mmc.h>
#include <part.h>
#include <ram.h>
#include <syscon.h>
#include <uuid.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-rockchip/boot_mode.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/periph.h>
#include <asm/arch-rockchip/misc.h>
#include <power/regulator.h>

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION)

#define DFU_ALT_BUF_LEN			SZ_1K

static struct efi_fw_image *fw_images;

static bool updatable_image(struct disk_partition *info)
{
	int i;
	bool ret = false;
	efi_guid_t image_type_guid;

	uuid_str_to_bin(info->type_guid, image_type_guid.b,
			UUID_STR_FORMAT_GUID);

	for (i = 0; i < update_info.num_images; i++) {
		if (!guidcmp(&fw_images[i].image_type_id, &image_type_guid)) {
			ret = true;
			break;
		}
	}

	return ret;
}

static void set_image_index(struct disk_partition *info, int index)
{
	int i;
	efi_guid_t image_type_guid;

	uuid_str_to_bin(info->type_guid, image_type_guid.b,
			UUID_STR_FORMAT_GUID);

	for (i = 0; i < update_info.num_images; i++) {
		if (!guidcmp(&fw_images[i].image_type_id, &image_type_guid)) {
			fw_images[i].image_index = index;
			break;
		}
	}
}

static int get_mmc_desc(struct blk_desc **desc)
{
	int ret;
	struct mmc *mmc;
	struct udevice *dev;

	/*
	 * For now the firmware images are assumed to
	 * be on the SD card
	 */
	ret = uclass_get_device(UCLASS_MMC, 1, &dev);
	if (ret)
		return -1;

	mmc = mmc_get_mmc_dev(dev);
	if (!mmc)
		return -ENODEV;

	if ((ret = mmc_init(mmc)))
		return ret;

	*desc = mmc_get_blk_desc(mmc);
	if (!*desc)
		return -1;

	return 0;
}

void set_dfu_alt_info(char *interface, char *devstr)
{
	const char *name;
	bool first = true;
	int p, len, devnum, ret;
	char buf[DFU_ALT_BUF_LEN];
	struct disk_partition info;
	struct blk_desc *desc = NULL;

	ret = get_mmc_desc(&desc);
	if (ret) {
		log_err("Unable to get mmc desc\n");
		return;
	}

	memset(buf, 0, sizeof(buf));
	name = blk_get_uclass_name(desc->uclass_id);
	devnum = desc->devnum;
	len = strlen(buf);

	len += snprintf(buf + len, DFU_ALT_BUF_LEN - len,
			 "%s %d=", name, devnum);

	for (p = 1; p <= MAX_SEARCH_PARTITIONS; p++) {
		if (part_get_info(desc, p, &info))
			continue;

		/* Add entry to dfu_alt_info only for updatable images */
		if (updatable_image(&info)) {
			if (!first)
				len += snprintf(buf + len,
						DFU_ALT_BUF_LEN - len, ";");

			len += snprintf(buf + len, DFU_ALT_BUF_LEN - len,
					"%s%d_%s part %d %d",
					name, devnum, info.name, devnum, p);
			first = false;
		}
	}

	log_debug("dfu_alt_info => %s\n", buf);
	env_set("dfu_alt_info", buf);
}

static void gpt_capsule_update_setup(void)
{
	int p, i, ret;
	struct disk_partition info;
	struct blk_desc *desc = NULL;

	fw_images = update_info.images;
	rockchip_capsule_update_board_setup();

	ret = get_mmc_desc(&desc);
	if (ret) {
		log_err("Unable to get mmc desc\n");
		return;
	}

	for (p = 1, i = 1; p <= MAX_SEARCH_PARTITIONS; p++) {
		if (part_get_info(desc, p, &info))
			continue;

		/*
		 * Since we have a GPT partitioned device, the updatable
		 * images could be stored in any order. Populate the
		 * image_index at runtime.
		 */
		if (updatable_image(&info)) {
			set_image_index(&info, i);
			i++;
		}
	}
}
#endif /* CONFIG_EFI_HAVE_CAPSULE_SUPPORT && CONFIG_EFI_PARTITION */

__weak int rk_board_late_init(void)
{
#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION)
	gpt_capsule_update_setup();
#endif

	return 0;
}

int board_late_init(void)
{
	setup_boot_mode();

	return rk_board_late_init();
}

int board_init(void)
{
	int ret;

#ifdef CONFIG_DM_REGULATOR
	ret = regulators_enable_boot_on(false);
	if (ret)
		debug("%s: Cannot enable boot on regulator\n", __func__);
#endif

	return 0;
}

#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
{
	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();
}
#endif

#if defined(CONFIG_USB_GADGET)
#include <usb.h>

#if defined(CONFIG_USB_GADGET_DWC2_OTG)
#include <usb/dwc2_udc.h>

static struct dwc2_plat_otg_data otg_data = {
	.rx_fifo_sz	= 512,
	.np_tx_fifo_sz	= 16,
	.tx_fifo_sz	= 128,
};

int board_usb_init(int index, enum usb_init_type init)
{
	ofnode node;
	const char *mode;
	bool matched = false;

	/* find the usb_otg node */
	node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
	while (ofnode_valid(node)) {
		mode = ofnode_read_string(node, "dr_mode");
		if (mode && strcmp(mode, "otg") == 0) {
			matched = true;
			break;
		}

		node = ofnode_by_compatible(node, "snps,dwc2");
	}
	if (!matched) {
		debug("Not found usb_otg device\n");
		return -ENODEV;
	}
	otg_data.regs_otg = ofnode_get_addr(node);

#ifdef CONFIG_ROCKCHIP_USB2_PHY
	int ret;
	u32 phandle, offset;
	ofnode phy_node;

	ret = ofnode_read_u32(node, "phys", &phandle);
	if (ret)
		return ret;

	node = ofnode_get_by_phandle(phandle);
	if (!ofnode_valid(node)) {
		debug("Not found usb phy device\n");
		return -ENODEV;
	}

	phy_node = ofnode_get_parent(node);
	if (!ofnode_valid(node)) {
		debug("Not found usb phy device\n");
		return -ENODEV;
	}

	otg_data.phy_of_node = phy_node;
	ret = ofnode_read_u32(node, "reg", &offset);
	if (ret)
		return ret;
	otg_data.regs_phy =  offset +
		(u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
#endif
	return dwc2_udc_probe(&otg_data);
}

int board_usb_cleanup(int index, enum usb_init_type init)
{
	return 0;
}
#endif /* CONFIG_USB_GADGET_DWC2_OTG */

#if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET)
#include <dwc3-uboot.h>

static struct dwc3_device dwc3_device_data = {
	.maximum_speed = USB_SPEED_HIGH,
	.base = 0xfe800000,
	.dr_mode = USB_DR_MODE_PERIPHERAL,
	.index = 0,
	.dis_u2_susphy_quirk = 1,
	.hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
};

int usb_gadget_handle_interrupts(int index)
{
	dwc3_uboot_handle_interrupt(0);
	return 0;
}

int board_usb_init(int index, enum usb_init_type init)
{
	return dwc3_uboot_init(&dwc3_device_data);
}
#endif /* CONFIG_USB_DWC3_GADGET */

#endif /* CONFIG_USB_GADGET */

#if IS_ENABLED(CONFIG_FASTBOOT)
int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
{
	if (reason != FASTBOOT_REBOOT_REASON_BOOTLOADER)
		return -ENOTSUPP;

	printf("Setting reboot to fastboot flag ...\n");
	/* Set boot mode to fastboot */
	writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);

	return 0;
}
#endif

#ifdef CONFIG_MISC_INIT_R
__weak int misc_init_r(void)
{
	const u32 cpuid_offset = CFG_CPUID_OFFSET;
	const u32 cpuid_length = 0x10;
	u8 cpuid[cpuid_length];
	int ret;

	ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
	if (ret)
		return ret;

	ret = rockchip_cpuid_set(cpuid, cpuid_length);
	if (ret)
		return ret;

	ret = rockchip_setup_macaddr();

	return ret;
}
#endif
Commit	Line	Data
54f17fa0 KY	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* (C) Copyright 2019 Rockchip Electronics Co., Ltd.
	4	*/
	5	#include <common.h>
	6	#include <clk.h>
9edefc27	7	#include <cpu_func.h>
54f17fa0	8	#include <dm.h>
bea9267d	9	#include <efi_loader.h>
851737ab	10	#include <fastboot.h>
5255932f	11	#include <init.h>
f7ae49fc	12	#include <log.h>
bea9267d SG	13	#include <mmc.h>
bea9267d SG	14	#include <part.h>
54f17fa0 KY	15	#include <ram.h>
54f17fa0 KY	16	#include <syscon.h>
bea9267d	17	#include <uuid.h>
90526e9f	18	#include <asm/cache.h>
401d1c4f	19	#include <asm/global_data.h>
54f17fa0 KY	20	#include <asm/io.h>
	21	#include <asm/arch-rockchip/boot_mode.h>
	22	#include <asm/arch-rockchip/clock.h>
	23	#include <asm/arch-rockchip/periph.h>
04825384	24	#include <asm/arch-rockchip/misc.h>
54f17fa0 KY	25	#include <power/regulator.h>
	26
	27	DECLARE_GLOBAL_DATA_PTR;
	28
bea9267d SG	29	#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION)
	30
	31	#define DFU_ALT_BUF_LEN SZ_1K
	32
	33	static struct efi_fw_image *fw_images;
	34
	35	static bool updatable_image(struct disk_partition *info)
	36	{
	37	int i;
	38	bool ret = false;
	39	efi_guid_t image_type_guid;
	40
	41	uuid_str_to_bin(info->type_guid, image_type_guid.b,
	42	UUID_STR_FORMAT_GUID);
	43
cccea188	44	for (i = 0; i < update_info.num_images; i++) {
bea9267d SG	45	if (!guidcmp(&fw_images[i].image_type_id, &image_type_guid)) {
	46	ret = true;
	47	break;
	48	}
	49	}
	50
	51	return ret;
	52	}
	53
	54	static void set_image_index(struct disk_partition *info, int index)
	55	{
	56	int i;
	57	efi_guid_t image_type_guid;
	58
	59	uuid_str_to_bin(info->type_guid, image_type_guid.b,
	60	UUID_STR_FORMAT_GUID);
	61
cccea188	62	for (i = 0; i < update_info.num_images; i++) {
bea9267d SG	63	if (!guidcmp(&fw_images[i].image_type_id, &image_type_guid)) {
	64	fw_images[i].image_index = index;
	65	break;
	66	}
	67	}
	68	}
	69
	70	static int get_mmc_desc(struct blk_desc **desc)
	71	{
	72	int ret;
	73	struct mmc *mmc;
	74	struct udevice *dev;
	75
	76	/*
	77	* For now the firmware images are assumed to
	78	* be on the SD card
	79	*/
	80	ret = uclass_get_device(UCLASS_MMC, 1, &dev);
	81	if (ret)
	82	return -1;
	83
	84	mmc = mmc_get_mmc_dev(dev);
	85	if (!mmc)
	86	return -ENODEV;
	87
	88	if ((ret = mmc_init(mmc)))
	89	return ret;
	90
	91	*desc = mmc_get_blk_desc(mmc);
	92	if (!*desc)
	93	return -1;
	94
	95	return 0;
	96	}
	97
	98	void set_dfu_alt_info(char interface, char devstr)
	99	{
	100	const char *name;
	101	bool first = true;
	102	int p, len, devnum, ret;
	103	char buf[DFU_ALT_BUF_LEN];
	104	struct disk_partition info;
	105	struct blk_desc *desc = NULL;
	106
	107	ret = get_mmc_desc(&desc);
	108	if (ret) {
	109	log_err("Unable to get mmc desc\n");
	110	return;
	111	}
	112
	113	memset(buf, 0, sizeof(buf));
	114	name = blk_get_uclass_name(desc->uclass_id);
	115	devnum = desc->devnum;
	116	len = strlen(buf);
	117
	118	len += snprintf(buf + len, DFU_ALT_BUF_LEN - len,
	119	"%s %d=", name, devnum);
	120
	121	for (p = 1; p <= MAX_SEARCH_PARTITIONS; p++) {
	122	if (part_get_info(desc, p, &info))
	123	continue;
	124
	125	/* Add entry to dfu_alt_info only for updatable images */
	126	if (updatable_image(&info)) {
127	if (!first)
128	len += snprintf(buf + len,
129	DFU_ALT_BUF_LEN - len, ";");
130
131	len += snprintf(buf + len, DFU_ALT_BUF_LEN - len,
132	"%s%d_%s part %d %d",
133	name, devnum, info.name, devnum, p);
134	first = false;
135	}
136	}
137
138	log_debug("dfu_alt_info => %s\n", buf);
139	env_set("dfu_alt_info", buf);
140	}
141
142	static void gpt_capsule_update_setup(void)
143	{
144	int p, i, ret;
145	struct disk_partition info;
146	struct blk_desc *desc = NULL;
147
148	fw_images = update_info.images;
149	rockchip_capsule_update_board_setup();
150
151	ret = get_mmc_desc(&desc);
152	if (ret) {
153	log_err("Unable to get mmc desc\n");
154	return;
155	}
156
157	for (p = 1, i = 1; p <= MAX_SEARCH_PARTITIONS; p++) {
158	if (part_get_info(desc, p, &info))
159	continue;
160
161	/*
162	* Since we have a GPT partitioned device, the updatable
163	* images could be stored in any order. Populate the
164	* image_index at runtime.
165	*/
166	if (updatable_image(&info)) {
167	set_image_index(&info, i);
168	i++;
169	}
170	}
171	}
172	#endif /* CONFIG_EFI_HAVE_CAPSULE_SUPPORT && CONFIG_EFI_PARTITION */
173
54f17fa0 KY	174	__weak int rk_board_late_init(void)
54f17fa0 KY	175	{
bea9267d SG	176	#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION)
	177	gpt_capsule_update_setup();
	178	#endif
	179
54f17fa0 KY	180	return 0;
	181	}
	182
	183	int board_late_init(void)
	184	{
	185	setup_boot_mode();
	186
	187	return rk_board_late_init();
	188	}
	189
	190	int board_init(void)
	191	{
	192	int ret;
	193
	194	#ifdef CONFIG_DM_REGULATOR
	195	ret = regulators_enable_boot_on(false);
	196	if (ret)
	197	debug("%s: Cannot enable boot on regulator\n", __func__);
	198	#endif
	199
	200	return 0;
	201	}
	202
	203	#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
	204	void enable_caches(void)
	205	{
	206	/* Enable D-cache. I-cache is already enabled in start.S */
	207	dcache_enable();
	208	}
	209	#endif
	210
c618bb00	211	#if defined(CONFIG_USB_GADGET)
54f17fa0	212	#include <usb.h>
c618bb00 JT	213
c618bb00 JT	214	#if defined(CONFIG_USB_GADGET_DWC2_OTG)
54f17fa0 KY	215	#include <usb/dwc2_udc.h>
	216
	217	static struct dwc2_plat_otg_data otg_data = {
	218	.rx_fifo_sz = 512,
	219	.np_tx_fifo_sz = 16,
	220	.tx_fifo_sz = 128,
	221	};
	222
	223	int board_usb_init(int index, enum usb_init_type init)
	224	{
e76943ca	225	ofnode node;
54f17fa0 KY	226	const char *mode;
54f17fa0 KY	227	bool matched = false;
54f17fa0 KY	228
54f17fa0 KY	229	/* find the usb_otg node */
e76943ca KY	230	node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
	231	while (ofnode_valid(node)) {
	232	mode = ofnode_read_string(node, "dr_mode");
54f17fa0 KY	233	if (mode && strcmp(mode, "otg") == 0) {
	234	matched = true;
	235	break;
	236	}
	237
e76943ca	238	node = ofnode_by_compatible(node, "snps,dwc2");
54f17fa0 KY	239	}
	240	if (!matched) {
	241	debug("Not found usb_otg device\n");
	242	return -ENODEV;
	243	}
e76943ca	244	otg_data.regs_otg = ofnode_get_addr(node);
54f17fa0	245
e0479b71	246	#ifdef CONFIG_ROCKCHIP_USB2_PHY
17224b32 KY	247	int ret;
	248	u32 phandle, offset;
	249	ofnode phy_node;
	250
	251	ret = ofnode_read_u32(node, "phys", &phandle);
	252	if (ret)
	253	return ret;
	254
	255	node = ofnode_get_by_phandle(phandle);
	256	if (!ofnode_valid(node)) {
	257	debug("Not found usb phy device\n");
	258	return -ENODEV;
	259	}
	260
	261	phy_node = ofnode_get_parent(node);
	262	if (!ofnode_valid(node)) {
	263	debug("Not found usb phy device\n");
	264	return -ENODEV;
	265	}
	266
	267	otg_data.phy_of_node = phy_node;
	268	ret = ofnode_read_u32(node, "reg", &offset);
	269	if (ret)
	270	return ret;
	271	otg_data.regs_phy = offset +
	272	(u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	273	#endif
54f17fa0 KY	274	return dwc2_udc_probe(&otg_data);
	275	}
	276
	277	int board_usb_cleanup(int index, enum usb_init_type init)
	278	{
	279	return 0;
	280	}
c618bb00 JT	281	#endif /* CONFIG_USB_GADGET_DWC2_OTG */
	282
	283	#if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET)
	284	#include <dwc3-uboot.h>
	285
	286	static struct dwc3_device dwc3_device_data = {
	287	.maximum_speed = USB_SPEED_HIGH,
	288	.base = 0xfe800000,
	289	.dr_mode = USB_DR_MODE_PERIPHERAL,
	290	.index = 0,
	291	.dis_u2_susphy_quirk = 1,
	292	.hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
	293	};
	294
79dec66c	295	int usb_gadget_handle_interrupts(int index)
c618bb00 JT	296	{
	297	dwc3_uboot_handle_interrupt(0);
	298	return 0;
	299	}
	300
	301	int board_usb_init(int index, enum usb_init_type init)
	302	{
	303	return dwc3_uboot_init(&dwc3_device_data);
	304	}
	305	#endif /* CONFIG_USB_DWC3_GADGET */
	306
	307	#endif /* CONFIG_USB_GADGET */
54f17fa0	308
41782a9c	309	#if IS_ENABLED(CONFIG_FASTBOOT)
851737ab	310	int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
54f17fa0	311	{
851737ab RK	312	if (reason != FASTBOOT_REBOOT_REASON_BOOTLOADER)
	313	return -ENOTSUPP;
	314
54f17fa0 KY	315	printf("Setting reboot to fastboot flag ...\n");
	316	/* Set boot mode to fastboot */
	317	writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
	318
	319	return 0;
	320	}
	321	#endif
04825384 RG	322
	323	#ifdef CONFIG_MISC_INIT_R
	324	__weak int misc_init_r(void)
	325	{
2eedb6d9	326	const u32 cpuid_offset = CFG_CPUID_OFFSET;
04825384 RG	327	const u32 cpuid_length = 0x10;
	328	u8 cpuid[cpuid_length];
	329	int ret;
	330
	331	ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
	332	if (ret)
	333	return ret;
	334
	335	ret = rockchip_cpuid_set(cpuid, cpuid_length);
	336	if (ret)
	337	return ret;
	338
	339	ret = rockchip_setup_macaddr();
	340
	341	return ret;
	342	}
	343	#endif