[u-boot.git] / include / configs / pr1.h

/*
 * U-Boot - Configuration file for PR1 Appliance
 *
 * based on bf537-stamp.h
 * Copyright (c) Switchfin Org. <[email protected]>
 */

#ifndef __CONFIG_PR1_H__
#define __CONFIG_PR1_H__

#include <asm/config-pre.h>

/*
 * Processor Settings
 */
#define CONFIG_BFIN_CPU             bf537-0.3
#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER

/*
 * Clock Settings
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
 */
/* CONFIG_CLKIN_HZ is any value in Hz					*/
#define CONFIG_CLKIN_HZ			25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
/*                                                1 = CLKIN / 2		*/
#define CONFIG_CLKIN_HALF		0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
/*                                                1 = bypass PLL	*/
#define CONFIG_PLL_BYPASS		0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
/* Values can range from 0-63 (where 0 means 64)			*/
#define CONFIG_VCO_MULT			24
/* CCLK_DIV controls the core clock divider				*/
/* Values can be 1, 2, 4, or 8 ONLY					*/
#define CONFIG_CCLK_DIV			1
/* SCLK_DIV controls the system clock divider				*/
/* Values can range from 1-15						*/
#define CONFIG_SCLK_DIV			5

/*
 * Memory Settings
 */
#define CONFIG_MEM_ADD_WDTH	11
#define CONFIG_MEM_SIZE		128

#define CONFIG_EBIU_SDRRC_VAL	0x306
#define CONFIG_EBIU_SDGCTL_VAL	0x8091998d

#define CONFIG_EBIU_AMGCTL_VAL	0xFF
#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0

#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(384 * 1024)

/*
 * Network Settings
 */
#ifndef __ADSPBF534__
#define ADI_CMDS_NETWORK	1
#define CONFIG_BFIN_MAC
#define CONFIG_NETCONSOLE
#endif
#define CONFIG_HOSTNAME		pr1
#define CONFIG_TFTP_BLOCKSIZE	4404

/*
 * Flash Settings
 */
#define CONFIG_SYS_NO_FLASH	/* We have no parallel FLASH */

/*
 * SPI Settings
 */
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ	30000000
#define CONFIG_SF_DEFAULT_SPEED	30000000

/*
 * Env Storage Settings
 */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET	0x10000
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x10000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR

/*
 * I2C Settings
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI

/*
 * NAND Settings
 */
#define CONFIG_NAND_PLAT
#define CONFIG_SYS_NAND_BASE		0x20000000
#define CONFIG_SYS_MAX_NAND_DEVICE	1

#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
#define BFIN_NAND_WRITE(addr, cmd) \
	do { \
		bfin_write8(addr, cmd); \
		SSYNC(); \
	} while (0)

#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF9

/*
 * Misc Settings
 */
#define CONFIG_BAUDRATE		115200
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE	0
#define CONFIG_BOOTCOMMAND	"run nandboot"
#define CONFIG_BOOTDELAY	2
#define CONFIG_LOADADDR		0x2000000

/*
 * Pull in common ADI header for remaining command/environment setup
 */
#include <configs/bfin_adi_common.h>

/*
 * Overwrite some settings defined in bfin_adi_common.h
 */
#undef NAND_ENV_SETTINGS
#define NAND_ENV_SETTINGS \
	"nandargs=set bootargs " CONFIG_BOOTARGS "\0" \
	"nandboot=" \
		"nand read $(loadaddr) 0x0 0x900000;" \
		"run nandargs;" \
		"bootm" \
		"\0"

#endif
Commit	Line	Data
939b150a	1	/*
a187559e	2	* U-Boot - Configuration file for PR1 Appliance
939b150a DP	3	*
	4	* based on bf537-stamp.h
	5	* Copyright (c) Switchfin Org. <[email protected]>
	6	*/
	7
	8	#ifndef __CONFIG_PR1_H__
	9	#define __CONFIG_PR1_H__
	10
	11	#include <asm/config-pre.h>
	12
939b150a DP	13	/*
	14	* Processor Settings
	15	*/
	16	#define CONFIG_BFIN_CPU bf537-0.3
	17	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
	18
939b150a DP	19	/*
	20	* Clock Settings
	21	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	22	* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
	23	*/
	24	/* CONFIG_CLKIN_HZ is any value in Hz */
	25	#define CONFIG_CLKIN_HZ 25000000
	26	/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
	27	/* 1 = CLKIN / 2 */
	28	#define CONFIG_CLKIN_HALF 0
	29	/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
	30	/* 1 = bypass PLL */
	31	#define CONFIG_PLL_BYPASS 0
	32	/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
	33	/* Values can range from 0-63 (where 0 means 64) */
	34	#define CONFIG_VCO_MULT 24
	35	/* CCLK_DIV controls the core clock divider */
	36	/* Values can be 1, 2, 4, or 8 ONLY */
	37	#define CONFIG_CCLK_DIV 1
	38	/* SCLK_DIV controls the system clock divider */
	39	/* Values can range from 1-15 */
	40	#define CONFIG_SCLK_DIV 5
	41
939b150a DP	42	/*
	43	* Memory Settings
	44	*/
	45	#define CONFIG_MEM_ADD_WDTH 11
	46	#define CONFIG_MEM_SIZE 128
	47
	48	#define CONFIG_EBIU_SDRRC_VAL 0x306
	49	#define CONFIG_EBIU_SDGCTL_VAL 0x8091998d
	50
	51	#define CONFIG_EBIU_AMGCTL_VAL 0xFF
	52	#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
	53	#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
	54
	55	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	56	#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
	57
939b150a DP	58	/*
	59	* Network Settings
	60	*/
	61	#ifndef __ADSPBF534__
	62	#define ADI_CMDS_NETWORK 1
	63	#define CONFIG_BFIN_MAC
	64	#define CONFIG_NETCONSOLE
	65	#endif
	66	#define CONFIG_HOSTNAME pr1
	67	#define CONFIG_TFTP_BLOCKSIZE 4404
939b150a	68
939b150a DP	69	/*
	70	* Flash Settings
	71	*/
	72	#define CONFIG_SYS_NO_FLASH /* We have no parallel FLASH */
	73
939b150a DP	74	/*
	75	* SPI Settings
	76	*/
	77	#define CONFIG_BFIN_SPI
	78	#define CONFIG_ENV_SPI_MAX_HZ 30000000
	79	#define CONFIG_SF_DEFAULT_SPEED 30000000
939b150a	80
939b150a DP	81	/*
	82	* Env Storage Settings
	83	*/
	84	#define CONFIG_ENV_IS_IN_SPI_FLASH
	85	#define CONFIG_ENV_OFFSET 0x10000
	86	#define CONFIG_ENV_SIZE 0x2000
	87	#define CONFIG_ENV_SECT_SIZE 0x10000
	88	#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
	89
939b150a DP	90	/*
	91	* I2C Settings
	92	*/
c469703b	93	#define CONFIG_SYS_I2C
fea9b69a	94	#define CONFIG_SYS_I2C_ADI
939b150a	95
939b150a DP	96	/*
	97	* NAND Settings
	98	*/
	99	#define CONFIG_NAND_PLAT
	100	#define CONFIG_SYS_NAND_BASE 0x20000000
	101	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	102
	103	#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W \| (1 << 2))
	104	#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W \| (1 << 1))
	105	#define BFIN_NAND_WRITE(addr, cmd) \
	106	do { \
	107	bfin_write8(addr, cmd); \
	108	SSYNC(); \
	109	} while (0)
	110
	111	#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
	112	#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
	113	#define NAND_PLAT_GPIO_DEV_READY GPIO_PF9
	114
	115	/*
	116	* Misc Settings
	117	*/
	118	#define CONFIG_BAUDRATE 115200
	119	#define CONFIG_RTC_BFIN
	120	#define CONFIG_UART_CONSOLE 0
939b150a DP	121	#define CONFIG_BOOTCOMMAND "run nandboot"
	122	#define CONFIG_BOOTDELAY 2
	123	#define CONFIG_LOADADDR 0x2000000
939b150a DP	124
	125	/*
	126	* Pull in common ADI header for remaining command/environment setup
	127	*/
	128	#include <configs/bfin_adi_common.h>
	129
	130	/*
	131	* Overwrite some settings defined in bfin_adi_common.h
	132	*/
	133	#undef NAND_ENV_SETTINGS
	134	#define NAND_ENV_SETTINGS \
	135	"nandargs=set bootargs " CONFIG_BOOTARGS "\0" \
	136	"nandboot=" \
	137	"nand read $(loadaddr) 0x0 0x900000;" \
	138	"run nandargs;" \
	139	"bootm" \
	140	"\0"
	141
	142	#endif