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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
0d04f34a | 2 | /* |
fe84ebf0 | 3 | * (C) Copyright 2012-2016 Stephen Warren |
0d04f34a SW |
4 | */ |
5 | ||
6 | #ifndef __CONFIG_H | |
7 | #define __CONFIG_H | |
8 | ||
fe84ebf0 SW |
9 | #include <linux/sizes.h> |
10 | #include <asm/arch/timer.h> | |
11 | ||
8e3361c8 MB |
12 | #ifndef __ASSEMBLY__ |
13 | #include <asm/arch/base.h> | |
14 | #endif | |
15 | ||
fe84ebf0 SW |
16 | #if defined(CONFIG_TARGET_RPI_2) || defined(CONFIG_TARGET_RPI_3_32B) |
17 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
18 | #endif | |
19 | ||
fe84ebf0 | 20 | /* Architecture, CPU, etc.*/ |
fe84ebf0 SW |
21 | |
22 | /* Use SoC timer for AArch32, but architected timer for AArch64 */ | |
23 | #ifndef CONFIG_ARM64 | |
24 | #define CONFIG_SYS_TIMER_RATE 1000000 | |
25 | #define CONFIG_SYS_TIMER_COUNTER \ | |
26 | (&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo) | |
27 | #endif | |
28 | ||
94ba26f2 TR |
29 | /* |
30 | * 2835 is a SKU in a series for which the 2708 is the first or primary SoC, | |
31 | * so 2708 has historically been used rather than a dedicated 2835 ID. | |
32 | * | |
33 | * We don't define a machine type for bcm2709/bcm2836 since the RPi Foundation | |
34 | * chose to use someone else's previously registered machine ID (3139, MX51_GGC) | |
35 | * rather than obtaining a valid ID:-/ | |
36 | * | |
37 | * For the bcm2837, hopefully a machine type is not needed, since everything | |
38 | * is DT. | |
39 | */ | |
40 | #ifdef CONFIG_BCM2835 | |
41 | #define CONFIG_MACH_TYPE MACH_TYPE_BCM2708 | |
42 | #endif | |
43 | ||
fe84ebf0 | 44 | /* Memory layout */ |
fe84ebf0 | 45 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
fe84ebf0 SW |
46 | #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE |
47 | /* | |
48 | * The board really has 256M. However, the VC (VideoCore co-processor) shares | |
49 | * the RAM, and uses a configurable portion at the top. We tell U-Boot that a | |
50 | * smaller amount of RAM is present in order to avoid stomping on the area | |
51 | * the VC uses. | |
52 | */ | |
53 | #define CONFIG_SYS_SDRAM_SIZE SZ_128M | |
54 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ | |
55 | CONFIG_SYS_SDRAM_SIZE - \ | |
56 | GENERATED_GBL_DATA_SIZE) | |
57 | #define CONFIG_SYS_MALLOC_LEN SZ_4M | |
58 | #define CONFIG_SYS_MEMTEST_START 0x00100000 | |
59 | #define CONFIG_SYS_MEMTEST_END 0x00200000 | |
60 | #define CONFIG_LOADADDR 0x00200000 | |
61 | ||
659f4fe3 BL |
62 | #ifdef CONFIG_ARM64 |
63 | #define CONFIG_SYS_BOOTM_LEN SZ_64M | |
64 | #endif | |
65 | ||
fe84ebf0 SW |
66 | /* Devices */ |
67 | /* GPIO */ | |
68 | #define CONFIG_BCM2835_GPIO | |
69 | /* LCD */ | |
fe84ebf0 | 70 | #define CONFIG_LCD_DT_SIMPLEFB |
fe84ebf0 | 71 | #define CONFIG_VIDEO_BCM2835 |
fe84ebf0 | 72 | |
fe84ebf0 | 73 | #ifdef CONFIG_CMD_USB |
d0375f3c | 74 | #define CONFIG_TFTP_TSIZE |
fe84ebf0 SW |
75 | #endif |
76 | ||
fe84ebf0 SW |
77 | /* Console configuration */ |
78 | #define CONFIG_SYS_CBSIZE 1024 | |
fe84ebf0 SW |
79 | |
80 | /* Environment */ | |
fe84ebf0 | 81 | #define CONFIG_SYS_LOAD_ADDR 0x1000000 |
fe84ebf0 SW |
82 | |
83 | /* Shell */ | |
fe84ebf0 | 84 | |
fe84ebf0 SW |
85 | /* ATAGs support for bootm/bootz */ |
86 | #define CONFIG_SETUP_MEMORY_TAGS | |
87 | #define CONFIG_CMDLINE_TAG | |
88 | #define CONFIG_INITRD_TAG | |
89 | ||
fe84ebf0 | 90 | /* Environment */ |
fe84ebf0 SW |
91 | #define ENV_DEVICE_SETTINGS \ |
92 | "stdin=serial,usbkbd\0" \ | |
ea843b6d SG |
93 | "stdout=serial,vidconsole\0" \ |
94 | "stderr=serial,vidconsole\0" | |
fe84ebf0 | 95 | |
72274259 TT |
96 | #ifdef CONFIG_ARM64 |
97 | #define FDT_HIGH "ffffffffffffffff" | |
98 | #define INITRD_HIGH "ffffffffffffffff" | |
99 | #else | |
100 | #define FDT_HIGH "ffffffff" | |
101 | #define INITRD_HIGH "ffffffff" | |
102 | #endif | |
103 | ||
fe84ebf0 SW |
104 | /* |
105 | * Memory layout for where various images get loaded by boot scripts: | |
106 | * | |
107 | * I suspect address 0 is used as the SMP pen on the RPi2, so avoid this. | |
108 | * | |
385cbe29 TT |
109 | * Older versions of the boot firmware place the firmware-loaded DTB at 0x100, |
110 | * newer versions place it in high memory. So prevent U-Boot from doing its own | |
111 | * DTB + initrd relocation so that we won't accidentally relocate the initrd | |
112 | * over the firmware-loaded DTB and generally try to lay out things starting | |
113 | * from the bottom of RAM. | |
fe84ebf0 | 114 | * |
385cbe29 TT |
115 | * kernel_addr_r has different constraints on ARM and Aarch64. For 32-bit ARM, |
116 | * it must be within the first 128M of RAM in order for the kernel's | |
117 | * CONFIG_AUTO_ZRELADDR option to work. The kernel itself will be decompressed | |
118 | * to 0x8000 but the decompressor clobbers 0x4000-0x8000 as well. The | |
119 | * decompressor also likes to relocate itself to right past the end of the | |
120 | * decompressed kernel, so in total the sum of the compressed and and | |
121 | * decompressed kernel needs to be reserved. | |
fe84ebf0 | 122 | * |
385cbe29 TT |
123 | * For Aarch64, the kernel image is uncompressed and must be loaded at |
124 | * text_offset bytes (specified in the header of the Image) into a 2MB | |
125 | * boundary. The 'booti' command relocates the image if necessary. Linux uses | |
126 | * a default text_offset of 0x80000. In summary, loading at 0x80000 | |
127 | * satisfies all these constraints and reserving memory up to 0x02400000 | |
128 | * permits fairly large (roughly 36M) kernels. | |
fe84ebf0 | 129 | * |
385cbe29 TT |
130 | * scriptaddr and pxefile_addr_r can be pretty much anywhere that doesn't |
131 | * conflict with something else. Reserving 1M for each of them at | |
132 | * 0x02400000-0x02500000 and 0x02500000-0x02600000 should be plenty. | |
fe84ebf0 | 133 | * |
385cbe29 TT |
134 | * On ARM, both the DTB and any possible initrd must be loaded such that they |
135 | * fit inside the lowmem mapping in Linux. In practice, this usually means not | |
136 | * more than ~700M away from the start of the kernel image but this number can | |
137 | * be larger OR smaller depending on e.g. the 'vmalloc=xxxM' command line | |
138 | * parameter given to the kernel. So reserving memory from low to high | |
139 | * satisfies this constraint again. Reserving 1M at 0x02600000-0x02700000 for | |
140 | * the DTB leaves rest of the free RAM to the initrd starting at 0x02700000. | |
141 | * Even with the smallest possible CPU-GPU memory split of the CPU getting | |
142 | * only 64M, the remaining 25M starting at 0x02700000 should allow quite | |
143 | * large initrds before they start colliding with U-Boot. | |
fe84ebf0 SW |
144 | */ |
145 | #define ENV_MEM_LAYOUT_SETTINGS \ | |
72274259 TT |
146 | "fdt_high=" FDT_HIGH "\0" \ |
147 | "initrd_high=" INITRD_HIGH "\0" \ | |
385cbe29 TT |
148 | "kernel_addr_r=0x00080000\0" \ |
149 | "scriptaddr=0x02400000\0" \ | |
150 | "pxefile_addr_r=0x02500000\0" \ | |
151 | "fdt_addr_r=0x02600000\0" \ | |
152 | "ramdisk_addr_r=0x02700000\0" | |
fe84ebf0 | 153 | |
e4617bdb | 154 | #if CONFIG_IS_ENABLED(CMD_MMC) |
155 | #define BOOT_TARGET_MMC(func) \ | |
156 | func(MMC, mmc, 0) \ | |
157 | func(MMC, mmc, 1) | |
158 | #else | |
159 | #define BOOT_TARGET_MMC(func) | |
160 | #endif | |
161 | ||
162 | #if CONFIG_IS_ENABLED(CMD_USB) | |
163 | #define BOOT_TARGET_USB(func) func(USB, usb, 0) | |
164 | #else | |
165 | #define BOOT_TARGET_USB(func) | |
166 | #endif | |
167 | ||
168 | #if CONFIG_IS_ENABLED(CMD_PXE) | |
169 | #define BOOT_TARGET_PXE(func) func(PXE, pxe, na) | |
170 | #else | |
171 | #define BOOT_TARGET_PXE(func) | |
172 | #endif | |
173 | ||
174 | #if CONFIG_IS_ENABLED(CMD_DHCP) | |
175 | #define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na) | |
176 | #else | |
177 | #define BOOT_TARGET_DHCP(func) | |
178 | #endif | |
179 | ||
fe84ebf0 | 180 | #define BOOT_TARGET_DEVICES(func) \ |
e4617bdb | 181 | BOOT_TARGET_MMC(func) \ |
182 | BOOT_TARGET_USB(func) \ | |
183 | BOOT_TARGET_PXE(func) \ | |
184 | BOOT_TARGET_DHCP(func) | |
185 | ||
fe84ebf0 SW |
186 | #include <config_distro_bootcmd.h> |
187 | ||
188 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
189 | "dhcpuboot=usb start; dhcp u-boot.uimg; bootm\0" \ | |
190 | ENV_DEVICE_SETTINGS \ | |
191 | ENV_MEM_LAYOUT_SETTINGS \ | |
192 | BOOTENV | |
060f9bf5 | 193 | |
0d04f34a | 194 | |
0d04f34a | 195 | #endif |