[u-boot.git] / drivers / rtc / x1205.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2007
 * Stefan Roese, DENX Software Engineering, [email protected].
 *
 * based on a the Linux rtc-x1207.c driver which is:
 *	Copyright 2004 Karen Spearel
 *	Copyright 2005 Alessandro Zummo
 *
 * Information and datasheet:
 * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
 */

/*
 * Date & Time support for Xicor/Intersil X1205 RTC
 */

/* #define	DEBUG	*/

#include <common.h>
#include <command.h>
#include <log.h>
#include <rtc.h>
#include <i2c.h>

#define CCR_SEC			0
#define CCR_MIN			1
#define CCR_HOUR		2
#define CCR_MDAY		3
#define CCR_MONTH		4
#define CCR_YEAR		5
#define CCR_WDAY		6
#define CCR_Y2K			7

#define X1205_REG_SR		0x3F	/* status register */
#define X1205_REG_Y2K		0x37
#define X1205_REG_DW		0x36
#define X1205_REG_YR		0x35
#define X1205_REG_MO		0x34
#define X1205_REG_DT		0x33
#define X1205_REG_HR		0x32
#define X1205_REG_MN		0x31
#define X1205_REG_SC		0x30
#define X1205_REG_DTR		0x13
#define X1205_REG_ATR		0x12
#define X1205_REG_INT		0x11
#define X1205_REG_0		0x10
#define X1205_REG_Y2K1		0x0F
#define X1205_REG_DWA1		0x0E
#define X1205_REG_YRA1		0x0D
#define X1205_REG_MOA1		0x0C
#define X1205_REG_DTA1		0x0B
#define X1205_REG_HRA1		0x0A
#define X1205_REG_MNA1		0x09
#define X1205_REG_SCA1		0x08
#define X1205_REG_Y2K0		0x07
#define X1205_REG_DWA0		0x06
#define X1205_REG_YRA0		0x05
#define X1205_REG_MOA0		0x04
#define X1205_REG_DTA0		0x03
#define X1205_REG_HRA0		0x02
#define X1205_REG_MNA0		0x01
#define X1205_REG_SCA0		0x00

#define X1205_CCR_BASE		0x30	/* Base address of CCR */
#define X1205_ALM0_BASE		0x00	/* Base address of ALARM0 */

#define X1205_SR_RTCF		0x01	/* Clock failure */
#define X1205_SR_WEL		0x02	/* Write Enable Latch */
#define X1205_SR_RWEL		0x04	/* Register Write Enable */

#define X1205_DTR_DTR0		0x01
#define X1205_DTR_DTR1		0x02
#define X1205_DTR_DTR2		0x04

#define X1205_HR_MIL		0x80	/* Set in ccr.hour for 24 hr mode */

static void rtc_write(int reg, u8 val)
{
	i2c_write(CONFIG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1);
}

/*
 * In the routines that deal directly with the x1205 hardware, we use
 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
 * Epoch is initialized as 2000. Time is set to UTC.
 */
int rtc_get(struct rtc_time *tm)
{
	u8 buf[8];

	i2c_read(CONFIG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8);

	debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
	      "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
	      __FUNCTION__,
	      buf[0], buf[1], buf[2], buf[3],
	      buf[4], buf[5], buf[6], buf[7]);

	tm->tm_sec = bcd2bin(buf[CCR_SEC]);
	tm->tm_min = bcd2bin(buf[CCR_MIN]);
	tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
	tm->tm_mday = bcd2bin(buf[CCR_MDAY]);
	tm->tm_mon = bcd2bin(buf[CCR_MONTH]); /* mon is 0-11 */
	tm->tm_year = bcd2bin(buf[CCR_YEAR])
		+ (bcd2bin(buf[CCR_Y2K]) * 100);
	tm->tm_wday = buf[CCR_WDAY];

	debug("%s: tm is secs=%d, mins=%d, hours=%d, "
	      "mday=%d, mon=%d, year=%d, wday=%d\n",
	      __FUNCTION__,
	      tm->tm_sec, tm->tm_min, tm->tm_hour,
	      tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);

	return 0;
}

int rtc_set(struct rtc_time *tm)
{
	int i;
	u8 buf[8];

	debug("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
	      tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
	      tm->tm_hour, tm->tm_min, tm->tm_sec);

	buf[CCR_SEC] = bin2bcd(tm->tm_sec);
	buf[CCR_MIN] = bin2bcd(tm->tm_min);

	/* set hour and 24hr bit */
	buf[CCR_HOUR] = bin2bcd(tm->tm_hour) | X1205_HR_MIL;

	buf[CCR_MDAY] = bin2bcd(tm->tm_mday);

	/* month, 1 - 12 */
	buf[CCR_MONTH] = bin2bcd(tm->tm_mon);

	/* year, since the rtc epoch*/
	buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100);
	buf[CCR_WDAY] = tm->tm_wday & 0x07;
	buf[CCR_Y2K] = bin2bcd(tm->tm_year / 100);

	/* this sequence is required to unlock the chip */
	rtc_write(X1205_REG_SR, X1205_SR_WEL);
	rtc_write(X1205_REG_SR, X1205_SR_WEL | X1205_SR_RWEL);

	/* write register's data */
	for (i = 0; i < 8; i++)
		rtc_write(X1205_CCR_BASE + i, buf[i]);

	rtc_write(X1205_REG_SR, 0);

	return 0;
}

void rtc_reset(void)
{
	/*
	 * Nothing to do
	 */
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
758c037a SR	2	/*
	3	* (C) Copyright 2007
	4	* Stefan Roese, DENX Software Engineering, [email protected].
	5	*
	6	* based on a the Linux rtc-x1207.c driver which is:
	7	* Copyright 2004 Karen Spearel
	8	* Copyright 2005 Alessandro Zummo
	9	*
	10	* Information and datasheet:
	11	* http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
758c037a SR	12	*/
	13
	14	/*
	15	* Date & Time support for Xicor/Intersil X1205 RTC
	16	*/
	17
	18	/* #define DEBUG */
	19
	20	#include <common.h>
	21	#include <command.h>
f7ae49fc	22	#include <log.h>
758c037a SR	23	#include <rtc.h>
758c037a SR	24	#include <i2c.h>
758c037a	25
758c037a SR	26	#define CCR_SEC 0
	27	#define CCR_MIN 1
	28	#define CCR_HOUR 2
	29	#define CCR_MDAY 3
	30	#define CCR_MONTH 4
	31	#define CCR_YEAR 5
	32	#define CCR_WDAY 6
	33	#define CCR_Y2K 7
	34
	35	#define X1205_REG_SR 0x3F /* status register */
	36	#define X1205_REG_Y2K 0x37
	37	#define X1205_REG_DW 0x36
	38	#define X1205_REG_YR 0x35
	39	#define X1205_REG_MO 0x34
	40	#define X1205_REG_DT 0x33
	41	#define X1205_REG_HR 0x32
	42	#define X1205_REG_MN 0x31
	43	#define X1205_REG_SC 0x30
	44	#define X1205_REG_DTR 0x13
	45	#define X1205_REG_ATR 0x12
	46	#define X1205_REG_INT 0x11
	47	#define X1205_REG_0 0x10
	48	#define X1205_REG_Y2K1 0x0F
	49	#define X1205_REG_DWA1 0x0E
	50	#define X1205_REG_YRA1 0x0D
	51	#define X1205_REG_MOA1 0x0C
	52	#define X1205_REG_DTA1 0x0B
	53	#define X1205_REG_HRA1 0x0A
	54	#define X1205_REG_MNA1 0x09
	55	#define X1205_REG_SCA1 0x08
	56	#define X1205_REG_Y2K0 0x07
	57	#define X1205_REG_DWA0 0x06
	58	#define X1205_REG_YRA0 0x05
	59	#define X1205_REG_MOA0 0x04
	60	#define X1205_REG_DTA0 0x03
	61	#define X1205_REG_HRA0 0x02
	62	#define X1205_REG_MNA0 0x01
	63	#define X1205_REG_SCA0 0x00
	64
	65	#define X1205_CCR_BASE 0x30 /* Base address of CCR */
	66	#define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */
	67
	68	#define X1205_SR_RTCF 0x01 /* Clock failure */
	69	#define X1205_SR_WEL 0x02 /* Write Enable Latch */
	70	#define X1205_SR_RWEL 0x04 /* Register Write Enable */
	71
	72	#define X1205_DTR_DTR0 0x01
	73	#define X1205_DTR_DTR1 0x02
	74	#define X1205_DTR_DTR2 0x04
	75
	76	#define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */
	77
	78	static void rtc_write(int reg, u8 val)
	79	{
6d0f6bcf	80	i2c_write(CONFIG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1);
758c037a SR	81	}
	82
	83	/*
	84	* In the routines that deal directly with the x1205 hardware, we use
	85	* rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
	86	* Epoch is initialized as 2000. Time is set to UTC.
	87	*/
b73a19e1	88	int rtc_get(struct rtc_time *tm)
758c037a SR	89	{
	90	u8 buf[8];
	91
6d0f6bcf	92	i2c_read(CONFIG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8);
758c037a SR	93
	94	debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
	95	"mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
	96	__FUNCTION__,
	97	buf[0], buf[1], buf[2], buf[3],
	98	buf[4], buf[5], buf[6], buf[7]);
	99
e84aba13 AT	100	tm->tm_sec = bcd2bin(buf[CCR_SEC]);
	101	tm->tm_min = bcd2bin(buf[CCR_MIN]);
	102	tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
	103	tm->tm_mday = bcd2bin(buf[CCR_MDAY]);
	104	tm->tm_mon = bcd2bin(buf[CCR_MONTH]); /* mon is 0-11 */
	105	tm->tm_year = bcd2bin(buf[CCR_YEAR])
	106	+ (bcd2bin(buf[CCR_Y2K]) * 100);
758c037a SR	107	tm->tm_wday = buf[CCR_WDAY];
	108
	109	debug("%s: tm is secs=%d, mins=%d, hours=%d, "
	110	"mday=%d, mon=%d, year=%d, wday=%d\n",
	111	__FUNCTION__,
	112	tm->tm_sec, tm->tm_min, tm->tm_hour,
	113	tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
b73a19e1 YT	114
b73a19e1 YT	115	return 0;
758c037a SR	116	}
758c037a SR	117
d1e23194	118	int rtc_set(struct rtc_time *tm)
758c037a SR	119	{
	120	int i;
	121	u8 buf[8];
	122
	123	debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
	124	tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
	125	tm->tm_hour, tm->tm_min, tm->tm_sec);
	126
e84aba13 AT	127	buf[CCR_SEC] = bin2bcd(tm->tm_sec);
e84aba13 AT	128	buf[CCR_MIN] = bin2bcd(tm->tm_min);
758c037a SR	129
758c037a SR	130	/* set hour and 24hr bit */
e84aba13	131	buf[CCR_HOUR] = bin2bcd(tm->tm_hour) \| X1205_HR_MIL;
758c037a	132
e84aba13	133	buf[CCR_MDAY] = bin2bcd(tm->tm_mday);
758c037a SR	134
758c037a SR	135	/* month, 1 - 12 */
e84aba13	136	buf[CCR_MONTH] = bin2bcd(tm->tm_mon);
758c037a SR	137
758c037a SR	138	/* year, since the rtc epoch*/
e84aba13	139	buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100);
758c037a	140	buf[CCR_WDAY] = tm->tm_wday & 0x07;
e84aba13	141	buf[CCR_Y2K] = bin2bcd(tm->tm_year / 100);
758c037a SR	142
	143	/* this sequence is required to unlock the chip */
	144	rtc_write(X1205_REG_SR, X1205_SR_WEL);
	145	rtc_write(X1205_REG_SR, X1205_SR_WEL \| X1205_SR_RWEL);
	146
	147	/* write register's data */
	148	for (i = 0; i < 8; i++)
	149	rtc_write(X1205_CCR_BASE + i, buf[i]);
	150
	151	rtc_write(X1205_REG_SR, 0);
d1e23194 JCPV	152
d1e23194 JCPV	153	return 0;
758c037a SR	154	}
	155
	156	void rtc_reset(void)
	157	{
	158	/*
	159	* Nothing to do
	160	*/
	161	}