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83d290c5 1// SPDX-License-Identifier: GPL-2.0+
5f184715
AF
2/*
3 * Generic PHY Management code
4 *
5f184715
AF
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 * author Andy Fleming
7 *
8 * Based loosely off of Linux's PHY Lib
9 */
5f184715 10#include <common.h>
24b852a7 11#include <console.h>
c74c8e66 12#include <dm.h>
f7ae49fc 13#include <log.h>
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AF
14#include <malloc.h>
15#include <net.h>
16#include <command.h>
17#include <miiphy.h>
18#include <phy.h>
19#include <errno.h>
c05ed00a 20#include <linux/delay.h>
1adb406b 21#include <linux/err.h>
597fe041 22#include <linux/compiler.h>
5f184715 23
abbfcbe5
MS
24DECLARE_GLOBAL_DATA_PTR;
25
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AF
26/* Generic PHY support and helper functions */
27
28/**
8d631203 29 * genphy_config_advert - sanitize and advertise auto-negotiation parameters
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AF
30 * @phydev: target phy_device struct
31 *
32 * Description: Writes MII_ADVERTISE with the appropriate values,
33 * after sanitizing the values to make sure we only advertise
34 * what is supported. Returns < 0 on error, 0 if the PHY's advertisement
35 * hasn't changed, and > 0 if it has changed.
36 */
960d70c6 37static int genphy_config_advert(struct phy_device *phydev)
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AF
38{
39 u32 advertise;
bbdcaff1 40 int oldadv, adv, bmsr;
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AF
41 int err, changed = 0;
42
bbdcaff1 43 /* Only allow advertising what this PHY supports */
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44 phydev->advertising &= phydev->supported;
45 advertise = phydev->advertising;
46
47 /* Setup standard advertisement */
bbdcaff1
FF
48 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE);
49 oldadv = adv;
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AF
50
51 if (adv < 0)
52 return adv;
53
54 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP |
55 ADVERTISE_PAUSE_ASYM);
56 if (advertise & ADVERTISED_10baseT_Half)
57 adv |= ADVERTISE_10HALF;
58 if (advertise & ADVERTISED_10baseT_Full)
59 adv |= ADVERTISE_10FULL;
60 if (advertise & ADVERTISED_100baseT_Half)
61 adv |= ADVERTISE_100HALF;
62 if (advertise & ADVERTISED_100baseT_Full)
63 adv |= ADVERTISE_100FULL;
64 if (advertise & ADVERTISED_Pause)
65 adv |= ADVERTISE_PAUSE_CAP;
66 if (advertise & ADVERTISED_Asym_Pause)
67 adv |= ADVERTISE_PAUSE_ASYM;
de1d786e
CC
68 if (advertise & ADVERTISED_1000baseX_Half)
69 adv |= ADVERTISE_1000XHALF;
70 if (advertise & ADVERTISED_1000baseX_Full)
71 adv |= ADVERTISE_1000XFULL;
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AF
72
73 if (adv != oldadv) {
74 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE, adv);
75
76 if (err < 0)
77 return err;
78 changed = 1;
79 }
80
bbdcaff1
FF
81 bmsr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
82 if (bmsr < 0)
83 return bmsr;
84
85 /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all
86 * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a
87 * logical 1.
88 */
89 if (!(bmsr & BMSR_ESTATEN))
90 return changed;
91
5f184715 92 /* Configure gigabit if it's supported */
bbdcaff1
FF
93 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
94 oldadv = adv;
95
96 if (adv < 0)
97 return adv;
5f184715 98
bbdcaff1 99 adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
5f184715 100
bbdcaff1
FF
101 if (phydev->supported & (SUPPORTED_1000baseT_Half |
102 SUPPORTED_1000baseT_Full)) {
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AF
103 if (advertise & SUPPORTED_1000baseT_Half)
104 adv |= ADVERTISE_1000HALF;
105 if (advertise & SUPPORTED_1000baseT_Full)
106 adv |= ADVERTISE_1000FULL;
bbdcaff1 107 }
5f184715 108
bbdcaff1
FF
109 if (adv != oldadv)
110 changed = 1;
5f184715 111
bbdcaff1
FF
112 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, adv);
113 if (err < 0)
114 return err;
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AF
115
116 return changed;
117}
118
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AF
119/**
120 * genphy_setup_forced - configures/forces speed/duplex from @phydev
121 * @phydev: target phy_device struct
122 *
123 * Description: Configures MII_BMCR to force speed/duplex
124 * to the values in phydev. Assumes that the values are valid.
125 */
960d70c6 126static int genphy_setup_forced(struct phy_device *phydev)
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AF
127{
128 int err;
53b0c38c 129 int ctl = BMCR_ANRESTART;
5f184715 130
8d631203
MS
131 phydev->pause = 0;
132 phydev->asym_pause = 0;
5f184715 133
8d631203 134 if (phydev->speed == SPEED_1000)
5f184715 135 ctl |= BMCR_SPEED1000;
8d631203 136 else if (phydev->speed == SPEED_100)
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AF
137 ctl |= BMCR_SPEED100;
138
8d631203 139 if (phydev->duplex == DUPLEX_FULL)
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AF
140 ctl |= BMCR_FULLDPLX;
141
142 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl);
143
144 return err;
145}
146
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AF
147/**
148 * genphy_restart_aneg - Enable and Restart Autonegotiation
149 * @phydev: target phy_device struct
150 */
151int genphy_restart_aneg(struct phy_device *phydev)
152{
153 int ctl;
154
155 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
156
157 if (ctl < 0)
158 return ctl;
159
160 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
161
162 /* Don't isolate the PHY if we're negotiating */
163 ctl &= ~(BMCR_ISOLATE);
164
165 ctl = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl);
166
167 return ctl;
168}
169
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AF
170/**
171 * genphy_config_aneg - restart auto-negotiation or write BMCR
172 * @phydev: target phy_device struct
173 *
174 * Description: If auto-negotiation is enabled, we configure the
175 * advertising, and then restart auto-negotiation. If it is not
176 * enabled, then we write the BMCR.
177 */
178int genphy_config_aneg(struct phy_device *phydev)
179{
180 int result;
181
8d631203 182 if (phydev->autoneg != AUTONEG_ENABLE)
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AF
183 return genphy_setup_forced(phydev);
184
185 result = genphy_config_advert(phydev);
186
187 if (result < 0) /* error */
188 return result;
189
190 if (result == 0) {
8d631203
MS
191 /*
192 * Advertisment hasn't changed, but maybe aneg was never on to
193 * begin with? Or maybe phy was isolated?
194 */
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AF
195 int ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
196
197 if (ctl < 0)
198 return ctl;
199
200 if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
201 result = 1; /* do restart aneg */
202 }
203
8d631203
MS
204 /*
205 * Only restart aneg if we are advertising something different
206 * than we were before.
207 */
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AF
208 if (result > 0)
209 result = genphy_restart_aneg(phydev);
210
211 return result;
212}
213
214/**
215 * genphy_update_link - update link status in @phydev
216 * @phydev: target phy_device struct
217 *
218 * Description: Update the value in phydev->link to reflect the
219 * current link value. In order to do this, we need to read
220 * the status register twice, keeping the second value.
221 */
222int genphy_update_link(struct phy_device *phydev)
223{
224 unsigned int mii_reg;
225
226 /*
227 * Wait if the link is up, and autonegotiation is in progress
228 * (ie - we're capable and it's not done)
229 */
230 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
231
232 /*
233 * If we already saw the link up, and it hasn't gone down, then
234 * we don't need to wait for autoneg again
235 */
236 if (phydev->link && mii_reg & BMSR_LSTATUS)
237 return 0;
238
1f9e672c
AM
239 if ((phydev->autoneg == AUTONEG_ENABLE) &&
240 !(mii_reg & BMSR_ANEGCOMPLETE)) {
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AF
241 int i = 0;
242
243 printf("%s Waiting for PHY auto negotiation to complete",
8d631203 244 phydev->dev->name);
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245 while (!(mii_reg & BMSR_ANEGCOMPLETE)) {
246 /*
247 * Timeout reached ?
248 */
a44ee246 249 if (i > (PHY_ANEG_TIMEOUT / 50)) {
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AF
250 printf(" TIMEOUT !\n");
251 phydev->link = 0;
ef5e821b 252 return -ETIMEDOUT;
5f184715
AF
253 }
254
255 if (ctrlc()) {
256 puts("user interrupt!\n");
257 phydev->link = 0;
258 return -EINTR;
259 }
260
27c3f70f 261 if ((i++ % 10) == 0)
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AF
262 printf(".");
263
5f184715 264 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
27c3f70f 265 mdelay(50); /* 50 ms */
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AF
266 }
267 printf(" done\n");
268 phydev->link = 1;
269 } else {
270 /* Read the link a second time to clear the latched state */
271 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
272
273 if (mii_reg & BMSR_LSTATUS)
274 phydev->link = 1;
275 else
276 phydev->link = 0;
277 }
278
279 return 0;
280}
281
282/*
283 * Generic function which updates the speed and duplex. If
284 * autonegotiation is enabled, it uses the AND of the link
285 * partner's advertised capabilities and our advertised
286 * capabilities. If autonegotiation is disabled, we use the
287 * appropriate bits in the control register.
288 *
289 * Stolen from Linux's mii.c and phy_device.c
290 */
e2043f5c 291int genphy_parse_link(struct phy_device *phydev)
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AF
292{
293 int mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
294
295 /* We're using autonegotiation */
1f9e672c 296 if (phydev->autoneg == AUTONEG_ENABLE) {
5f184715 297 u32 lpa = 0;
f6d1f6e4 298 int gblpa = 0;
de1d786e 299 u32 estatus = 0;
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AF
300
301 /* Check for gigabit capability */
3a530d1b
DD
302 if (phydev->supported & (SUPPORTED_1000baseT_Full |
303 SUPPORTED_1000baseT_Half)) {
5f184715
AF
304 /* We want a list of states supported by
305 * both PHYs in the link
306 */
307 gblpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000);
f6d1f6e4 308 if (gblpa < 0) {
8d631203
MS
309 debug("Could not read MII_STAT1000. ");
310 debug("Ignoring gigabit capability\n");
f6d1f6e4
HS
311 gblpa = 0;
312 }
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AF
313 gblpa &= phy_read(phydev,
314 MDIO_DEVAD_NONE, MII_CTRL1000) << 2;
315 }
316
317 /* Set the baseline so we only have to set them
318 * if they're different
319 */
320 phydev->speed = SPEED_10;
321 phydev->duplex = DUPLEX_HALF;
322
323 /* Check the gigabit fields */
324 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
325 phydev->speed = SPEED_1000;
326
327 if (gblpa & PHY_1000BTSR_1000FD)
328 phydev->duplex = DUPLEX_FULL;
329
330 /* We're done! */
331 return 0;
332 }
333
334 lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE);
335 lpa &= phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA);
336
0dcfb0fc 337 if (lpa & (LPA_100FULL | LPA_100HALF)) {
5f184715
AF
338 phydev->speed = SPEED_100;
339
0dcfb0fc
WD
340 if (lpa & LPA_100FULL)
341 phydev->duplex = DUPLEX_FULL;
342
8d631203 343 } else if (lpa & LPA_10FULL) {
5f184715 344 phydev->duplex = DUPLEX_FULL;
8d631203 345 }
de1d786e 346
9ba30f6b
SS
347 /*
348 * Extended status may indicate that the PHY supports
349 * 1000BASE-T/X even though the 1000BASE-T registers
350 * are missing. In this case we can't tell whether the
351 * peer also supports it, so we only check extended
352 * status if the 1000BASE-T registers are actually
353 * missing.
354 */
355 if ((mii_reg & BMSR_ESTATEN) && !(mii_reg & BMSR_ERCAP))
de1d786e
CC
356 estatus = phy_read(phydev, MDIO_DEVAD_NONE,
357 MII_ESTATUS);
358
359 if (estatus & (ESTATUS_1000_XFULL | ESTATUS_1000_XHALF |
360 ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) {
361 phydev->speed = SPEED_1000;
362 if (estatus & (ESTATUS_1000_XFULL | ESTATUS_1000_TFULL))
363 phydev->duplex = DUPLEX_FULL;
364 }
365
5f184715
AF
366 } else {
367 u32 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
368
369 phydev->speed = SPEED_10;
370 phydev->duplex = DUPLEX_HALF;
371
372 if (bmcr & BMCR_FULLDPLX)
373 phydev->duplex = DUPLEX_FULL;
374
375 if (bmcr & BMCR_SPEED1000)
376 phydev->speed = SPEED_1000;
377 else if (bmcr & BMCR_SPEED100)
378 phydev->speed = SPEED_100;
379 }
380
381 return 0;
382}
383
384int genphy_config(struct phy_device *phydev)
385{
386 int val;
387 u32 features;
388
5f184715
AF
389 features = (SUPPORTED_TP | SUPPORTED_MII
390 | SUPPORTED_AUI | SUPPORTED_FIBRE |
391 SUPPORTED_BNC);
392
393 /* Do we support autonegotiation? */
394 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
395
396 if (val < 0)
397 return val;
398
399 if (val & BMSR_ANEGCAPABLE)
400 features |= SUPPORTED_Autoneg;
401
402 if (val & BMSR_100FULL)
403 features |= SUPPORTED_100baseT_Full;
404 if (val & BMSR_100HALF)
405 features |= SUPPORTED_100baseT_Half;
406 if (val & BMSR_10FULL)
407 features |= SUPPORTED_10baseT_Full;
408 if (val & BMSR_10HALF)
409 features |= SUPPORTED_10baseT_Half;
410
411 if (val & BMSR_ESTATEN) {
412 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_ESTATUS);
413
414 if (val < 0)
415 return val;
416
417 if (val & ESTATUS_1000_TFULL)
418 features |= SUPPORTED_1000baseT_Full;
419 if (val & ESTATUS_1000_THALF)
420 features |= SUPPORTED_1000baseT_Half;
de1d786e
CC
421 if (val & ESTATUS_1000_XFULL)
422 features |= SUPPORTED_1000baseX_Full;
423 if (val & ESTATUS_1000_XHALF)
9a5dad23 424 features |= SUPPORTED_1000baseX_Half;
5f184715
AF
425 }
426
44bc3174
SH
427 phydev->supported &= features;
428 phydev->advertising &= features;
5f184715
AF
429
430 genphy_config_aneg(phydev);
431
432 return 0;
433}
434
435int genphy_startup(struct phy_device *phydev)
436{
b733c278 437 int ret;
5f184715 438
b733c278
MS
439 ret = genphy_update_link(phydev);
440 if (ret)
441 return ret;
442
443 return genphy_parse_link(phydev);
5f184715
AF
444}
445
446int genphy_shutdown(struct phy_device *phydev)
447{
448 return 0;
449}
450
451static struct phy_driver genphy_driver = {
452 .uid = 0xffffffff,
453 .mask = 0xffffffff,
454 .name = "Generic PHY",
44bc3174
SH
455 .features = PHY_GBIT_FEATURES | SUPPORTED_MII |
456 SUPPORTED_AUI | SUPPORTED_FIBRE |
457 SUPPORTED_BNC,
5f184715
AF
458 .config = genphy_config,
459 .startup = genphy_startup,
460 .shutdown = genphy_shutdown,
461};
462
be49508a
SDPP
463int genphy_init(void)
464{
465 return phy_register(&genphy_driver);
466}
467
5f184715
AF
468static LIST_HEAD(phy_drivers);
469
470int phy_init(void)
471{
c689c486
SDPP
472#ifdef CONFIG_NEEDS_MANUAL_RELOC
473 /*
474 * The pointers inside phy_drivers also needs to be updated incase of
475 * manual reloc, without which these points to some invalid
476 * pre reloc address and leads to invalid accesses, hangs.
477 */
478 struct list_head *head = &phy_drivers;
479
480 head->next = (void *)head->next + gd->reloc_off;
481 head->prev = (void *)head->prev + gd->reloc_off;
482#endif
483
137963d7
FF
484#ifdef CONFIG_B53_SWITCH
485 phy_b53_init();
486#endif
24ae3961
KS
487#ifdef CONFIG_MV88E61XX_SWITCH
488 phy_mv88e61xx_init();
489#endif
f7c38cf8
SX
490#ifdef CONFIG_PHY_AQUANTIA
491 phy_aquantia_init();
492#endif
9082eeac
AF
493#ifdef CONFIG_PHY_ATHEROS
494 phy_atheros_init();
495#endif
496#ifdef CONFIG_PHY_BROADCOM
497 phy_broadcom_init();
498#endif
9b18e519
SL
499#ifdef CONFIG_PHY_CORTINA
500 phy_cortina_init();
501#endif
9082eeac
AF
502#ifdef CONFIG_PHY_DAVICOM
503 phy_davicom_init();
504#endif
f485c8a3
MP
505#ifdef CONFIG_PHY_ET1011C
506 phy_et1011c_init();
507#endif
9082eeac
AF
508#ifdef CONFIG_PHY_LXT
509 phy_lxt_init();
510#endif
511#ifdef CONFIG_PHY_MARVELL
512 phy_marvell_init();
513#endif
d397f7c4
AG
514#ifdef CONFIG_PHY_MICREL_KSZ8XXX
515 phy_micrel_ksz8xxx_init();
516#endif
517#ifdef CONFIG_PHY_MICREL_KSZ90X1
518 phy_micrel_ksz90x1_init();
9082eeac 519#endif
8995a96d
NA
520#ifdef CONFIG_PHY_MESON_GXL
521 phy_meson_gxl_init();
522#endif
9082eeac
AF
523#ifdef CONFIG_PHY_NATSEMI
524 phy_natsemi_init();
525#endif
526#ifdef CONFIG_PHY_REALTEK
527 phy_realtek_init();
528#endif
5751aa2f
NI
529#ifdef CONFIG_PHY_SMSC
530 phy_smsc_init();
531#endif
9082eeac
AF
532#ifdef CONFIG_PHY_TERANETICS
533 phy_teranetics_init();
534#endif
721aed79
EI
535#ifdef CONFIG_PHY_TI
536 phy_ti_init();
537#endif
9082eeac
AF
538#ifdef CONFIG_PHY_VITESSE
539 phy_vitesse_init();
540#endif
ed6fad3e
SDPP
541#ifdef CONFIG_PHY_XILINX
542 phy_xilinx_init();
543#endif
a5fd13ad
JH
544#ifdef CONFIG_PHY_MSCC
545 phy_mscc_init();
546#endif
db40c1aa
HS
547#ifdef CONFIG_PHY_FIXED
548 phy_fixed_init();
f41e588c 549#endif
e2ffeaa1
SMJ
550#ifdef CONFIG_PHY_NCSI
551 phy_ncsi_init();
552#endif
f41e588c
SDPP
553#ifdef CONFIG_PHY_XILINX_GMII2RGMII
554 phy_xilinx_gmii2rgmii_init();
db40c1aa 555#endif
be49508a
SDPP
556 genphy_init();
557
5f184715
AF
558 return 0;
559}
560
561int phy_register(struct phy_driver *drv)
562{
563 INIT_LIST_HEAD(&drv->list);
564 list_add_tail(&drv->list, &phy_drivers);
565
abbfcbe5
MS
566#ifdef CONFIG_NEEDS_MANUAL_RELOC
567 if (drv->probe)
568 drv->probe += gd->reloc_off;
569 if (drv->config)
570 drv->config += gd->reloc_off;
571 if (drv->startup)
572 drv->startup += gd->reloc_off;
573 if (drv->shutdown)
574 drv->shutdown += gd->reloc_off;
575 if (drv->readext)
576 drv->readext += gd->reloc_off;
577 if (drv->writeext)
578 drv->writeext += gd->reloc_off;
4f6746dc
CC
579 if (drv->read_mmd)
580 drv->read_mmd += gd->reloc_off;
581 if (drv->write_mmd)
582 drv->write_mmd += gd->reloc_off;
abbfcbe5 583#endif
5f184715
AF
584 return 0;
585}
586
b18acb0a
AB
587int phy_set_supported(struct phy_device *phydev, u32 max_speed)
588{
589 /* The default values for phydev->supported are provided by the PHY
590 * driver "features" member, we want to reset to sane defaults first
591 * before supporting higher speeds.
592 */
593 phydev->supported &= PHY_DEFAULT_FEATURES;
594
595 switch (max_speed) {
596 default:
597 return -ENOTSUPP;
598 case SPEED_1000:
599 phydev->supported |= PHY_1000BT_FEATURES;
600 /* fall through */
601 case SPEED_100:
602 phydev->supported |= PHY_100BT_FEATURES;
603 /* fall through */
604 case SPEED_10:
605 phydev->supported |= PHY_10BT_FEATURES;
606 }
607
608 return 0;
609}
610
960d70c6 611static int phy_probe(struct phy_device *phydev)
5f184715
AF
612{
613 int err = 0;
614
8d631203
MS
615 phydev->advertising = phydev->drv->features;
616 phydev->supported = phydev->drv->features;
617
5f184715
AF
618 phydev->mmds = phydev->drv->mmds;
619
620 if (phydev->drv->probe)
621 err = phydev->drv->probe(phydev);
622
623 return err;
624}
625
626static struct phy_driver *generic_for_interface(phy_interface_t interface)
627{
628#ifdef CONFIG_PHYLIB_10G
629 if (is_10g_interface(interface))
630 return &gen10g_driver;
631#endif
632
633 return &genphy_driver;
634}
635
960d70c6 636static struct phy_driver *get_phy_driver(struct phy_device *phydev,
8d631203 637 phy_interface_t interface)
5f184715
AF
638{
639 struct list_head *entry;
640 int phy_id = phydev->phy_id;
641 struct phy_driver *drv = NULL;
642
643 list_for_each(entry, &phy_drivers) {
644 drv = list_entry(entry, struct phy_driver, list);
645 if ((drv->uid & drv->mask) == (phy_id & drv->mask))
646 return drv;
647 }
648
649 /* If we made it here, there's no driver for this PHY */
650 return generic_for_interface(interface);
651}
652
960d70c6 653static struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
b3eabd82 654 u32 phy_id, bool is_c45,
960d70c6 655 phy_interface_t interface)
5f184715
AF
656{
657 struct phy_device *dev;
658
8d631203
MS
659 /*
660 * We allocate the device, and initialize the
661 * default values
662 */
5f184715
AF
663 dev = malloc(sizeof(*dev));
664 if (!dev) {
665 printf("Failed to allocate PHY device for %s:%d\n",
8d631203 666 bus->name, addr);
5f184715
AF
667 return NULL;
668 }
669
670 memset(dev, 0, sizeof(*dev));
671
672 dev->duplex = -1;
26d3acda 673 dev->link = 0;
5f184715
AF
674 dev->interface = interface;
675
eef0b8a9
GS
676#ifdef CONFIG_DM_ETH
677 dev->node = ofnode_null();
678#endif
679
5f184715
AF
680 dev->autoneg = AUTONEG_ENABLE;
681
682 dev->addr = addr;
683 dev->phy_id = phy_id;
b3eabd82 684 dev->is_c45 = is_c45;
5f184715
AF
685 dev->bus = bus;
686
687 dev->drv = get_phy_driver(dev, interface);
688
05eb6a69
SDPP
689 if (phy_probe(dev)) {
690 printf("%s, PHY probe failed\n", __func__);
691 return NULL;
692 }
5f184715 693
7b4ea2d8
MS
694 if (addr >= 0 && addr < PHY_MAX_ADDR)
695 bus->phymap[addr] = dev;
5f184715
AF
696
697 return dev;
698}
699
700/**
701 * get_phy_id - reads the specified addr for its ID.
702 * @bus: the target MII bus
703 * @addr: PHY address on the MII bus
704 * @phy_id: where to store the ID retrieved.
705 *
706 * Description: Reads the ID registers of the PHY at @addr on the
707 * @bus, stores it in @phy_id and returns zero on success.
708 */
5707d5ff 709int __weak get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
5f184715
AF
710{
711 int phy_reg;
712
8d631203
MS
713 /*
714 * Grab the bits from PHYIR1, and put them
715 * in the upper half
716 */
5f184715
AF
717 phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
718
719 if (phy_reg < 0)
720 return -EIO;
721
722 *phy_id = (phy_reg & 0xffff) << 16;
723
724 /* Grab the bits from PHYIR2, and put them in the lower half */
725 phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
726
727 if (phy_reg < 0)
728 return -EIO;
729
730 *phy_id |= (phy_reg & 0xffff);
731
732 return 0;
733}
734
1adb406b 735static struct phy_device *create_phy_by_mask(struct mii_dev *bus,
8d631203
MS
736 uint phy_mask, int devad,
737 phy_interface_t interface)
1adb406b
TK
738{
739 u32 phy_id = 0xffffffff;
b3eabd82 740 bool is_c45;
8d631203 741
1adb406b
TK
742 while (phy_mask) {
743 int addr = ffs(phy_mask) - 1;
744 int r = get_phy_id(bus, addr, devad, &phy_id);
3bf135b6
AM
745
746 /*
747 * If the PHY ID is flat 0 we ignore it. There are C45 PHYs
748 * that return all 0s for C22 reads (like Aquantia AQR112) and
749 * there are C22 PHYs that return all 0s for C45 reads (like
750 * Atheros AR8035).
751 */
752 if (r == 0 && phy_id == 0)
753 goto next;
754
1adb406b 755 /* If the PHY ID is mostly f's, we didn't find anything */
b3eabd82
PB
756 if (r == 0 && (phy_id & 0x1fffffff) != 0x1fffffff) {
757 is_c45 = (devad == MDIO_DEVAD_NONE) ? false : true;
758 return phy_device_create(bus, addr, phy_id, is_c45,
759 interface);
760 }
3bf135b6 761next:
1adb406b
TK
762 phy_mask &= ~(1 << addr);
763 }
764 return NULL;
765}
766
767static struct phy_device *search_for_existing_phy(struct mii_dev *bus,
8d631203
MS
768 uint phy_mask,
769 phy_interface_t interface)
1adb406b
TK
770{
771 /* If we have one, return the existing device, with new interface */
772 while (phy_mask) {
773 int addr = ffs(phy_mask) - 1;
8d631203 774
1adb406b
TK
775 if (bus->phymap[addr]) {
776 bus->phymap[addr]->interface = interface;
777 return bus->phymap[addr];
778 }
779 phy_mask &= ~(1 << addr);
780 }
781 return NULL;
782}
783
784static struct phy_device *get_phy_device_by_mask(struct mii_dev *bus,
8d631203
MS
785 uint phy_mask,
786 phy_interface_t interface)
1adb406b
TK
787{
788 int i;
789 struct phy_device *phydev;
790
791 phydev = search_for_existing_phy(bus, phy_mask, interface);
792 if (phydev)
793 return phydev;
794 /* Try Standard (ie Clause 22) access */
795 /* Otherwise we have to try Clause 45 */
796 for (i = 0; i < 5; i++) {
797 phydev = create_phy_by_mask(bus, phy_mask,
8d631203 798 i ? i : MDIO_DEVAD_NONE, interface);
1adb406b
TK
799 if (IS_ERR(phydev))
800 return NULL;
801 if (phydev)
802 return phydev;
803 }
3e1949d7
BM
804
805 debug("\n%s PHY: ", bus->name);
806 while (phy_mask) {
807 int addr = ffs(phy_mask) - 1;
8d631203 808
3e1949d7
BM
809 debug("%d ", addr);
810 phy_mask &= ~(1 << addr);
811 }
812 debug("not found\n");
0132b9ab
BM
813
814 return NULL;
1adb406b
TK
815}
816
5f184715 817/**
8d631203
MS
818 * get_phy_device - reads the specified PHY device and returns its
819 * @phy_device struct
5f184715
AF
820 * @bus: the target MII bus
821 * @addr: PHY address on the MII bus
822 *
823 * Description: Reads the ID registers of the PHY at @addr on the
824 * @bus, then allocates and returns the phy_device to represent it.
825 */
960d70c6
KP
826static struct phy_device *get_phy_device(struct mii_dev *bus, int addr,
827 phy_interface_t interface)
5f184715 828{
1adb406b 829 return get_phy_device_by_mask(bus, 1 << addr, interface);
5f184715
AF
830}
831
832int phy_reset(struct phy_device *phydev)
833{
834 int reg;
835 int timeout = 500;
836 int devad = MDIO_DEVAD_NONE;
837
ddcd1f30
SX
838 if (phydev->flags & PHY_FLAG_BROKEN_RESET)
839 return 0;
840
5f184715
AF
841#ifdef CONFIG_PHYLIB_10G
842 /* If it's 10G, we need to issue reset through one of the MMDs */
843 if (is_10g_interface(phydev->interface)) {
844 if (!phydev->mmds)
845 gen10g_discover_mmds(phydev);
846
847 devad = ffs(phydev->mmds) - 1;
848 }
849#endif
850
a058052c 851 if (phy_write(phydev, devad, MII_BMCR, BMCR_RESET) < 0) {
5f184715
AF
852 debug("PHY reset failed\n");
853 return -1;
854 }
855
856#ifdef CONFIG_PHY_RESET_DELAY
857 udelay(CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */
858#endif
859 /*
860 * Poll the control register for the reset bit to go to 0 (it is
861 * auto-clearing). This should happen within 0.5 seconds per the
862 * IEEE spec.
863 */
a058052c 864 reg = phy_read(phydev, devad, MII_BMCR);
5f184715
AF
865 while ((reg & BMCR_RESET) && timeout--) {
866 reg = phy_read(phydev, devad, MII_BMCR);
867
868 if (reg < 0) {
869 debug("PHY status read failed\n");
870 return -1;
871 }
872 udelay(1000);
873 }
874
875 if (reg & BMCR_RESET) {
876 puts("PHY reset timed out\n");
877 return -1;
878 }
879
880 return 0;
881}
882
883int miiphy_reset(const char *devname, unsigned char addr)
884{
885 struct mii_dev *bus = miiphy_get_dev_by_name(devname);
886 struct phy_device *phydev;
887
888 /*
889 * miiphy_reset was only used on standard PHYs, so we'll fake it here.
890 * If later code tries to connect with the right interface, this will
891 * be corrected by get_phy_device in phy_connect()
892 */
893 phydev = get_phy_device(bus, addr, PHY_INTERFACE_MODE_MII);
894
895 return phy_reset(phydev);
896}
897
8d631203
MS
898struct phy_device *phy_find_by_mask(struct mii_dev *bus, uint phy_mask,
899 phy_interface_t interface)
5f184715 900{
5f184715 901 /* Reset the bus */
59370f3f 902 if (bus->reset) {
e3a77218 903 bus->reset(bus);
5f184715 904
59370f3f 905 /* Wait 15ms to make sure the PHY has come out of hard reset */
8d631203 906 mdelay(15);
59370f3f
JK
907 }
908
1adb406b
TK
909 return get_phy_device_by_mask(bus, phy_mask, interface);
910}
5f184715 911
c74c8e66
SG
912#ifdef CONFIG_DM_ETH
913void phy_connect_dev(struct phy_device *phydev, struct udevice *dev)
914#else
1adb406b 915void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev)
c74c8e66 916#endif
1adb406b 917{
5f184715
AF
918 /* Soft Reset the PHY */
919 phy_reset(phydev);
17ecfa9b 920 if (phydev->dev && phydev->dev != dev) {
5f184715 921 printf("%s:%d is connected to %s. Reconnecting to %s\n",
8d631203
MS
922 phydev->bus->name, phydev->addr,
923 phydev->dev->name, dev->name);
1adb406b 924 }
5f184715 925 phydev->dev = dev;
b91a9d9d 926 debug("%s connected to %s\n", dev->name, phydev->drv->name);
1adb406b
TK
927}
928
f41e588c
SDPP
929#ifdef CONFIG_PHY_XILINX_GMII2RGMII
930#ifdef CONFIG_DM_ETH
931static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus,
932 struct udevice *dev,
933 phy_interface_t interface)
934#else
935static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus,
936 struct eth_device *dev,
937 phy_interface_t interface)
938#endif
939{
940 struct phy_device *phydev = NULL;
941 int sn = dev_of_offset(dev);
942 int off;
943
944 while (sn > 0) {
945 off = fdt_node_offset_by_compatible(gd->fdt_blob, sn,
946 "xlnx,gmii-to-rgmii-1.0");
947 if (off > 0) {
948 phydev = phy_device_create(bus, off,
949 PHY_GMII2RGMII_ID, false,
950 interface);
951 break;
952 }
953 if (off == -FDT_ERR_NOTFOUND)
954 sn = fdt_first_subnode(gd->fdt_blob, sn);
955 else
956 printf("%s: Error finding compat string:%d\n",
957 __func__, off);
958 }
959
960 return phydev;
961}
962#endif
963
c256d3f7 964#ifdef CONFIG_PHY_FIXED
c74c8e66 965#ifdef CONFIG_DM_ETH
c256d3f7
SDPP
966static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
967 struct udevice *dev,
968 phy_interface_t interface)
c74c8e66 969#else
c256d3f7
SDPP
970static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
971 struct eth_device *dev,
972 phy_interface_t interface)
c74c8e66 973#endif
1adb406b 974{
db40c1aa 975 struct phy_device *phydev = NULL;
db40c1aa
HS
976 int sn;
977 const char *name;
8d631203 978
da409ccc 979 sn = fdt_first_subnode(gd->fdt_blob, dev_of_offset(dev));
db40c1aa
HS
980 while (sn > 0) {
981 name = fdt_get_name(gd->fdt_blob, sn, NULL);
8d631203 982 if (name && strcmp(name, "fixed-link") == 0) {
b3eabd82
PB
983 phydev = phy_device_create(bus, sn, PHY_FIXED_ID, false,
984 interface);
db40c1aa
HS
985 break;
986 }
987 sn = fdt_next_subnode(gd->fdt_blob, sn);
988 }
c256d3f7
SDPP
989
990 return phydev;
991}
db40c1aa 992#endif
c256d3f7
SDPP
993
994#ifdef CONFIG_DM_ETH
995struct phy_device *phy_connect(struct mii_dev *bus, int addr,
996 struct udevice *dev,
997 phy_interface_t interface)
998#else
999struct phy_device *phy_connect(struct mii_dev *bus, int addr,
1000 struct eth_device *dev,
1001 phy_interface_t interface)
1002#endif
1003{
1004 struct phy_device *phydev = NULL;
1f607896 1005 uint mask = (addr >= 0) ? (1 << addr) : 0xffffffff;
c256d3f7
SDPP
1006
1007#ifdef CONFIG_PHY_FIXED
1008 phydev = phy_connect_fixed(bus, dev, interface);
1009#endif
e2ffeaa1
SMJ
1010
1011#ifdef CONFIG_PHY_NCSI
1012 if (!phydev)
1013 phydev = phy_device_create(bus, 0, PHY_NCSI_ID, false, interface);
1014#endif
1015
f41e588c
SDPP
1016#ifdef CONFIG_PHY_XILINX_GMII2RGMII
1017 if (!phydev)
1018 phydev = phy_connect_gmii2rgmii(bus, dev, interface);
1019#endif
c256d3f7 1020
8d631203 1021 if (!phydev)
afbc3194 1022 phydev = phy_find_by_mask(bus, mask, interface);
5f184715 1023
1adb406b
TK
1024 if (phydev)
1025 phy_connect_dev(phydev, dev);
1026 else
1027 printf("Could not get PHY for %s: addr %d\n", bus->name, addr);
5f184715
AF
1028 return phydev;
1029}
1030
6e5b9ac0
TT
1031/*
1032 * Start the PHY. Returns 0 on success, or a negative error code.
1033 */
5f184715
AF
1034int phy_startup(struct phy_device *phydev)
1035{
1036 if (phydev->drv->startup)
6e5b9ac0 1037 return phydev->drv->startup(phydev);
5f184715
AF
1038
1039 return 0;
1040}
1041
3c6928fd 1042__weak int board_phy_config(struct phy_device *phydev)
5f184715 1043{
9fafe7da
TK
1044 if (phydev->drv->config)
1045 return phydev->drv->config(phydev);
5f184715
AF
1046 return 0;
1047}
1048
5f184715
AF
1049int phy_config(struct phy_device *phydev)
1050{
5f184715 1051 /* Invoke an optional board-specific helper */
7a673f0b 1052 return board_phy_config(phydev);
5f184715
AF
1053}
1054
1055int phy_shutdown(struct phy_device *phydev)
1056{
1057 if (phydev->drv->shutdown)
1058 phydev->drv->shutdown(phydev);
1059
1060 return 0;
1061}
c74c8e66
SG
1062
1063int phy_get_interface_by_name(const char *str)
1064{
1065 int i;
1066
1067 for (i = 0; i < PHY_INTERFACE_MODE_COUNT; i++) {
1068 if (!strcmp(str, phy_interface_strings[i]))
1069 return i;
1070 }
1071
1072 return -1;
1073}
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