[u-boot.git] / drivers / i2c / rk_i2c.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2015 Google, Inc
 *
 * (C) Copyright 2008-2014 Rockchip Electronics
 * Peter, Software Engineering, <[email protected]>.
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <i2c.h>
#include <log.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/i2c.h>
#include <asm/arch-rockchip/periph.h>
#include <dm/pinctrl.h>
#include <linux/delay.h>
#include <linux/sizes.h>

/* i2c timerout */
#define I2C_TIMEOUT_MS		100
#define I2C_RETRY_COUNT		3

/* rk i2c fifo max transfer bytes */
#define RK_I2C_FIFO_SIZE	32

struct rk_i2c {
	struct clk clk;
	struct i2c_regs *regs;
	unsigned int speed;
};

enum {
	RK_I2C_LEGACY,
	RK_I2C_NEW,
};

/**
 * @controller_type: i2c controller type
 */
struct rk_i2c_soc_data {
	int controller_type;
};

static inline void rk_i2c_get_div(int div, int *divh, int *divl)
{
	*divl = div / 2;
	if (div % 2 == 0)
		*divh = div / 2;
	else
		*divh = DIV_ROUND_UP(div, 2);
}

/*
 * SCL Divisor = 8 * (CLKDIVL+1 + CLKDIVH+1)
 * SCL = PCLK / SCLK Divisor
 * i2c_rate = PCLK
 */
static void rk_i2c_set_clk(struct rk_i2c *i2c, uint32_t scl_rate)
{
	uint32_t i2c_rate;
	int div, divl, divh;

	/* First get i2c rate from pclk */
	i2c_rate = clk_get_rate(&i2c->clk);

	div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
	divh = 0;
	divl = 0;
	if (div >= 0)
		rk_i2c_get_div(div, &divh, &divl);
	writel(I2C_CLKDIV_VAL(divl, divh), &i2c->regs->clkdiv);

	debug("rk_i2c_set_clk: i2c rate = %d, scl rate = %d\n", i2c_rate,
	      scl_rate);
	debug("set i2c clk div = %d, divh = %d, divl = %d\n", div, divh, divl);
	debug("set clk(I2C_CLKDIV: 0x%08x)\n", readl(&i2c->regs->clkdiv));
}

static void rk_i2c_show_regs(struct i2c_regs *regs)
{
#ifdef DEBUG
	uint i;

	debug("i2c_con: 0x%08x\n", readl(&regs->con));
	debug("i2c_clkdiv: 0x%08x\n", readl(&regs->clkdiv));
	debug("i2c_mrxaddr: 0x%08x\n", readl(&regs->mrxaddr));
	debug("i2c_mrxraddR: 0x%08x\n", readl(&regs->mrxraddr));
	debug("i2c_mtxcnt: 0x%08x\n", readl(&regs->mtxcnt));
	debug("i2c_mrxcnt: 0x%08x\n", readl(&regs->mrxcnt));
	debug("i2c_ien: 0x%08x\n", readl(&regs->ien));
	debug("i2c_ipd: 0x%08x\n", readl(&regs->ipd));
	debug("i2c_fcnt: 0x%08x\n", readl(&regs->fcnt));
	for (i = 0; i < 8; i++)
		debug("i2c_txdata%d: 0x%08x\n", i, readl(&regs->txdata[i]));
	for (i = 0; i < 8; i++)
		debug("i2c_rxdata%d: 0x%08x\n", i, readl(&regs->rxdata[i]));
#endif
}

static int rk_i2c_send_start_bit(struct rk_i2c *i2c)
{
	struct i2c_regs *regs = i2c->regs;
	ulong start;

	debug("I2c Send Start bit.\n");
	writel(I2C_IPD_ALL_CLEAN, &regs->ipd);

	writel(I2C_CON_EN | I2C_CON_START, &regs->con);
	writel(I2C_STARTIEN, &regs->ien);

	start = get_timer(0);
	while (1) {
		if (readl(&regs->ipd) & I2C_STARTIPD) {
			writel(I2C_STARTIPD, &regs->ipd);
			break;
		}
		if (get_timer(start) > I2C_TIMEOUT_MS) {
			debug("I2C Send Start Bit Timeout\n");
			rk_i2c_show_regs(regs);
			return -ETIMEDOUT;
		}
		udelay(1);
	}

	return 0;
}

static int rk_i2c_send_stop_bit(struct rk_i2c *i2c)
{
	struct i2c_regs *regs = i2c->regs;
	ulong start;

	debug("I2c Send Stop bit.\n");
	writel(I2C_IPD_ALL_CLEAN, &regs->ipd);

	writel(I2C_CON_EN | I2C_CON_STOP, &regs->con);
	writel(I2C_CON_STOP, &regs->ien);

	start = get_timer(0);
	while (1) {
		if (readl(&regs->ipd) & I2C_STOPIPD) {
			writel(I2C_STOPIPD, &regs->ipd);
			break;
		}
		if (get_timer(start) > I2C_TIMEOUT_MS) {
			debug("I2C Send Start Bit Timeout\n");
			rk_i2c_show_regs(regs);
			return -ETIMEDOUT;
		}
		udelay(1);
	}

	return 0;
}

static inline void rk_i2c_disable(struct rk_i2c *i2c)
{
	writel(0, &i2c->regs->con);
}

static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
		       uchar *buf, uint b_len)
{
	struct i2c_regs *regs = i2c->regs;
	uchar *pbuf = buf;
	uint bytes_remain_len = b_len;
	uint bytes_xferred = 0;
	uint words_xferred = 0;
	ulong start;
	uint con = 0;
	uint rxdata;
	uint i, j;
	int err;
	bool snd_chunk = false;

	debug("rk_i2c_read: chip = %d, reg = %d, r_len = %d, b_len = %d\n",
	      chip, reg, r_len, b_len);

	err = rk_i2c_send_start_bit(i2c);
	if (err)
		return err;

	writel(I2C_MRXADDR_SET(1, chip << 1 | 1), &regs->mrxaddr);
	if (r_len == 0) {
		writel(0, &regs->mrxraddr);
	} else if (r_len < 4) {
		writel(I2C_MRXRADDR_SET(r_len, reg), &regs->mrxraddr);
	} else {
		debug("I2C Read: addr len %d not supported\n", r_len);
		return -EIO;
	}

	while (bytes_remain_len) {
		if (bytes_remain_len > RK_I2C_FIFO_SIZE) {
			con = I2C_CON_EN;
			bytes_xferred = 32;
		} else {
			/*
			 * The hw can read up to 32 bytes at a time. If we need
			 * more than one chunk, send an ACK after the last byte.
			 */
			con = I2C_CON_EN | I2C_CON_LASTACK;
			bytes_xferred = bytes_remain_len;
		}
		words_xferred = DIV_ROUND_UP(bytes_xferred, 4);

		/*
		 * make sure we are in plain RX mode if we read a second chunk
		 */
		if (snd_chunk)
			con |= I2C_CON_MOD(I2C_MODE_RX);
		else
			con |= I2C_CON_MOD(I2C_MODE_TRX);

		writel(con, &regs->con);
		writel(bytes_xferred, &regs->mrxcnt);
		writel(I2C_MBRFIEN | I2C_NAKRCVIEN, &regs->ien);

		start = get_timer(0);
		while (1) {
			if (readl(&regs->ipd) & I2C_NAKRCVIPD) {
				writel(I2C_NAKRCVIPD, &regs->ipd);
				err = -EREMOTEIO;
			}
			if (readl(&regs->ipd) & I2C_MBRFIPD) {
				writel(I2C_MBRFIPD, &regs->ipd);
				break;
			}
			if (get_timer(start) > I2C_TIMEOUT_MS) {
				debug("I2C Read Data Timeout\n");
				err =  -ETIMEDOUT;
				rk_i2c_show_regs(regs);
				goto i2c_exit;
			}
			udelay(1);
		}

		for (i = 0; i < words_xferred; i++) {
			rxdata = readl(&regs->rxdata[i]);
			debug("I2c Read RXDATA[%d] = 0x%x\n", i, rxdata);
			for (j = 0; j < 4; j++) {
				if ((i * 4 + j) == bytes_xferred)
					break;
				*pbuf++ = (rxdata >> (j * 8)) & 0xff;
			}
		}

		bytes_remain_len -= bytes_xferred;
		snd_chunk = true;
		debug("I2C Read bytes_remain_len %d\n", bytes_remain_len);
	}

i2c_exit:
	rk_i2c_disable(i2c);

	return err;
}

static int rk_i2c_write(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
			uchar *buf, uint b_len)
{
	struct i2c_regs *regs = i2c->regs;
	int err;
	uchar *pbuf = buf;
	uint bytes_remain_len = b_len + r_len + 1;
	uint bytes_xferred = 0;
	uint words_xferred = 0;
	ulong start;
	uint txdata;
	uint i, j;

	debug("rk_i2c_write: chip = %d, reg = %d, r_len = %d, b_len = %d\n",
	      chip, reg, r_len, b_len);
	err = rk_i2c_send_start_bit(i2c);
	if (err)
		return err;

	while (bytes_remain_len) {
		if (bytes_remain_len > RK_I2C_FIFO_SIZE)
			bytes_xferred = RK_I2C_FIFO_SIZE;
		else
			bytes_xferred = bytes_remain_len;
		words_xferred = DIV_ROUND_UP(bytes_xferred, 4);

		for (i = 0; i < words_xferred; i++) {
			txdata = 0;
			for (j = 0; j < 4; j++) {
				if ((i * 4 + j) == bytes_xferred)
					break;

				if (i == 0 && j == 0 && pbuf == buf) {
					txdata |= (chip << 1);
				} else if (i == 0 && j <= r_len && pbuf == buf) {
					txdata |= (reg &
						(0xff << ((j - 1) * 8))) << 8;
				} else {
					txdata |= (*pbuf++)<<(j * 8);
				}
			}
			writel(txdata, &regs->txdata[i]);
			debug("I2c Write TXDATA[%d] = 0x%08x\n", i, txdata);
		}

		writel(I2C_CON_EN | I2C_CON_MOD(I2C_MODE_TX), &regs->con);
		writel(bytes_xferred, &regs->mtxcnt);
		writel(I2C_MBTFIEN | I2C_NAKRCVIEN, &regs->ien);

		start = get_timer(0);
		while (1) {
			if (readl(&regs->ipd) & I2C_NAKRCVIPD) {
				writel(I2C_NAKRCVIPD, &regs->ipd);
				err = -EREMOTEIO;
			}
			if (readl(&regs->ipd) & I2C_MBTFIPD) {
				writel(I2C_MBTFIPD, &regs->ipd);
				break;
			}
			if (get_timer(start) > I2C_TIMEOUT_MS) {
				debug("I2C Write Data Timeout\n");
				err =  -ETIMEDOUT;
				rk_i2c_show_regs(regs);
				goto i2c_exit;
			}
			udelay(1);
		}

		bytes_remain_len -= bytes_xferred;
		debug("I2C Write bytes_remain_len %d\n", bytes_remain_len);
	}

i2c_exit:
	rk_i2c_disable(i2c);

	return err;
}

static int rockchip_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
			     int nmsgs)
{
	struct rk_i2c *i2c = dev_get_priv(bus);
	int ret;

	debug("i2c_xfer: %d messages\n", nmsgs);
	for (; nmsgs > 0; nmsgs--, msg++) {
		debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
		if (msg->flags & I2C_M_RD) {
			ret = rk_i2c_read(i2c, msg->addr, 0, 0, msg->buf,
					  msg->len);
		} else {
			ret = rk_i2c_write(i2c, msg->addr, 0, 0, msg->buf,
					   msg->len);
		}
		if (ret) {
			debug("i2c_write: error sending\n");
			return -EREMOTEIO;
		}
	}

	rk_i2c_send_stop_bit(i2c);
	rk_i2c_disable(i2c);

	return 0;
}

int rockchip_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
{
	struct rk_i2c *i2c = dev_get_priv(bus);

	rk_i2c_set_clk(i2c, speed);

	return 0;
}

static int rockchip_i2c_ofdata_to_platdata(struct udevice *bus)
{
	struct rk_i2c *priv = dev_get_priv(bus);
	int ret;

	ret = clk_get_by_index(bus, 0, &priv->clk);
	if (ret < 0) {
		debug("%s: Could not get clock for %s: %d\n", __func__,
		      bus->name, ret);
		return ret;
	}

	return 0;
}

static int rockchip_i2c_probe(struct udevice *bus)
{
	struct rk_i2c *priv = dev_get_priv(bus);
	struct rk_i2c_soc_data *soc_data;
	struct udevice *pinctrl;
	int bus_nr;
	int ret;

	priv->regs = dev_read_addr_ptr(bus);

	soc_data = (struct rk_i2c_soc_data*)dev_get_driver_data(bus);

	if (soc_data->controller_type == RK_I2C_LEGACY) {
		ret = dev_read_alias_seq(bus, &bus_nr);
		if (ret < 0) {
			debug("%s: Could not get alias for %s: %d\n",
			 __func__, bus->name, ret);
			return ret;
		}

		ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
		if (ret) {
			debug("%s: Cannot find pinctrl device\n", __func__);
			return ret;
		}

		/* pinctrl will switch I2C to new type */
		ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_I2C0 + bus_nr);
		if (ret) {
			debug("%s: Failed to switch I2C to new type %s: %d\n",
				__func__, bus->name, ret);
			return ret;
		}
	}

	return 0;
}

static const struct dm_i2c_ops rockchip_i2c_ops = {
	.xfer		= rockchip_i2c_xfer,
	.set_bus_speed	= rockchip_i2c_set_bus_speed,
};

static const struct rk_i2c_soc_data rk3066_soc_data = {
	.controller_type = RK_I2C_LEGACY,
};

static const struct rk_i2c_soc_data rk3188_soc_data = {
	.controller_type = RK_I2C_LEGACY,
};

static const struct rk_i2c_soc_data rk3228_soc_data = {
	.controller_type = RK_I2C_NEW,
};

static const struct rk_i2c_soc_data rk3288_soc_data = {
	.controller_type = RK_I2C_NEW,
};

static const struct rk_i2c_soc_data rk3328_soc_data = {
	.controller_type = RK_I2C_NEW,
};

static const struct rk_i2c_soc_data rk3399_soc_data = {
	.controller_type = RK_I2C_NEW,
};

static const struct udevice_id rockchip_i2c_ids[] = {
	{
		.compatible = "rockchip,rk3066-i2c",
		.data = (ulong)&rk3066_soc_data,
	},
	{
		.compatible = "rockchip,rk3188-i2c",
		.data = (ulong)&rk3188_soc_data,
	},
	{
		.compatible = "rockchip,rk3228-i2c",
		.data = (ulong)&rk3228_soc_data,
	},
	{
		.compatible = "rockchip,rk3288-i2c",
		.data = (ulong)&rk3288_soc_data,
	},
	{
		.compatible = "rockchip,rk3328-i2c",
		.data = (ulong)&rk3328_soc_data,
	},
	{
		.compatible = "rockchip,rk3399-i2c",
		.data = (ulong)&rk3399_soc_data,
	},
	{ }
};

U_BOOT_DRIVER(i2c_rockchip) = {
	.name	= "i2c_rockchip",
	.id	= UCLASS_I2C,
	.of_match = rockchip_i2c_ids,
	.ofdata_to_platdata = rockchip_i2c_ofdata_to_platdata,
	.probe	= rockchip_i2c_probe,
	.priv_auto_alloc_size = sizeof(struct rk_i2c),
	.ops	= &rockchip_i2c_ops,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
34374699 SG	2	/*
	3	* (C) Copyright 2015 Google, Inc
	4	*
	5	* (C) Copyright 2008-2014 Rockchip Electronics
	6	* Peter, Software Engineering, <[email protected]>.
34374699 SG	7	*/
	8
	9	#include <common.h>
	10	#include <clk.h>
	11	#include <dm.h>
	12	#include <errno.h>
	13	#include <i2c.h>
f7ae49fc	14	#include <log.h>
34374699	15	#include <asm/io.h>
15f09a1a KY	16	#include <asm/arch-rockchip/clock.h>
	17	#include <asm/arch-rockchip/i2c.h>
	18	#include <asm/arch-rockchip/periph.h>
34374699	19	#include <dm/pinctrl.h>
c05ed00a	20	#include <linux/delay.h>
34374699 SG	21	#include <linux/sizes.h>
34374699 SG	22
34374699 SG	23	/* i2c timerout */
	24	#define I2C_TIMEOUT_MS 100
	25	#define I2C_RETRY_COUNT 3
	26
	27	/* rk i2c fifo max transfer bytes */
	28	#define RK_I2C_FIFO_SIZE 32
	29
	30	struct rk_i2c {
135aa950	31	struct clk clk;
34374699 SG	32	struct i2c_regs *regs;
34374699 SG	33	unsigned int speed;
34374699 SG	34	};
34374699 SG	35
5944bd9a AK	36	enum {
	37	RK_I2C_LEGACY,
	38	RK_I2C_NEW,
	39	};
	40
	41	/**
	42	* @controller_type: i2c controller type
	43	*/
	44	struct rk_i2c_soc_data {
	45	int controller_type;
	46	};
	47
34374699 SG	48	static inline void rk_i2c_get_div(int div, int divh, int divl)
	49	{
	50	*divl = div / 2;
	51	if (div % 2 == 0)
	52	*divh = div / 2;
	53	else
	54	*divh = DIV_ROUND_UP(div, 2);
	55	}
	56
	57	/*
	58	* SCL Divisor = 8 * (CLKDIVL+1 + CLKDIVH+1)
	59	* SCL = PCLK / SCLK Divisor
	60	* i2c_rate = PCLK
	61	*/
	62	static void rk_i2c_set_clk(struct rk_i2c *i2c, uint32_t scl_rate)
	63	{
	64	uint32_t i2c_rate;
	65	int div, divl, divh;
	66
	67	/* First get i2c rate from pclk */
135aa950	68	i2c_rate = clk_get_rate(&i2c->clk);
34374699 SG	69
	70	div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
	71	divh = 0;
	72	divl = 0;
	73	if (div >= 0)
	74	rk_i2c_get_div(div, &divh, &divl);
	75	writel(I2C_CLKDIV_VAL(divl, divh), &i2c->regs->clkdiv);
	76
	77	debug("rk_i2c_set_clk: i2c rate = %d, scl rate = %d\n", i2c_rate,
	78	scl_rate);
	79	debug("set i2c clk div = %d, divh = %d, divl = %d\n", div, divh, divl);
	80	debug("set clk(I2C_CLKDIV: 0x%08x)\n", readl(&i2c->regs->clkdiv));
	81	}
	82
	83	static void rk_i2c_show_regs(struct i2c_regs *regs)
	84	{
	85	#ifdef DEBUG
	86	uint i;
	87
	88	debug("i2c_con: 0x%08x\n", readl(&regs->con));
	89	debug("i2c_clkdiv: 0x%08x\n", readl(&regs->clkdiv));
	90	debug("i2c_mrxaddr: 0x%08x\n", readl(&regs->mrxaddr));
	91	debug("i2c_mrxraddR: 0x%08x\n", readl(&regs->mrxraddr));
	92	debug("i2c_mtxcnt: 0x%08x\n", readl(&regs->mtxcnt));
	93	debug("i2c_mrxcnt: 0x%08x\n", readl(&regs->mrxcnt));
	94	debug("i2c_ien: 0x%08x\n", readl(&regs->ien));
	95	debug("i2c_ipd: 0x%08x\n", readl(&regs->ipd));
	96	debug("i2c_fcnt: 0x%08x\n", readl(&regs->fcnt));
	97	for (i = 0; i < 8; i++)
	98	debug("i2c_txdata%d: 0x%08x\n", i, readl(&regs->txdata[i]));
	99	for (i = 0; i < 8; i++)
	100	debug("i2c_rxdata%d: 0x%08x\n", i, readl(&regs->rxdata[i]));
	101	#endif
	102	}
	103
	104	static int rk_i2c_send_start_bit(struct rk_i2c *i2c)
	105	{
	106	struct i2c_regs *regs = i2c->regs;
	107	ulong start;
	108
	109	debug("I2c Send Start bit.\n");
	110	writel(I2C_IPD_ALL_CLEAN, &regs->ipd);
	111
	112	writel(I2C_CON_EN \| I2C_CON_START, &regs->con);
	113	writel(I2C_STARTIEN, &regs->ien);
	114
	115	start = get_timer(0);
	116	while (1) {
	117	if (readl(&regs->ipd) & I2C_STARTIPD) {
	118	writel(I2C_STARTIPD, &regs->ipd);
	119	break;
	120	}
	121	if (get_timer(start) > I2C_TIMEOUT_MS) {
	122	debug("I2C Send Start Bit Timeout\n");
	123	rk_i2c_show_regs(regs);
	124	return -ETIMEDOUT;
	125	}
	126	udelay(1);
	127	}
	128
	129	return 0;
	130	}
	131
	132	static int rk_i2c_send_stop_bit(struct rk_i2c *i2c)
133	{
134	struct i2c_regs *regs = i2c->regs;
135	ulong start;
136
137	debug("I2c Send Stop bit.\n");
138	writel(I2C_IPD_ALL_CLEAN, &regs->ipd);
139
140	writel(I2C_CON_EN \| I2C_CON_STOP, &regs->con);
141	writel(I2C_CON_STOP, &regs->ien);
142
143	start = get_timer(0);
144	while (1) {
145	if (readl(&regs->ipd) & I2C_STOPIPD) {
146	writel(I2C_STOPIPD, &regs->ipd);
147	break;
148	}
149	if (get_timer(start) > I2C_TIMEOUT_MS) {
150	debug("I2C Send Start Bit Timeout\n");
151	rk_i2c_show_regs(regs);
152	return -ETIMEDOUT;
153	}
154	udelay(1);
155	}
156
157	return 0;
158	}
159
160	static inline void rk_i2c_disable(struct rk_i2c *i2c)
161	{
162	writel(0, &i2c->regs->con);
163	}
164
165	static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
166	uchar *buf, uint b_len)
167	{
168	struct i2c_regs *regs = i2c->regs;
169	uchar *pbuf = buf;
170	uint bytes_remain_len = b_len;
171	uint bytes_xferred = 0;
172	uint words_xferred = 0;
173	ulong start;
174	uint con = 0;
175	uint rxdata;
176	uint i, j;
177	int err;
5deaa530	178	bool snd_chunk = false;
34374699 SG	179
	180	debug("rk_i2c_read: chip = %d, reg = %d, r_len = %d, b_len = %d\n",
	181	chip, reg, r_len, b_len);
	182
	183	err = rk_i2c_send_start_bit(i2c);
	184	if (err)
	185	return err;
	186
	187	writel(I2C_MRXADDR_SET(1, chip << 1 \| 1), &regs->mrxaddr);
	188	if (r_len == 0) {
	189	writel(0, &regs->mrxraddr);
	190	} else if (r_len < 4) {
	191	writel(I2C_MRXRADDR_SET(r_len, reg), &regs->mrxraddr);
	192	} else {
	193	debug("I2C Read: addr len %d not supported\n", r_len);
	194	return -EIO;
	195	}
	196
	197	while (bytes_remain_len) {
	198	if (bytes_remain_len > RK_I2C_FIFO_SIZE) {
5deaa530	199	con = I2C_CON_EN;
34374699 SG	200	bytes_xferred = 32;
34374699 SG	201	} else {
5deaa530 WE	202	/*
	203	* The hw can read up to 32 bytes at a time. If we need
	204	* more than one chunk, send an ACK after the last byte.
	205	*/
	206	con = I2C_CON_EN \| I2C_CON_LASTACK;
34374699 SG	207	bytes_xferred = bytes_remain_len;
	208	}
	209	words_xferred = DIV_ROUND_UP(bytes_xferred, 4);
	210
5deaa530 WE	211	/*
	212	* make sure we are in plain RX mode if we read a second chunk
	213	*/
	214	if (snd_chunk)
	215	con \|= I2C_CON_MOD(I2C_MODE_RX);
	216	else
	217	con \|= I2C_CON_MOD(I2C_MODE_TRX);
	218
34374699 SG	219	writel(con, &regs->con);
	220	writel(bytes_xferred, &regs->mrxcnt);
	221	writel(I2C_MBRFIEN \| I2C_NAKRCVIEN, &regs->ien);
	222
	223	start = get_timer(0);
	224	while (1) {
	225	if (readl(&regs->ipd) & I2C_NAKRCVIPD) {
	226	writel(I2C_NAKRCVIPD, &regs->ipd);
	227	err = -EREMOTEIO;
	228	}
	229	if (readl(&regs->ipd) & I2C_MBRFIPD) {
	230	writel(I2C_MBRFIPD, &regs->ipd);
	231	break;
	232	}
	233	if (get_timer(start) > I2C_TIMEOUT_MS) {
	234	debug("I2C Read Data Timeout\n");
	235	err = -ETIMEDOUT;
	236	rk_i2c_show_regs(regs);
	237	goto i2c_exit;
	238	}
	239	udelay(1);
	240	}
	241
	242	for (i = 0; i < words_xferred; i++) {
	243	rxdata = readl(&regs->rxdata[i]);
	244	debug("I2c Read RXDATA[%d] = 0x%x\n", i, rxdata);
	245	for (j = 0; j < 4; j++) {
	246	if ((i * 4 + j) == bytes_xferred)
	247	break;
	248	pbuf++ = (rxdata >> (j 8)) & 0xff;
	249	}
	250	}
	251
	252	bytes_remain_len -= bytes_xferred;
5deaa530	253	snd_chunk = true;
34374699 SG	254	debug("I2C Read bytes_remain_len %d\n", bytes_remain_len);
	255	}
	256
	257	i2c_exit:
34374699 SG	258	rk_i2c_disable(i2c);
	259
	260	return err;
	261	}
	262
	263	static int rk_i2c_write(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
	264	uchar *buf, uint b_len)
	265	{
	266	struct i2c_regs *regs = i2c->regs;
	267	int err;
	268	uchar *pbuf = buf;
	269	uint bytes_remain_len = b_len + r_len + 1;
	270	uint bytes_xferred = 0;
	271	uint words_xferred = 0;
	272	ulong start;
	273	uint txdata;
	274	uint i, j;
	275
	276	debug("rk_i2c_write: chip = %d, reg = %d, r_len = %d, b_len = %d\n",
	277	chip, reg, r_len, b_len);
	278	err = rk_i2c_send_start_bit(i2c);
	279	if (err)
	280	return err;
	281
	282	while (bytes_remain_len) {
	283	if (bytes_remain_len > RK_I2C_FIFO_SIZE)
80333fd8	284	bytes_xferred = RK_I2C_FIFO_SIZE;
34374699 SG	285	else
	286	bytes_xferred = bytes_remain_len;
	287	words_xferred = DIV_ROUND_UP(bytes_xferred, 4);
	288
	289	for (i = 0; i < words_xferred; i++) {
	290	txdata = 0;
	291	for (j = 0; j < 4; j++) {
	292	if ((i * 4 + j) == bytes_xferred)
	293	break;
	294
21d4b7d4	295	if (i == 0 && j == 0 && pbuf == buf) {
34374699	296	txdata \|= (chip << 1);
21d4b7d4	297	} else if (i == 0 && j <= r_len && pbuf == buf) {
34374699 SG	298	txdata \|= (reg &
	299	(0xff << ((j - 1) * 8))) << 8;
	300	} else {
	301	txdata \|= (pbuf++)<<(j 8);
	302	}
34374699	303	}
551288bd JK	304	writel(txdata, &regs->txdata[i]);
551288bd JK	305	debug("I2c Write TXDATA[%d] = 0x%08x\n", i, txdata);
34374699 SG	306	}
	307
	308	writel(I2C_CON_EN \| I2C_CON_MOD(I2C_MODE_TX), &regs->con);
	309	writel(bytes_xferred, &regs->mtxcnt);
	310	writel(I2C_MBTFIEN \| I2C_NAKRCVIEN, &regs->ien);
	311
	312	start = get_timer(0);
	313	while (1) {
	314	if (readl(&regs->ipd) & I2C_NAKRCVIPD) {
	315	writel(I2C_NAKRCVIPD, &regs->ipd);
	316	err = -EREMOTEIO;
	317	}
	318	if (readl(&regs->ipd) & I2C_MBTFIPD) {
	319	writel(I2C_MBTFIPD, &regs->ipd);
	320	break;
	321	}
	322	if (get_timer(start) > I2C_TIMEOUT_MS) {
	323	debug("I2C Write Data Timeout\n");
	324	err = -ETIMEDOUT;
	325	rk_i2c_show_regs(regs);
	326	goto i2c_exit;
	327	}
	328	udelay(1);
	329	}
	330
	331	bytes_remain_len -= bytes_xferred;
	332	debug("I2C Write bytes_remain_len %d\n", bytes_remain_len);
	333	}
	334
	335	i2c_exit:
34374699 SG	336	rk_i2c_disable(i2c);
	337
	338	return err;
	339	}
	340
	341	static int rockchip_i2c_xfer(struct udevice bus, struct i2c_msg msg,
	342	int nmsgs)
	343	{
	344	struct rk_i2c *i2c = dev_get_priv(bus);
	345	int ret;
	346
	347	debug("i2c_xfer: %d messages\n", nmsgs);
	348	for (; nmsgs > 0; nmsgs--, msg++) {
	349	debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
	350	if (msg->flags & I2C_M_RD) {
	351	ret = rk_i2c_read(i2c, msg->addr, 0, 0, msg->buf,
	352	msg->len);
	353	} else {
	354	ret = rk_i2c_write(i2c, msg->addr, 0, 0, msg->buf,
	355	msg->len);
	356	}
	357	if (ret) {
	358	debug("i2c_write: error sending\n");
	359	return -EREMOTEIO;
	360	}
	361	}
	362
c9fca5ec VK	363	rk_i2c_send_stop_bit(i2c);
	364	rk_i2c_disable(i2c);
	365
34374699 SG	366	return 0;
	367	}
	368
	369	int rockchip_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
	370	{
	371	struct rk_i2c *i2c = dev_get_priv(bus);
	372
	373	rk_i2c_set_clk(i2c, speed);
	374
	375	return 0;
	376	}
	377
930bc374	378	static int rockchip_i2c_ofdata_to_platdata(struct udevice *bus)
34374699	379	{
930bc374	380	struct rk_i2c *priv = dev_get_priv(bus);
34374699 SG	381	int ret;
34374699 SG	382
930bc374 SG	383	ret = clk_get_by_index(bus, 0, &priv->clk);
	384	if (ret < 0) {
	385	debug("%s: Could not get clock for %s: %d\n", __func__,
	386	bus->name, ret);
34374699	387	return ret;
930bc374	388	}
930bc374 SG	389
	390	return 0;
	391	}
	392
	393	static int rockchip_i2c_probe(struct udevice *bus)
	394	{
	395	struct rk_i2c *priv = dev_get_priv(bus);
5944bd9a AK	396	struct rk_i2c_soc_data *soc_data;
	397	struct udevice *pinctrl;
	398	int bus_nr;
	399	int ret;
930bc374	400
cc91bdf8	401	priv->regs = dev_read_addr_ptr(bus);
930bc374	402
5944bd9a AK	403	soc_data = (struct rk_i2c_soc_data*)dev_get_driver_data(bus);
	404
	405	if (soc_data->controller_type == RK_I2C_LEGACY) {
	406	ret = dev_read_alias_seq(bus, &bus_nr);
	407	if (ret < 0) {
	408	debug("%s: Could not get alias for %s: %d\n",
	409	__func__, bus->name, ret);
	410	return ret;
	411	}
	412
	413	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
	414	if (ret) {
	415	debug("%s: Cannot find pinctrl device\n", __func__);
	416	return ret;
	417	}
	418
	419	/* pinctrl will switch I2C to new type */
	420	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_I2C0 + bus_nr);
	421	if (ret) {
	422	debug("%s: Failed to switch I2C to new type %s: %d\n",
	423	__func__, bus->name, ret);
	424	return ret;
	425	}
	426	}
	427
930bc374	428	return 0;
34374699 SG	429	}
	430
	431	static const struct dm_i2c_ops rockchip_i2c_ops = {
	432	.xfer = rockchip_i2c_xfer,
	433	.set_bus_speed = rockchip_i2c_set_bus_speed,
	434	};
	435
5944bd9a AK	436	static const struct rk_i2c_soc_data rk3066_soc_data = {
	437	.controller_type = RK_I2C_LEGACY,
	438	};
	439
	440	static const struct rk_i2c_soc_data rk3188_soc_data = {
	441	.controller_type = RK_I2C_LEGACY,
	442	};
	443
	444	static const struct rk_i2c_soc_data rk3228_soc_data = {
	445	.controller_type = RK_I2C_NEW,
	446	};
	447
	448	static const struct rk_i2c_soc_data rk3288_soc_data = {
	449	.controller_type = RK_I2C_NEW,
	450	};
	451
	452	static const struct rk_i2c_soc_data rk3328_soc_data = {
	453	.controller_type = RK_I2C_NEW,
	454	};
	455
	456	static const struct rk_i2c_soc_data rk3399_soc_data = {
	457	.controller_type = RK_I2C_NEW,
	458	};
	459
34374699	460	static const struct udevice_id rockchip_i2c_ids[] = {
5944bd9a AK	461	{
	462	.compatible = "rockchip,rk3066-i2c",
	463	.data = (ulong)&rk3066_soc_data,
	464	},
	465	{
	466	.compatible = "rockchip,rk3188-i2c",
	467	.data = (ulong)&rk3188_soc_data,
	468	},
	469	{
	470	.compatible = "rockchip,rk3228-i2c",
	471	.data = (ulong)&rk3228_soc_data,
	472	},
	473	{
	474	.compatible = "rockchip,rk3288-i2c",
	475	.data = (ulong)&rk3288_soc_data,
	476	},
	477	{
	478	.compatible = "rockchip,rk3328-i2c",
	479	.data = (ulong)&rk3328_soc_data,
	480	},
	481	{
	482	.compatible = "rockchip,rk3399-i2c",
	483	.data = (ulong)&rk3399_soc_data,
	484	},
34374699 SG	485	{ }
	486	};
	487
	488	U_BOOT_DRIVER(i2c_rockchip) = {
	489	.name = "i2c_rockchip",
	490	.id = UCLASS_I2C,
	491	.of_match = rockchip_i2c_ids,
930bc374	492	.ofdata_to_platdata = rockchip_i2c_ofdata_to_platdata,
34374699 SG	493	.probe = rockchip_i2c_probe,
	494	.priv_auto_alloc_size = sizeof(struct rk_i2c),
	495	.ops = &rockchip_i2c_ops,
	496	};