[u-boot.git] / arch / arm / mach-tegra / cpu.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2010-2019, NVIDIA CORPORATION.  All rights reserved.
 */

#include <common.h>
#include <log.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/scu.h>
#include <linux/delay.h>
#include "cpu.h"

int get_num_cpus(void)
{
	struct apb_misc_gp_ctlr *gp;
	uint rev;
	debug("%s entry\n", __func__);

	gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
	rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;

	switch (rev) {
	case CHIPID_TEGRA20:
		return 2;
		break;
	case CHIPID_TEGRA30:
	case CHIPID_TEGRA114:
	case CHIPID_TEGRA124:
	case CHIPID_TEGRA210:
	default:
		return 4;
		break;
	}
}

/*
 * Timing tables for each SOC for all four oscillator options.
 */
struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
	/*
	 * T20: 1 GHz
	 *
	 * Register   Field  Bits   Width
	 * ------------------------------
	 * PLLX_BASE  p      22:20    3
	 * PLLX_BASE  n      17: 8   10
	 * PLLX_BASE  m       4: 0    5
	 * PLLX_MISC  cpcon  11: 8    4
	 */
	{
		{ .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
		{ .n =  625, .m = 12, .p = 0, .cpcon =  8 }, /* OSC: 19.2 MHz */
		{ .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
		{ .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
		{ .n =    0, .m =  0, .p = 0, .cpcon =  0 }, /* OSC: 38.4 MHz (N/A) */
		{ .n =    0, .m =  0, .p = 0, .cpcon =  0 }, /* OSC: 48.0 MHz (N/A) */
	},
	/*
	 * T25: 1.2 GHz
	 *
	 * Register   Field  Bits   Width
	 * ------------------------------
	 * PLLX_BASE  p      22:20    3
	 * PLLX_BASE  n      17: 8   10
	 * PLLX_BASE  m       4: 0    5
	 * PLLX_MISC  cpcon  11: 8    4
	 */
	{
		{ .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
		{ .n = 750, .m = 12, .p = 0, .cpcon =  8 }, /* OSC: 19.2 MHz */
		{ .n = 600, .m =  6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
		{ .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
		{ .n =   0, .m =  0, .p = 0, .cpcon =  0 }, /* OSC: 38.4 MHz (N/A) */
		{ .n =   0, .m =  0, .p = 0, .cpcon =  0 }, /* OSC: 48.0 MHz (N/A) */
	},
	/*
	 * T30: 600 MHz
	 *
	 * Register   Field  Bits   Width
	 * ------------------------------
	 * PLLX_BASE  p      22:20    3
	 * PLLX_BASE  n      17: 8   10
	 * PLLX_BASE  m       4: 0    5
	 * PLLX_MISC  cpcon  11: 8    4
	 */
	{
		{ .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
		{ .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
		{ .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
		{ .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
		{ .n =   0, .m =  0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
		{ .n =   0, .m =  0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
	},
	/*
	 * T114: 700 MHz
	 *
	 * Register   Field  Bits   Width
	 * ------------------------------
	 * PLLX_BASE  p      23:20    4
	 * PLLX_BASE  n      15: 8    8
	 * PLLX_BASE  m       7: 0    8
	 */
	{
		{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
		{ .n =  73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
		{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
		{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
		{ .n =   0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
		{ .n =   0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
	},

	/*
	 * T124: 700 MHz
	 *
	 * Register   Field  Bits   Width
	 * ------------------------------
	 * PLLX_BASE  p      23:20    4
	 * PLLX_BASE  n      15: 8    8
	 * PLLX_BASE  m       7: 0    8
	 */
	{
		{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
		{ .n =  73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
		{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
		{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
		{ .n =   0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
		{ .n =   0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
	},

	/*
	 * T210: 700 MHz
	 *
	 * Register   Field  Bits   Width
	 * ------------------------------
	 * PLLX_BASE  p      24:20    5
	 * PLLX_BASE  n      15: 8    8
	 * PLLX_BASE  m       7: 0    8
	 */
	{
		{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702   MHz*/
		{ .n =  73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
		{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696   MHz*/
		{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702   MHz*/
		{ .n =  36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */
		{ .n =  58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696   MHz */
	},
};

static inline void pllx_set_iddq(void)
{
#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	u32 reg;
	debug("%s entry\n", __func__);

	/* Disable IDDQ */
	reg = readl(&clkrst->crc_pllx_misc3);
	reg &= ~PLLX_IDDQ_MASK;
	writel(reg, &clkrst->crc_pllx_misc3);
	udelay(2);
	debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
	      readl(&clkrst->crc_pllx_misc3));
#endif
}

int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
		u32 divp, u32 cpcon)
{
	struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU];
	int chip = tegra_get_chip();
	u32 reg;
	debug("%s entry\n", __func__);

	/* If PLLX is already enabled, just return */
	if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
		debug("%s: PLLX already enabled, returning\n", __func__);
		return 0;
	}

	pllx_set_iddq();

	/* Set BYPASS, m, n and p to PLLX_BASE */
	reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift);
	reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift);
	writel(reg, &pll->pll_base);

	/* Set cpcon to PLLX_MISC */
	if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
		reg = (cpcon << pllinfo->kcp_shift);
	else
		reg = 0;

	/*
	 * TODO([email protected]) Check which SoCs use DCCON
	 * and add to pllinfo table if needed!
	 */
	 /* Set dccon to PLLX_MISC if freq > 600MHz */
	if (divn > 600)
		reg |= (1 << PLL_DCCON_SHIFT);
	writel(reg, &pll->pll_misc);

	/* Disable BYPASS */
	reg = readl(&pll->pll_base);
	reg &= ~PLL_BYPASS_MASK;
	writel(reg, &pll->pll_base);
	debug("%s: base = 0x%08X\n", __func__, reg);

	/* Set lock_enable to PLLX_MISC if lock_ena is valid (i.e. 0-31) */
	reg = readl(&pll->pll_misc);
	if (pllinfo->lock_ena < 32)
		reg |= (1 << pllinfo->lock_ena);
	writel(reg, &pll->pll_misc);
	debug("%s: misc = 0x%08X\n", __func__, reg);

	/* Enable PLLX last, once it's all configured */
	reg = readl(&pll->pll_base);
	reg |= PLL_ENABLE_MASK;
	writel(reg, &pll->pll_base);
	debug("%s: base final = 0x%08X\n", __func__, reg);

	return 0;
}

void init_pllx(void)
{
	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
	int soc_type, sku_info, chip_sku;
	enum clock_osc_freq osc;
	struct clk_pll_table *sel;
	debug("%s entry\n", __func__);

	/* get SOC (chip) type */
	soc_type = tegra_get_chip();
	debug("%s: SoC = 0x%02X\n", __func__, soc_type);

	/* get SKU info */
	sku_info = tegra_get_sku_info();
	debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info);

	/* get chip SKU, combo of the above info */
	chip_sku = tegra_get_chip_sku();
	debug("%s: Chip SKU = %d\n", __func__, chip_sku);

	/* get osc freq */
	osc = clock_get_osc_freq();
	debug("%s: osc = %d\n", __func__, osc);

	/* set pllx */
	sel = &tegra_pll_x_table[chip_sku][osc];
	pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
}

void enable_cpu_clock(int enable)
{
	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	u32 clk;
	debug("%s entry\n", __func__);

	/*
	 * NOTE:
	 * Regardless of whether the request is to enable or disable the CPU
	 * clock, every processor in the CPU complex except the master (CPU 0)
	 * will have it's clock stopped because the AVP only talks to the
	 * master.
	 */

	if (enable) {
		/* Initialize PLLX */
		init_pllx();

		/* Wait until all clocks are stable */
		udelay(PLL_STABILIZATION_DELAY);

		writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
		writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
	}

	/*
	 * Read the register containing the individual CPU clock enables and
	 * always stop the clocks to CPUs > 0.
	 */
	clk = readl(&clkrst->crc_clk_cpu_cmplx);
	clk |= 1 << CPU1_CLK_STP_SHIFT;
	if (get_num_cpus() == 4)
		clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);

	/* Stop/Unstop the CPU clock */
	clk &= ~CPU0_CLK_STP_MASK;
	clk |= !enable << CPU0_CLK_STP_SHIFT;
	writel(clk, &clkrst->crc_clk_cpu_cmplx);

	clock_enable(PERIPH_ID_CPU);
}

static int is_cpu_powered(void)
{
	return (tegra_pmc_readl(offsetof(struct pmc_ctlr,
				pmc_pwrgate_status)) & CPU_PWRED) ? 1 : 0;
}

static void remove_cpu_io_clamps(void)
{
	u32 reg;
	debug("%s entry\n", __func__);

	/* Remove the clamps on the CPU I/O signals */
	reg = tegra_pmc_readl(offsetof(struct pmc_ctlr, pmc_remove_clamping));
	reg |= CPU_CLMP;
	tegra_pmc_writel(reg, offsetof(struct pmc_ctlr, pmc_remove_clamping));

	/* Give I/O signals time to stabilize */
	udelay(IO_STABILIZATION_DELAY);
}

void powerup_cpu(void)
{
	u32 reg;
	int timeout = IO_STABILIZATION_DELAY;
	debug("%s entry\n", __func__);

	if (!is_cpu_powered()) {
		/* Toggle the CPU power state (OFF -> ON) */
		reg = tegra_pmc_readl(offsetof(struct pmc_ctlr,
				      pmc_pwrgate_toggle));
		reg &= PARTID_CP;
		reg |= START_CP;
		tegra_pmc_writel(reg,
				 offsetof(struct pmc_ctlr,
				 pmc_pwrgate_toggle));

		/* Wait for the power to come up */
		while (!is_cpu_powered()) {
			if (timeout-- == 0)
				printf("CPU failed to power up!\n");
			else
				udelay(10);
		}

		/*
		 * Remove the I/O clamps from CPU power partition.
		 * Recommended only on a Warm boot, if the CPU partition gets
		 * power gated. Shouldn't cause any harm when called after a
		 * cold boot according to HW, probably just redundant.
		 */
		remove_cpu_io_clamps();
	}
}

void reset_A9_cpu(int reset)
{
	/*
	* NOTE:  Regardless of whether the request is to hold the CPU in reset
	*        or take it out of reset, every processor in the CPU complex
	*        except the master (CPU 0) will be held in reset because the
	*        AVP only talks to the master. The AVP does not know that there
	*        are multiple processors in the CPU complex.
	*/
	int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
	int num_cpus = get_num_cpus();
	int cpu;

	debug("%s entry\n", __func__);
	/* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
	for (cpu = 1; cpu < num_cpus; cpu++)
		reset_cmplx_set_enable(cpu, mask, 1);
	reset_cmplx_set_enable(0, mask, reset);

	/* Enable/Disable master CPU reset */
	reset_set_enable(PERIPH_ID_CPU, reset);
}

void clock_enable_coresight(int enable)
{
	u32 rst, src = 2;

	debug("%s entry\n", __func__);
	clock_set_enable(PERIPH_ID_CORESIGHT, enable);
	reset_set_enable(PERIPH_ID_CORESIGHT, !enable);

	if (enable) {
		/*
		 * Put CoreSight on PLLP_OUT0 and divide it down as per
		 * PLLP base frequency based on SoC type (T20/T30+).
		 * Clock divider request would setup CSITE clock as 144MHz
		 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
		 */
		src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
		clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);

		/* Unlock the CPU CoreSight interfaces */
		rst = CORESIGHT_UNLOCK;
		writel(rst, CSITE_CPU_DBG0_LAR);
		writel(rst, CSITE_CPU_DBG1_LAR);
		if (get_num_cpus() == 4) {
			writel(rst, CSITE_CPU_DBG2_LAR);
			writel(rst, CSITE_CPU_DBG3_LAR);
		}
	}
}

void halt_avp(void)
{
	debug("%s entry\n", __func__);

	for (;;) {
		writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
		       FLOW_CTLR_HALT_COP_EVENTS);
	}
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0
1b245fee	2	/*
f9ec2ec8	3	* Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved.
1b245fee TW	4	*/
	5
	6	#include <common.h>
f7ae49fc	7	#include <log.h>
1b245fee TW	8	#include <asm/io.h>
	9	#include <asm/arch/clock.h>
	10	#include <asm/arch/gp_padctrl.h>
	11	#include <asm/arch/pinmux.h>
	12	#include <asm/arch/tegra.h>
	13	#include <asm/arch-tegra/clk_rst.h>
	14	#include <asm/arch-tegra/pmc.h>
	15	#include <asm/arch-tegra/scu.h>
c05ed00a	16	#include <linux/delay.h>
1b245fee TW	17	#include "cpu.h"
1b245fee TW	18
1b245fee TW	19	int get_num_cpus(void)
1b245fee TW	20	{
4040ec10 TW	21	struct apb_misc_gp_ctlr *gp;
4040ec10 TW	22	uint rev;
7aaa5a60	23	debug("%s entry\n", __func__);
4040ec10 TW	24
	25	gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
	26	rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
	27
	28	switch (rev) {
	29	case CHIPID_TEGRA20:
	30	return 2;
	31	break;
	32	case CHIPID_TEGRA30:
	33	case CHIPID_TEGRA114:
7aaa5a60 TW	34	case CHIPID_TEGRA124:
7aaa5a60 TW	35	case CHIPID_TEGRA210:
4040ec10 TW	36	default:
	37	return 4;
	38	break;
	39	}
1b245fee TW	40	}
	41
	42	/*
	43	* Timing tables for each SOC for all four oscillator options.
	44	*/
	45	struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
44de8e22 JZ	46	/*
	47	* T20: 1 GHz
	48	*
	49	* Register Field Bits Width
	50	* ------------------------------
	51	* PLLX_BASE p 22:20 3
	52	* PLLX_BASE n 17: 8 10
	53	* PLLX_BASE m 4: 0 5
	54	* PLLX_MISC cpcon 11: 8 4
	55	*/
	56	{
	57	{ .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
	58	{ .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
	59	{ .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
	60	{ .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
3e8650c0 TW	61	{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
3e8650c0 TW	62	{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
1b245fee	63	},
44de8e22 JZ	64	/*
	65	* T25: 1.2 GHz
	66	*
	67	* Register Field Bits Width
	68	* ------------------------------
	69	* PLLX_BASE p 22:20 3
	70	* PLLX_BASE n 17: 8 10
	71	* PLLX_BASE m 4: 0 5
	72	* PLLX_MISC cpcon 11: 8 4
	73	*/
	74	{
	75	{ .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
	76	{ .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
	77	{ .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
	78	{ .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
3e8650c0 TW	79	{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
3e8650c0 TW	80	{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
1b245fee	81	},
44de8e22	82	/*
2364e151	83	* T30: 600 MHz
44de8e22 JZ	84	*
	85	* Register Field Bits Width
	86	* ------------------------------
	87	* PLLX_BASE p 22:20 3
	88	* PLLX_BASE n 17: 8 10
	89	* PLLX_BASE m 4: 0 5
	90	* PLLX_MISC cpcon 11: 8 4
	91	*/
	92	{
2364e151 SW	93	{ .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
	94	{ .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
	95	{ .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
	96	{ .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
3e8650c0 TW	97	{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
3e8650c0 TW	98	{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
1b245fee	99	},
44de8e22 JZ	100	/*
	101	* T114: 700 MHz
	102	*
	103	* Register Field Bits Width
	104	* ------------------------------
	105	* PLLX_BASE p 23:20 4
	106	* PLLX_BASE n 15: 8 8
	107	* PLLX_BASE m 7: 0 8
	108	*/
	109	{
	110	{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
	111	{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
	112	{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
	113	{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
3e8650c0 TW	114	{ .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
3e8650c0 TW	115	{ .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
4040ec10	116	},
32edd2ed TW	117
	118	/*
	119	* T124: 700 MHz
	120	*
	121	* Register Field Bits Width
	122	* ------------------------------
	123	* PLLX_BASE p 23:20 4
	124	* PLLX_BASE n 15: 8 8
	125	* PLLX_BASE m 7: 0 8
	126	*/
	127	{
	128	{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
	129	{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
	130	{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
	131	{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
3e8650c0 TW	132	{ .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
3e8650c0 TW	133	{ .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
32edd2ed	134	},
7aaa5a60 TW	135
	136	/*
	137	* T210: 700 MHz
	138	*
	139	* Register Field Bits Width
	140	* ------------------------------
	141	* PLLX_BASE p 24:20 5
	142	* PLLX_BASE n 15: 8 8
	143	* PLLX_BASE m 7: 0 8
	144	*/
	145	{
	146	{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/
	147	{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
	148	{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/
	149	{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/
3e8650c0 TW	150	{ .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */
3e8650c0 TW	151	{ .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */
7aaa5a60	152	},
1b245fee TW	153	};
1b245fee TW	154
32edd2ed TW	155	static inline void pllx_set_iddq(void)
32edd2ed TW	156	{
7aaa5a60	157	#if defined(CONFIG_TEGRA124) \|\| defined(CONFIG_TEGRA210)
32edd2ed TW	158	struct clk_rst_ctlr clkrst = (struct clk_rst_ctlr )NV_PA_CLK_RST_BASE;
32edd2ed TW	159	u32 reg;
7aaa5a60	160	debug("%s entry\n", __func__);
32edd2ed TW	161
	162	/* Disable IDDQ */
	163	reg = readl(&clkrst->crc_pllx_misc3);
	164	reg &= ~PLLX_IDDQ_MASK;
	165	writel(reg, &clkrst->crc_pllx_misc3);
	166	udelay(2);
	167	debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
	168	readl(&clkrst->crc_pllx_misc3));
	169	#endif
	170	}
	171
1b245fee TW	172	int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
	173	u32 divp, u32 cpcon)
	174	{
722e000c	175	struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU];
4475c775	176	int chip = tegra_get_chip();
1b245fee	177	u32 reg;
7aaa5a60	178	debug("%s entry\n", __func__);
1b245fee TW	179
	180	/* If PLLX is already enabled, just return */
	181	if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
7aaa5a60	182	debug("%s: PLLX already enabled, returning\n", __func__);
1b245fee TW	183	return 0;
	184	}
	185
32edd2ed TW	186	pllx_set_iddq();
32edd2ed TW	187
1b245fee	188	/* Set BYPASS, m, n and p to PLLX_BASE */
722e000c TW	189	reg = PLL_BYPASS_MASK \| (divm << pllinfo->m_shift);
722e000c TW	190	reg \|= (divn << pllinfo->n_shift) \| (divp << pllinfo->p_shift);
1b245fee TW	191	writel(reg, &pll->pll_base);
	192
	193	/* Set cpcon to PLLX_MISC */
4475c775	194	if (chip == CHIPID_TEGRA20 \|\| chip == CHIPID_TEGRA30)
722e000c	195	reg = (cpcon << pllinfo->kcp_shift);
4475c775 TR	196	else
4475c775 TR	197	reg = 0;
1b245fee	198
722e000c TW	199	/*
	200	* TODO([email protected]) Check which SoCs use DCCON
	201	* and add to pllinfo table if needed!
	202	*/
	203	/* Set dccon to PLLX_MISC if freq > 600MHz */
1b245fee TW	204	if (divn > 600)
	205	reg \|= (1 << PLL_DCCON_SHIFT);
	206	writel(reg, &pll->pll_misc);
	207
1b245fee	208	/* Disable BYPASS */
41447fb2	209	reg = readl(&pll->pll_base);
1b245fee TW	210	reg &= ~PLL_BYPASS_MASK;
1b245fee TW	211	writel(reg, &pll->pll_base);
7aaa5a60	212	debug("%s: base = 0x%08X\n", __func__, reg);
1b245fee	213
722e000c	214	/* Set lock_enable to PLLX_MISC if lock_ena is valid (i.e. 0-31) */
1b245fee	215	reg = readl(&pll->pll_misc);
722e000c TW	216	if (pllinfo->lock_ena < 32)
722e000c TW	217	reg \|= (1 << pllinfo->lock_ena);
1b245fee	218	writel(reg, &pll->pll_misc);
7aaa5a60	219	debug("%s: misc = 0x%08X\n", __func__, reg);
41447fb2 SW	220
	221	/* Enable PLLX last, once it's all configured */
	222	reg = readl(&pll->pll_base);
	223	reg \|= PLL_ENABLE_MASK;
	224	writel(reg, &pll->pll_base);
7aaa5a60	225	debug("%s: base final = 0x%08X\n", __func__, reg);
1b245fee TW	226
	227	return 0;
	228	}
	229
	230	void init_pllx(void)
	231	{
	232	struct clk_rst_ctlr clkrst = (struct clk_rst_ctlr )NV_PA_CLK_RST_BASE;
	233	struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
49493cb7	234	int soc_type, sku_info, chip_sku;
1b245fee TW	235	enum clock_osc_freq osc;
1b245fee TW	236	struct clk_pll_table *sel;
7aaa5a60	237	debug("%s entry\n", __func__);
1b245fee	238
49493cb7 TW	239	/* get SOC (chip) type */
49493cb7 TW	240	soc_type = tegra_get_chip();
7aaa5a60	241	debug("%s: SoC = 0x%02X\n", __func__, soc_type);
49493cb7 TW	242
	243	/* get SKU info */
	244	sku_info = tegra_get_sku_info();
7aaa5a60	245	debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info);
49493cb7 TW	246
	247	/* get chip SKU, combo of the above info */
	248	chip_sku = tegra_get_chip_sku();
7aaa5a60	249	debug("%s: Chip SKU = %d\n", __func__, chip_sku);
1b245fee TW	250
	251	/* get osc freq */
	252	osc = clock_get_osc_freq();
7aaa5a60	253	debug("%s: osc = %d\n", __func__, osc);
1b245fee TW	254
1b245fee TW	255	/* set pllx */
49493cb7	256	sel = &tegra_pll_x_table[chip_sku][osc];
1b245fee	257	pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
1b245fee TW	258	}
	259
	260	void enable_cpu_clock(int enable)
	261	{
	262	struct clk_rst_ctlr clkrst = (struct clk_rst_ctlr )NV_PA_CLK_RST_BASE;
	263	u32 clk;
7aaa5a60	264	debug("%s entry\n", __func__);
1b245fee TW	265
	266	/*
	267	* NOTE:
	268	* Regardless of whether the request is to enable or disable the CPU
	269	* clock, every processor in the CPU complex except the master (CPU 0)
	270	* will have it's clock stopped because the AVP only talks to the
	271	* master.
	272	*/
	273
	274	if (enable) {
	275	/* Initialize PLLX */
	276	init_pllx();
	277
	278	/* Wait until all clocks are stable */
	279	udelay(PLL_STABILIZATION_DELAY);
	280
	281	writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
	282	writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
	283	}
	284
	285	/*
	286	* Read the register containing the individual CPU clock enables and
	287	* always stop the clocks to CPUs > 0.
	288	*/
	289	clk = readl(&clkrst->crc_clk_cpu_cmplx);
	290	clk \|= 1 << CPU1_CLK_STP_SHIFT;
4040ec10 TW	291	if (get_num_cpus() == 4)
	292	clk \|= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
	293
1b245fee TW	294	/* Stop/Unstop the CPU clock */
	295	clk &= ~CPU0_CLK_STP_MASK;
	296	clk \|= !enable << CPU0_CLK_STP_SHIFT;
	297	writel(clk, &clkrst->crc_clk_cpu_cmplx);
	298
	299	clock_enable(PERIPH_ID_CPU);
	300	}
	301
	302	static int is_cpu_powered(void)
	303	{
f9ec2ec8 TR	304	return (tegra_pmc_readl(offsetof(struct pmc_ctlr,
f9ec2ec8 TR	305	pmc_pwrgate_status)) & CPU_PWRED) ? 1 : 0;
1b245fee TW	306	}
	307
	308	static void remove_cpu_io_clamps(void)
	309	{
1b245fee	310	u32 reg;
7aaa5a60	311	debug("%s entry\n", __func__);
1b245fee TW	312
1b245fee TW	313	/* Remove the clamps on the CPU I/O signals */
f9ec2ec8	314	reg = tegra_pmc_readl(offsetof(struct pmc_ctlr, pmc_remove_clamping));
1b245fee	315	reg \|= CPU_CLMP;
f9ec2ec8	316	tegra_pmc_writel(reg, offsetof(struct pmc_ctlr, pmc_remove_clamping));
1b245fee TW	317
	318	/* Give I/O signals time to stabilize */
	319	udelay(IO_STABILIZATION_DELAY);
	320	}
	321
	322	void powerup_cpu(void)
	323	{
1b245fee TW	324	u32 reg;
1b245fee TW	325	int timeout = IO_STABILIZATION_DELAY;
7aaa5a60	326	debug("%s entry\n", __func__);
1b245fee TW	327
	328	if (!is_cpu_powered()) {
	329	/* Toggle the CPU power state (OFF -> ON) */
f9ec2ec8 TR	330	reg = tegra_pmc_readl(offsetof(struct pmc_ctlr,
f9ec2ec8 TR	331	pmc_pwrgate_toggle));
1b245fee TW	332	reg &= PARTID_CP;
1b245fee TW	333	reg \|= START_CP;
f9ec2ec8 TR	334	tegra_pmc_writel(reg,
	335	offsetof(struct pmc_ctlr,
	336	pmc_pwrgate_toggle));
1b245fee TW	337
	338	/* Wait for the power to come up */
	339	while (!is_cpu_powered()) {
	340	if (timeout-- == 0)
	341	printf("CPU failed to power up!\n");
	342	else
	343	udelay(10);
	344	}
	345
	346	/*
	347	* Remove the I/O clamps from CPU power partition.
	348	* Recommended only on a Warm boot, if the CPU partition gets
	349	* power gated. Shouldn't cause any harm when called after a
	350	* cold boot according to HW, probably just redundant.
	351	*/
	352	remove_cpu_io_clamps();
	353	}
	354	}
	355
	356	void reset_A9_cpu(int reset)
	357	{
	358	/*
	359	* NOTE: Regardless of whether the request is to hold the CPU in reset
	360	* or take it out of reset, every processor in the CPU complex
	361	* except the master (CPU 0) will be held in reset because the
	362	* AVP only talks to the master. The AVP does not know that there
	363	* are multiple processors in the CPU complex.
	364	*/
	365	int mask = crc_rst_cpu \| crc_rst_de \| crc_rst_debug;
	366	int num_cpus = get_num_cpus();
	367	int cpu;
	368
7aaa5a60	369	debug("%s entry\n", __func__);
1b245fee TW	370	/* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
	371	for (cpu = 1; cpu < num_cpus; cpu++)
	372	reset_cmplx_set_enable(cpu, mask, 1);
	373	reset_cmplx_set_enable(0, mask, reset);
	374
	375	/* Enable/Disable master CPU reset */
	376	reset_set_enable(PERIPH_ID_CPU, reset);
	377	}
	378
	379	void clock_enable_coresight(int enable)
	380	{
4040ec10	381	u32 rst, src = 2;
1b245fee	382
7aaa5a60	383	debug("%s entry\n", __func__);
1b245fee TW	384	clock_set_enable(PERIPH_ID_CORESIGHT, enable);
	385	reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
	386
	387	if (enable) {
	388	/*
49493cb7	389	* Put CoreSight on PLLP_OUT0 and divide it down as per
32edd2ed	390	* PLLP base frequency based on SoC type (T20/T30+).
49493cb7 TW	391	* Clock divider request would setup CSITE clock as 144MHz
49493cb7 TW	392	* for PLLP base 216MHz and 204MHz for PLLP base 408MHz
1b245fee	393	*/
a4bcd67c	394	src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
1b245fee TW	395	clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
	396
	397	/* Unlock the CPU CoreSight interfaces */
	398	rst = CORESIGHT_UNLOCK;
	399	writel(rst, CSITE_CPU_DBG0_LAR);
	400	writel(rst, CSITE_CPU_DBG1_LAR);
4040ec10 TW	401	if (get_num_cpus() == 4) {
	402	writel(rst, CSITE_CPU_DBG2_LAR);
	403	writel(rst, CSITE_CPU_DBG3_LAR);
	404	}
1b245fee TW	405	}
	406	}
	407
	408	void halt_avp(void)
	409	{
7aaa5a60 TW	410	debug("%s entry\n", __func__);
7aaa5a60 TW	411
1b245fee	412	for (;;) {
716ff5ce SW	413	writel(HALT_COP_EVENT_JTAG \| (FLOW_MODE_STOP << 29),
716ff5ce SW	414	FLOW_CTLR_HALT_COP_EVENTS);
1b245fee TW	415	}
1b245fee TW	416	}