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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
d1712369 | 2 | /* |
2a9fab82 | 3 | * Copyright 2008-2011 Freescale Semiconductor, Inc. |
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4 | * |
5 | * (C) Copyright 2000 | |
6 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
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7 | */ |
8 | ||
9 | #include <common.h> | |
10 | #include <asm/mmu.h> | |
11 | ||
12 | struct fsl_e_tlb_entry tlb_table[] = { | |
13 | /* TLB 0 - for temp stack in cache */ | |
14 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, | |
15 | CONFIG_SYS_INIT_RAM_ADDR_PHYS, | |
86df5142 | 16 | MAS3_SW|MAS3_SR, 0, |
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17 | 0, 0, BOOKE_PAGESZ_4K, 0), |
18 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, | |
19 | CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, | |
86df5142 | 20 | MAS3_SW|MAS3_SR, 0, |
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21 | 0, 0, BOOKE_PAGESZ_4K, 0), |
22 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, | |
23 | CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, | |
86df5142 | 24 | MAS3_SW|MAS3_SR, 0, |
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25 | 0, 0, BOOKE_PAGESZ_4K, 0), |
26 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, | |
27 | CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, | |
86df5142 | 28 | MAS3_SW|MAS3_SR, 0, |
d1712369 | 29 | 0, 0, BOOKE_PAGESZ_4K, 0), |
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30 | #ifdef CPLD_BASE |
31 | SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS, | |
32 | MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
33 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
34 | #endif | |
d1712369 | 35 | |
f8bc7bb5 | 36 | #ifdef PIXIS_BASE |
d1712369 | 37 | SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS, |
86df5142 | 38 | MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
d1712369 | 39 | 0, 0, BOOKE_PAGESZ_4K, 0), |
f8bc7bb5 | 40 | #endif |
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41 | |
42 | /* TLB 1 */ | |
43 | /* *I*** - Covers boot page */ | |
2a9fab82 | 44 | #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) |
467a40df | 45 | |
bef18454 | 46 | #if !defined(CONFIG_NXP_ESBC) |
2a9fab82 SX |
47 | /* |
48 | * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the | |
49 | * SRAM is at 0xfff00000, it covered the 0xfffff000. | |
50 | */ | |
51 | SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, | |
52 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
53 | 0, 0, BOOKE_PAGESZ_1M, 1), | |
467a40df AB |
54 | #else |
55 | /* | |
56 | * *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot | |
57 | * the physical address of the SRAM is at CONFIG_SYS_INIT_L3_ADDR, | |
58 | * and virtual address is CONFIG_SYS_MONITOR_BASE | |
59 | */ | |
60 | ||
61 | SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE & 0xfff00000, | |
62 | CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, | |
63 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
64 | 0, 0, BOOKE_PAGESZ_1M, 1), | |
65 | #endif | |
66 | ||
461632bd | 67 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
292dc6c5 | 68 | /* |
461632bd | 69 | * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the |
292dc6c5 LG |
70 | * space is at 0xfff00000, it covered the 0xfffff000. |
71 | */ | |
461632bd LG |
72 | SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, |
73 | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, | |
292dc6c5 LG |
74 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, |
75 | 0, 0, BOOKE_PAGESZ_1M, 1), | |
2a9fab82 | 76 | #else |
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77 | SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, |
78 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
79 | 0, 0, BOOKE_PAGESZ_4K, 1), | |
2a9fab82 | 80 | #endif |
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81 | |
82 | /* *I*G* - CCSRBAR */ | |
83 | SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, | |
86df5142 | 84 | MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
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85 | 0, 1, BOOKE_PAGESZ_16M, 1), |
86 | ||
87 | /* *I*G* - Flash, localbus */ | |
88 | /* This will be changed to *I*G* after relocation to RAM. */ | |
89 | SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, | |
90 | MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, | |
91 | 0, 2, BOOKE_PAGESZ_256M, 1), | |
92 | ||
93 | /* *I*G* - PCI */ | |
94 | SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, | |
86df5142 | 95 | MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
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96 | 0, 3, BOOKE_PAGESZ_1G, 1), |
97 | ||
98 | /* *I*G* - PCI */ | |
99 | SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, | |
100 | CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, | |
86df5142 | 101 | MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
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102 | 0, 4, BOOKE_PAGESZ_256M, 1), |
103 | ||
104 | SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, | |
105 | CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, | |
86df5142 | 106 | MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
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107 | 0, 5, BOOKE_PAGESZ_256M, 1), |
108 | ||
109 | /* *I*G* - PCI I/O */ | |
110 | SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, | |
86df5142 | 111 | MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
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112 | 0, 6, BOOKE_PAGESZ_256K, 1), |
113 | ||
114 | /* Bman/Qman */ | |
be1ff615 | 115 | #ifdef CONFIG_SYS_BMAN_MEM_PHYS |
d1712369 | 116 | SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, |
86df5142 | 117 | MAS3_SW|MAS3_SR, 0, |
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118 | 0, 9, BOOKE_PAGESZ_1M, 1), |
119 | SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, | |
120 | CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, | |
86df5142 | 121 | MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
d1712369 | 122 | 0, 10, BOOKE_PAGESZ_1M, 1), |
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123 | #endif |
124 | #ifdef CONFIG_SYS_QMAN_MEM_PHYS | |
d1712369 | 125 | SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, |
86df5142 | 126 | MAS3_SW|MAS3_SR, 0, |
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127 | 0, 11, BOOKE_PAGESZ_1M, 1), |
128 | SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, | |
129 | CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, | |
86df5142 | 130 | MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
d1712369 | 131 | 0, 12, BOOKE_PAGESZ_1M, 1), |
be1ff615 | 132 | #endif |
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133 | #ifdef CONFIG_SYS_DCSRBAR_PHYS |
134 | SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, | |
86df5142 | 135 | MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
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136 | 0, 13, BOOKE_PAGESZ_4M, 1), |
137 | #endif | |
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138 | #ifdef CONFIG_SYS_NAND_BASE |
139 | /* | |
140 | * *I*G - NAND | |
141 | * entry 14 and 15 has been used hard coded, they will be disabled | |
142 | * in cpu_init_f, so we use entry 16 for nand. | |
143 | */ | |
144 | SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, | |
145 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
146 | 0, 16, BOOKE_PAGESZ_1M, 1), | |
147 | #endif | |
461632bd | 148 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE |
3f1af81b | 149 | /* |
461632bd LG |
150 | * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for |
151 | * fetching ucode and ENV from master | |
3f1af81b | 152 | */ |
461632bd LG |
153 | SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, |
154 | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, | |
3f1af81b LG |
155 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, |
156 | 0, 17, BOOKE_PAGESZ_1M, 1), | |
157 | #endif | |
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158 | }; |
159 | ||
160 | int num_tlb_entries = ARRAY_SIZE(tlb_table); |