[u-boot.git] / include / configs / P3041DS.h

/*
 * Copyright 2010-2011 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * P3041 DS board configuration file
 *
 */
#define CONFIG_P3041DS
#define CONFIG_PPC_P3041

#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */

#define CONFIG_MMC
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE3
#define CONFIG_PCIE4
#define CONFIG_SYS_DPAA_RMAN

#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1			/* SRIO port 1 */
#define CONFIG_SRIO2			/* SRIO port 2 */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */

#include "corenet_ds.h"
Commit	Line	Data
e02aea61 KG	1	/*
	2	* Copyright 2010-2011 Freescale Semiconductor, Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
e02aea61 KG	5	*/
	6
	7	/*
	8	* P3041 DS board configuration file
	9	*
	10	*/
	11	#define CONFIG_P3041DS
e02aea61 KG	12	#define CONFIG_PPC_P3041
e02aea61 KG	13
c6d33901 KG	14	#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
	15
	16	#define CONFIG_MMC
	17	#define CONFIG_NAND_FSL_ELBC
9760b274	18	#define CONFIG_FSL_SATA_V2
c6d33901	19	#define CONFIG_PCIE3
e02aea61	20	#define CONFIG_PCIE4
4d28db8a	21	#define CONFIG_SYS_DPAA_RMAN
e02aea61	22
11860d88 TT	23	#define CONFIG_SYS_SRIO
	24	#define CONFIG_SRIO1 /* SRIO port 1 */
	25	#define CONFIG_SRIO2 /* SRIO port 2 */
c8b28152	26	#define CONFIG_SRIO_PCIE_BOOT_MASTER
e02aea61 KG	27	#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
	28
	29	#include "corenet_ds.h"