[u-boot.git] / include / configs / ebony.h

/*
 * (C) Copyright 2002 Scott McNutt <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
 ***********************************************************************/

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_EBONY		1	    /* Board is ebony		*/
#define CONFIG_440GP		1	    /* Specifc GP support	*/
#define CONFIG_440		1	    /* ... PPC440 family	*/
#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
#undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/

/*
 * Define here the location of the environment variables (FLASH or NVRAM).
 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
 *       supported for backward compatibility.
 */
#if 1
#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
#else
#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
#endif

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
#define CFG_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
#define CFG_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
#define CFG_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
#define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
#define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
#define CFG_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/

#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
#define CFG_FPGA_BASE	    (CFG_PERIPHERAL_BASE + 0x08300000)

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in internal SRAM)
 *----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address	*/
#define CFG_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
#define CFG_GBL_DATA_SIZE  128		    /* num bytes initial data	*/

#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
#define CONFIG_BAUDRATE		115200

#define CFG_BAUDRATE_TABLE  \
    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}

/*-----------------------------------------------------------------------
 * NVRAM/RTC
 *
 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
 * The DS1743 code assumes this condition (i.e. -- it assumes the base
 * address for the RTC registers is:
 *
 *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
 *
 *----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE	    (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS174x	1		    /* DS1743 RTC		*/

#ifdef CFG_ENV_IS_IN_NVRAM
#define CFG_ENV_SIZE		0x1000	    /* Size of Environment vars */
#define CFG_ENV_ADDR		\
	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_NVRAM */

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CFG_MAX_FLASH_BANKS	3		    /* number of banks	    */
#define CFG_MAX_FLASH_SECT	32		    /* sectors per device   */

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#define CFG_FLASH_ADDR0         0x5555
#define CFG_FLASH_ADDR1         0x2aaa
#define CFG_FLASH_WORD_SIZE     unsigned char

#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE	0x10000	/* size of one complete sector		*/
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
#define SPD_EEPROM_ADDRESS {0x53,0x52}	/* SPD i2c spd addresses	*/
#define CONFIG_PROG_SDRAM_TLB	1	/* setup SDRAM TLB's dynamically*/

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=ebony\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
	        "bootm\0"						\
	"rootpath=/opt/eldk/ppc_4xx\0"					\
	"bootfile=/tftpboot/ebony/uImage\0"				\
	"kernel_addr=ff800000\0"					\
	"ramdisk_addr=ff810000\0"					\
	"initrd_high=30000000\0"					\
	"load=tftp 100000 /tftpboot/ebony/u-boot.bin\0"		        \
	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
		"cp.b 100000 fffc0000 40000;"			        \
		"setenv filesize;saveenv\0"				\
	"upd=run load;run update\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define CONFIG_BAUDRATE		115200

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		8	/* PHY address			*/
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR	9	/* EMAC1 PHY address		*/
#define CONFIG_NET_MULTI	1
#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */

#define CONFIG_NETCONSOLE		/* include NetConsole support	*/

#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
				CFG_CMD_ASKENV	| \
				CFG_CMD_DATE	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_DIAG	| \
				CFG_CMD_ELF	| \
				CFG_CMD_EEPROM	| \
				CFG_CMD_I2C	| \
				CFG_CMD_IRQ	| \
				CFG_CMD_MII	| \
				CFG_CMD_NET	| \
				CFG_CMD_NFS	| \
				CFG_CMD_PCI	| \
				CFG_CMD_PING	| \
				CFG_CMD_REGINFO	| \
				CFG_CMD_SDRAM	| \
				CFG_CMD_SNTP	)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */
#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CONFIG_LOOPW            1       /* enable loopw command         */
#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
/* General PCI */
#define CONFIG_PCI			            /* include pci support	        */
#define CONFIG_PCI_PNP			        /* do pci plug-and-play         */
#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
#define CFG_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CFG_PCI_MEMBASE */

/* Board-specific PCI */
#define CFG_PCI_TARGET_INIT	            /* let board init pci target    */

#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
#define CFG_CACHELINE_SIZE	32	/* ...			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif
#endif	/* __CONFIG_H */
Commit	Line	Data
acea76a2 WD	1	/*
	2	* (C) Copyright 2002 Scott McNutt <[email protected]>
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	/************************************************************************
0c8721a4	24	* board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
acea76a2 WD	25	***********************************************************************/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	/*-----------------------------------------------------------------------
	31	* High Level Configuration Options
	32	----------------------------------------------------------------------/
	33	#define CONFIG_EBONY 1 /* Board is ebony */
4a3cd9e6	34	#define CONFIG_440GP 1 /* Specifc GP support */
efa35cf1	35	#define CONFIG_440 1 /* ... PPC440 family */
acea76a2	36	#define CONFIG_4xx 1 /* ... PPC4xx family */
c837dcb1	37	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
acea76a2 WD	38	#undef CFG_DRAM_TEST /* Disable-takes long time! */
	39	#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
	40
8a316c9b SR	41	/*
	42	* Define here the location of the environment variables (FLASH or NVRAM).
	43	* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
	44	* supported for backward compatibility.
	45	*/
	46	#if 1
	47	#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
	48	#else
	49	#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
	50	#endif
	51
acea76a2 WD	52	/*-----------------------------------------------------------------------
	53	* Base addresses -- Note these are effective addresses where the
	54	* actual resources get mapped (not physical addresses)
	55	----------------------------------------------------------------------/
	56	#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
	57	#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
8a316c9b	58	#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
acea76a2 WD	59	#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
	60	#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
	61	#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
	62	#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
	63
acea76a2	64	#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
8a316c9b	65	#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
acea76a2 WD	66
	67	/*-----------------------------------------------------------------------
	68	* Initial RAM & stack pointer (placed in internal SRAM)
	69	----------------------------------------------------------------------/
	70	#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
	71	#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
	72	#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
	73
	74	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	75	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	76
	77	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
	78	#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
	79
	80	/*-----------------------------------------------------------------------
	81	* Serial Port
	82	----------------------------------------------------------------------/
	83	#undef CONFIG_SERIAL_SOFTWARE_FIFO
	84	#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
8a316c9b	85	#define CONFIG_BAUDRATE 115200
acea76a2 WD	86
	87	#define CFG_BAUDRATE_TABLE \
	88	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
	89
	90	/*-----------------------------------------------------------------------
	91	* NVRAM/RTC
	92	*
	93	* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
	94	* The DS1743 code assumes this condition (i.e. -- it assumes the base
	95	* address for the RTC registers is:
	96	*
	97	* CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
	98	*
	99	----------------------------------------------------------------------/
	100	#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
	101	#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
	102
8a316c9b SR	103	#ifdef CFG_ENV_IS_IN_NVRAM
	104	#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
	105	#define CFG_ENV_ADDR \
	106	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
	107	#endif /* CFG_ENV_IS_IN_NVRAM */
	108
acea76a2 WD	109	/*-----------------------------------------------------------------------
	110	* FLASH related
	111	----------------------------------------------------------------------/
	112	#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
	113	#define CFG_MAX_FLASH_SECT 32 /* sectors per device */
	114
acea76a2 WD	115	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	116	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	117
8a316c9b SR	118	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	119
	120	#define CFG_FLASH_ADDR0 0x5555
	121	#define CFG_FLASH_ADDR1 0x2aaa
	122	#define CFG_FLASH_WORD_SIZE unsigned char
	123
	124	#ifdef CFG_ENV_IS_IN_FLASH
1636d1c8	125	#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
8a316c9b SR	126	#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
	127	#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
	128
	129	/* Address and size of Redundant Environment Sector */
	130	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
	131	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	132	#endif /* CFG_ENV_IS_IN_FLASH */
	133
acea76a2 WD	134	/*-----------------------------------------------------------------------
	135	* DDR SDRAM
	136	----------------------------------------------------------------------/
8423e5e3 SR	137	#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
	138	#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
	139	#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/
acea76a2 WD	140
	141	/*-----------------------------------------------------------------------
	142	* I2C
	143	----------------------------------------------------------------------/
	144	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	145	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	146	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	147	#define CFG_I2C_SLAVE 0x7F
4f92ed5f SR	148
	149	#define CFG_I2C_MULTI_EEPROMS
	150	#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
	151	#define CFG_I2C_EEPROM_ADDR_LEN 1
	152	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	153	#define CFG_EEPROM_PAGE_WRITE_BITS 3
	154	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
acea76a2	155
8a316c9b SR	156	#define CONFIG_PREBOOT "echo;" \
	157	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	158	"echo"
	159
	160	#undef CONFIG_BOOTARGS
	161
	162	#define CONFIG_EXTRA_ENV_SETTINGS \
	163	"netdev=eth0\0" \
	164	"hostname=ebony\0" \
	165	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	166	"nfsroot=${serverip}:${rootpath}\0" \
8a316c9b	167	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	168	"addip=setenv bootargs ${bootargs} " \
	169	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	170	":${hostname}:${netdev}:off panic=1\0" \
	171	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
8a316c9b	172	"flash_nfs=run nfsargs addip addtty;" \
fe126d8b	173	"bootm ${kernel_addr}\0" \
8a316c9b	174	"flash_self=run ramargs addip addtty;" \
fe126d8b WD	175	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	176	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
8a316c9b SR	177	"bootm\0" \
	178	"rootpath=/opt/eldk/ppc_4xx\0" \
	179	"bootfile=/tftpboot/ebony/uImage\0" \
	180	"kernel_addr=ff800000\0" \
	181	"ramdisk_addr=ff810000\0" \
5a753f98	182	"initrd_high=30000000\0" \
8a316c9b SR	183	"load=tftp 100000 /tftpboot/ebony/u-boot.bin\0" \
	184	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
	185	"cp.b 100000 fffc0000 40000;" \
	186	"setenv filesize;saveenv\0" \
	187	"upd=run load;run update\0" \
	188	""
	189	#define CONFIG_BOOTCOMMAND "run flash_self"
	190
	191	#if 0
	192	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	193	#else
	194	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	195	#endif
acea76a2	196
8a316c9b	197	#define CONFIG_BAUDRATE 115200
acea76a2 WD	198
	199	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	200	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	201
	202	#define CONFIG_MII 1 /* MII PHY management */
	203	#define CONFIG_PHY_ADDR 8 /* PHY address */
4a3cd9e6 SR	204	#define CONFIG_HAS_ETH1
	205	#define CONFIG_PHY1_ADDR 9 /* EMAC1 PHY address */
	206	#define CONFIG_NET_MULTI 1
	207	#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
acea76a2	208
1e25f957 SR	209	#define CONFIG_NETCONSOLE /* include NetConsole support */
1e25f957 SR	210
acea76a2	211	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
8a316c9b	212	CFG_CMD_ASKENV \| \
acea76a2	213	CFG_CMD_DATE \| \
8a316c9b SR	214	CFG_CMD_DHCP \| \
	215	CFG_CMD_DIAG \| \
	216	CFG_CMD_ELF \| \
4f92ed5f	217	CFG_CMD_EEPROM \| \
8a316c9b SR	218	CFG_CMD_I2C \| \
	219	CFG_CMD_IRQ \| \
	220	CFG_CMD_MII \| \
	221	CFG_CMD_NET \| \
	222	CFG_CMD_NFS \| \
	223	CFG_CMD_PCI \| \
	224	CFG_CMD_PING \| \
	225	CFG_CMD_REGINFO \| \
	226	CFG_CMD_SDRAM \| \
	227	CFG_CMD_SNTP )
acea76a2 WD	228
	229	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	230	#include <cmd_confdefs.h>
	231
	232	#undef CONFIG_WATCHDOG /* watchdog disabled */
	233
	234	/*
	235	* Miscellaneous configurable options
	236	*/
	237	#define CFG_LONGHELP /* undef to save memory */
	238	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	239	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	240	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	241	#else
	242	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	243	#endif
	244	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	245	#define CFG_MAXARGS 16 /* max number of command args */
	246	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	247
	248	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	249	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	250
	251	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	252	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	253
	254	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	255
4f92ed5f	256	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
8a316c9b	257	#define CONFIG_LOOPW 1 /* enable loopw command */
4f92ed5f	258	#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
8a316c9b SR	259	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	260	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
	261
acea76a2 WD	262	/*-----------------------------------------------------------------------
	263	* PCI stuff
	264	*-----------------------------------------------------------------------
	265	*/
	266	/* General PCI */
	267	#define CONFIG_PCI /* include pci support */
	268	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	269	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	270	#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
	271
	272	/* Board-specific PCI */
acea76a2 WD	273	#define CFG_PCI_TARGET_INIT /* let board init pci target */
acea76a2 WD	274
8a316c9b	275	#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
acea76a2 WD	276	#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
	277
	278	/*
	279	* For booting Linux, the board info and command line data
	280	* have to be in the first 8 MB of memory, since this is
	281	* the maximum mapped by the Linux kernel during initialization.
	282	*/
	283	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	284	/*-----------------------------------------------------------------------
	285	* Cache Configuration
	286	*/
0c8721a4	287	#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
acea76a2 WD	288	#define CFG_CACHELINE_SIZE 32 /* ... */
	289	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	290	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	291	#endif
	292
	293	/*
	294	* Internal Definitions
	295	*
	296	* Boot Flags
	297	*/
	298	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	299	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	300
	301	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	302	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	303	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	304	#endif
	305	#endif /* __CONFIG_H */