[u-boot.git] / include / configs / C29XPCIE.h

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * C29XPCIE board configuration file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_PHYS_64BIT
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO

#ifdef CONFIG_C29XPCIE
#define CONFIG_PPC_C29X
#endif

#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_SYS_TEXT_BASE		0x11000000
#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
#endif

#ifdef CONFIG_NAND
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SPL_NAND_BOOT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NAND_INIT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_COMMON_INIT_DDR
#define CONFIG_SPL_MAX_SIZE		(128 << 10)
#define CONFIG_SPL_TEXT_BASE		0xf8f81000
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
#define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
#elif defined(CONFIG_SPL_BUILD)
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TEXT_BASE		0xff800000
#define CONFIG_SPL_MAX_SIZE		8192
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
#define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
#endif
#define CONFIG_SPL_PAD_TO		0x20000
#define CONFIG_TPL_PAD_TO		0x20000
#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
#define CONFIG_SYS_TEXT_BASE		0x11001000
#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE		0xeff40000
#endif

#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
#endif

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
#endif

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif

/* High Level Configuration Options */
#define CONFIG_BOOKE			/* BOOKE */
#define CONFIG_E500			/* BOOKE e500 family */
#define CONFIG_FSL_IFC			/* Enable IFC Support */
#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
#define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */

#define CONFIG_PCI			/* Enable PCI/PCIE */
#ifdef CONFIG_PCI
#define CONFIG_PCIE1			/* PCIE controler 1 (slot 1) */
#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */

#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI

#define CONFIG_E1000

/*
 * PCI Windows
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
/* controller 1, Slot 1, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_NAME		"Slot 1"
#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull

#define CONFIG_PCI_PNP			/* do pci plug-and-play */

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#endif

#define CONFIG_FSL_LAW			/* Use common FSL init code */
#define CONFIG_TSEC_ENET
#define CONFIG_ENV_OVERWRITE

#define CONFIG_DDR_CLK_FREQ	100000000
#define CONFIG_SYS_CLK_FREQ	66666666

#define CONFIG_HWCONFIG

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */

#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */

#define CONFIG_ENABLE_36BIT_PHYS

#define CONFIG_ADDR_MAP			1
#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */

#define CONFIG_SYS_MEMTEST_START	0x00200000
#define CONFIG_SYS_MEMTEST_END		0x00400000
#define CONFIG_PANIC_HANG

/* DDR Setup */
#define CONFIG_SYS_FSL_DDR3
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM		0
#define SPD_EEPROM_ADDRESS		0x50
#define CONFIG_SYS_DDR_RAW_TIMING

/* DDR ECC Setup*/
#define CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER

#define CONFIG_SYS_SDRAM_SIZE		512
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	1

#define CONFIG_SYS_CCSRBAR		0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* Platform SRAM setting  */
#define CONFIG_SYS_PLATFORM_SRAM_BASE	0xffb00000
#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
			(0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
#define CONFIG_SYS_PLATFORM_SRAM_SIZE	(512 << 10)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_NO_FLASH
#endif

/*
 * IFC Definitions
 */
/* NOR Flash on IFC */
#define CONFIG_SYS_FLASH_BASE		0xec000000
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */

#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)

#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }
#define CONFIG_SYS_MAX_FLASH_BANKS	1

#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* in ms */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* in ms */

/* 16Bit NOR Flash - S29GL512S10TFI01 */
#define CONFIG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(64*1024*1024)
#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(4)

#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
				FTIM0_NOR_TEADC(0x5) | \
				FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
				FTIM1_NOR_TRAD_NOR(0x1A) |\
				FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
				FTIM2_NOR_TCH(0x4) | \
				FTIM2_NOR_TWPH(0x0E) | \
				FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3	0x0

/* CFI for NOR Flash */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE

/* NAND Flash on IFC */
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_BASE		0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }

#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE	(1024 * 1024)

/* 8Bit NAND Flash - K9F1G08U0B */
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_NAND \
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_OOBSIZE	0x00000280	/* 640b */
#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
				| CSOR_NAND_PGS_8K	/* Page Size = 8K */ \
				| CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
				| CSOR_NAND_PB(128))	/*128 Pages Per Block*/
#define CONFIG_SYS_NAND_FTIM0	(FTIM0_NAND_TCCST(0x01) | \
				FTIM0_NAND_TWP(0x0c)   | \
				FTIM0_NAND_TWCHT(0x08) | \
				FTIM0_NAND_TWH(0x06))
#define CONFIG_SYS_NAND_FTIM1	(FTIM1_NAND_TADLE(0x28) | \
				FTIM1_NAND_TWBE(0x1d)  | \
				FTIM1_NAND_TRR(0x08)   | \
				FTIM1_NAND_TRP(0x0c))
#define CONFIG_SYS_NAND_FTIM2	(FTIM2_NAND_TRAD(0x0c) | \
				FTIM2_NAND_TREH(0x0a) | \
				FTIM2_NAND_TWHRE(0x18))
#define CONFIG_SYS_NAND_FTIM3	(FTIM3_NAND_TWW(0x04))

#define CONFIG_SYS_NAND_DDR_LAW		11

/* Set up IFC registers for boot location NOR/NAND */
#ifdef CONFIG_NAND
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CSOR0_EXT		CONFIG_SYS_NAND_OOBSIZE
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#else
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CSOR1_EXT		CONFIG_SYS_NAND_OOBSIZE
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
#endif

/* CPLD on IFC, selected by CS2 */
#define CONFIG_SYS_CPLD_BASE		0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull \
					| CONFIG_SYS_CPLD_BASE)

#define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)
#define CONFIG_SYS_AMASK2	IFC_AMASK(64*1024)
#define CONFIG_SYS_CSOR2	0x0
/* CPLD Timing parameters for IFC CS2 */
#define CONFIG_SYS_CS2_FTIM0	(FTIM0_GPCM_TACSE(0x0e) | \
				FTIM0_GPCM_TEADC(0x0e) | \
				FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS2_FTIM1	(FTIM1_GPCM_TACO(0x0e) | \
				FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS2_FTIM2	(FTIM2_GPCM_TCS(0x0e) | \
				FTIM2_GPCM_TCH(0x8) | \
				FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS2_FTIM3	0x0

#if defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#endif

#define CONFIG_BOARD_EARLY_INIT_R

#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000
#define CONFIG_SYS_INIT_RAM_END		0x00004000

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END \
						- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(2 * 1024 * 1024)

/*
 * Config the L2 Cache as L2 SRAM
 */
#if defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_L2_SIZE		(256 << 10)
#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
#define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_SIZE	(96 << 10)
#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
#elif defined(CONFIG_NAND)
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_L2_SIZE		(256 << 10)
#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
#else
#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_L2_SIZE		(256 << 10)
#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x3000)
#define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
#endif
#endif
#endif

/* Serial Port */
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif

#define CONFIG_SERIAL_MULTI		/* Enable both serial ports */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER

/*
 * Pass open firmware flat tree
 */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_OF_STDOUT_VIA_ALIAS

/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */

#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100

/* I2C EEPROM */
/* enable read and write access to EEPROM */
#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5

#define CONFIG_CMD_I2C

/* eSPI - Enhanced SPI */
#define CONFIG_FSL_ESPI
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_SPI_FLASH_EON
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED		10000000
#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0

#ifdef CONFIG_TSEC_ENET
#define CONFIG_NET_MULTI
#define CONFIG_MII			/* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"eTSEC1"
#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"eTSEC2"

/* Default mode is RGMII mode */
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		2

#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)

#define CONFIG_ETHPRIME		"eTSEC1"

#define CONFIG_PHY_GIGE
#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#if defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS	0
#define CONFIG_ENV_SPI_CS	0
#define CONFIG_ENV_SPI_MAX_HZ	10000000
#define CONFIG_ENV_SPI_MODE	0
#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
#define CONFIG_ENV_SECT_SIZE	0x10000
#define CONFIG_ENV_SIZE		0x2000
#endif
#elif defined(CONFIG_NAND)
#define CONFIG_ENV_IS_IN_NAND
#ifdef CONFIG_TPL_BUILD
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
#else
#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_RANGE	CONFIG_ENV_SIZE
#endif
#define CONFIG_ENV_OFFSET	CONFIG_SYS_NAND_BLOCK_SIZE
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x20000
#endif

#define CONFIG_LOADS_ECHO
#define CONFIG_SYS_LOADS_BAUD_CHANGE

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO

/* Hash command with SHA acceleration supported in hardware */
#ifdef CONFIG_FSL_CAAM
#define CONFIG_CMD_HASH
#define CONFIG_SHA_HW_ACCEL
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
						/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */

/*
 * Environment Configuration
 */

#ifdef CONFIG_TSEC_ENET
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif

#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_BOOTFILE		"uImage"
#define CONFIG_UBOOTPATH	u-boot.bin/* U-Boot image on TFTP server */

/* default location for tftp and bootm */
#define CONFIG_LOADADDR		1000000

#define CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */

#define CONFIG_BAUDRATE		115200

#define CONFIG_DEF_HWCONFIG	fsl_ddr:ecc=on

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"	\
	"netdev=eth0\0"						\
	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
	"loadaddr=1000000\0"				\
	"consoledev=ttyS0\0"				\
	"ramdiskaddr=2000000\0"				\
	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
	"fdtaddr=c00000\0"				\
	"fdtfile=name/of/device-tree.dtb\0"			\
	"othbootargs=ramdisk_size=600000\0"		\

#define CONFIG_RAMBOOTCOMMAND			\
	"setenv bootargs root=/dev/ram rw "	\
	"console=$consoledev,$baudrate $othbootargs; "	\
	"tftp $ramdiskaddr $ramdiskfile;"	\
	"tftp $loadaddr $bootfile;"		\
	"tftp $fdtaddr $fdtfile;"		\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
a8d9758d MH	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
3aab0cd8	4	* SPDX-License-Identifier: GPL-2.0+
a8d9758d MH	5	*/
	6
	7	/*
	8	* C29XPCIE board configuration file
	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	#define CONFIG_PHYS_64BIT
9a7eeb9c CL	15	#define CONFIG_SYS_GENERIC_BOARD
9a7eeb9c CL	16	#define CONFIG_DISPLAY_BOARDINFO
a8d9758d MH	17
	18	#ifdef CONFIG_C29XPCIE
	19	#define CONFIG_PPC_C29X
	20	#endif
	21
	22	#ifdef CONFIG_SPIFLASH
	23	#define CONFIG_RAMBOOT_SPIFLASH
	24	#define CONFIG_SYS_TEXT_BASE 0x11000000
e222b1f3	25	#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
a8d9758d MH	26	#endif
a8d9758d MH	27
eb6b458c	28	#ifdef CONFIG_NAND
eb6b458c PL	29	#ifdef CONFIG_TPL_BUILD
	30	#define CONFIG_SPL_NAND_BOOT
	31	#define CONFIG_SPL_FLUSH_IMAGE
	32	#define CONFIG_SPL_ENV_SUPPORT
	33	#define CONFIG_SPL_NAND_INIT
	34	#define CONFIG_SPL_SERIAL_SUPPORT
	35	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	36	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	37	#define CONFIG_SPL_I2C_SUPPORT
	38	#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
	39	#define CONFIG_SPL_NAND_SUPPORT
	40	#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
	41	#define CONFIG_SPL_COMMON_INIT_DDR
	42	#define CONFIG_SPL_MAX_SIZE (128 << 10)
	43	#define CONFIG_SPL_TEXT_BASE 0xf8f81000
	44	#define CONFIG_SYS_MPC85XX_NO_RESETVEC
e222b1f3	45	#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
eb6b458c PL	46	#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
	47	#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
	48	#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
	49	#elif defined(CONFIG_SPL_BUILD)
	50	#define CONFIG_SPL_INIT_MINIMAL
	51	#define CONFIG_SPL_SERIAL_SUPPORT
	52	#define CONFIG_SPL_NAND_SUPPORT
	53	#define CONFIG_SPL_NAND_MINIMAL
	54	#define CONFIG_SPL_FLUSH_IMAGE
	55	#define CONFIG_SPL_TEXT_BASE 0xff800000
	56	#define CONFIG_SPL_MAX_SIZE 8192
	57	#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
	58	#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
	59	#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
	60	#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
	61	#endif
	62	#define CONFIG_SPL_PAD_TO 0x20000
	63	#define CONFIG_TPL_PAD_TO 0x20000
	64	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
	65	#define CONFIG_SYS_TEXT_BASE 0x11001000
	66	#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
	67	#endif
	68
a8d9758d	69	#ifndef CONFIG_SYS_TEXT_BASE
e222b1f3	70	#define CONFIG_SYS_TEXT_BASE 0xeff40000
a8d9758d MH	71	#endif
	72
	73	#ifndef CONFIG_RESET_VECTOR_ADDRESS
	74	#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
	75	#endif
	76
eb6b458c PL	77	#ifdef CONFIG_SPL_BUILD
	78	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	79	#else
	80	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	81	#endif
	82
	83	#ifdef CONFIG_SPL_BUILD
	84	#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
a8d9758d MH	85	#endif
	86
	87	/* High Level Configuration Options */
	88	#define CONFIG_BOOKE /* BOOKE */
	89	#define CONFIG_E500 /* BOOKE e500 family */
a8d9758d	90	#define CONFIG_FSL_IFC /* Enable IFC Support */
737537ef	91	#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
a8d9758d MH	92	#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
	93
	94	#define CONFIG_PCI /* Enable PCI/PCIE */
	95	#ifdef CONFIG_PCI
	96	#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
	97	#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
	98	#define CONFIG_PCI_INDIRECT_BRIDGE
	99	#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
	100	#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
	101
	102	#define CONFIG_CMD_NET
	103	#define CONFIG_CMD_PCI
	104
	105	#define CONFIG_E1000
	106
	107	/*
	108	* PCI Windows
	109	* Memory space is mapped 1-1, but I/O space must start from 0.
	110	*/
	111	/* controller 1, Slot 1, tgtid 1, Base address a000 */
	112	#define CONFIG_SYS_PCIE1_NAME "Slot 1"
	113	#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
	114	#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
	115	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
	116	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
	117	#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
	118	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
	119	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
	120	#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
	121
	122	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	123
	124	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	125	#define CONFIG_DOS_PARTITION
	126	#endif
	127
	128	#define CONFIG_FSL_LAW /* Use common FSL init code */
	129	#define CONFIG_TSEC_ENET
	130	#define CONFIG_ENV_OVERWRITE
	131
	132	#define CONFIG_DDR_CLK_FREQ 100000000
	133	#define CONFIG_SYS_CLK_FREQ 66666666
	134
	135	#define CONFIG_HWCONFIG
	136
	137	/*
	138	* These can be toggled for performance analysis, otherwise use default.
	139	*/
	140	#define CONFIG_L2_CACHE /* toggle L2 cache */
	141	#define CONFIG_BTB /* toggle branch predition */
	142
	143	#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
	144
	145	#define CONFIG_ENABLE_36BIT_PHYS
	146
	147	#define CONFIG_ADDR_MAP 1
	148	#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
	149
	150	#define CONFIG_SYS_MEMTEST_START 0x00200000
	151	#define CONFIG_SYS_MEMTEST_END 0x00400000
	152	#define CONFIG_PANIC_HANG
	153
	154	/* DDR Setup */
5614e71b	155	#define CONFIG_SYS_FSL_DDR3
a8d9758d MH	156	#define CONFIG_DDR_SPD
	157	#define CONFIG_SYS_SPD_BUS_NUM 0
	158	#define SPD_EEPROM_ADDRESS 0x50
	159	#define CONFIG_SYS_DDR_RAW_TIMING
	160
	161	/* DDR ECC Setup*/
	162	#define CONFIG_DDR_ECC
	163	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	164	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	165
	166	#define CONFIG_SYS_SDRAM_SIZE 512
	167	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	168	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	169
	170	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	171	#define CONFIG_CHIP_SELECTS_PER_CTRL 1
	172
	173	#define CONFIG_SYS_CCSRBAR 0xffe00000
	174	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
	175
	176	/* Platform SRAM setting */
	177	#define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
	178	#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
	179	(0xf00000000ull \| CONFIG_SYS_PLATFORM_SRAM_BASE)
	180	#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
	181
eb6b458c PL	182	#ifdef CONFIG_SPL_BUILD
	183	#define CONFIG_SYS_NO_FLASH
	184	#endif
	185
a8d9758d MH	186	/*
	187	* IFC Definitions
	188	*/
	189	/* NOR Flash on IFC */
	190	#define CONFIG_SYS_FLASH_BASE 0xec000000
	191	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
	192
	193	#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_FLASH_BASE)
	194
	195	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
	196	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	197
	198	#define CONFIG_SYS_FLASH_QUIET_TEST
	199	#define CONFIG_FLASH_SHOW_PROGRESS 45
	200	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */
	201	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */
	202
	203	/* 16Bit NOR Flash - S29GL512S10TFI01 */
	204	#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	205	CSPR_PORT_SIZE_16 \| \
	206	CSPR_MSEL_NOR \| \
	207	CSPR_V)
	208	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(6410241024)
	209	#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
ac2785c6	210
a8d9758d MH	211	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	212	FTIM0_NOR_TEADC(0x5) \| \
	213	FTIM0_NOR_TEAHC(0x5))
ac2785c6 PL	214	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	215	FTIM1_NOR_TRAD_NOR(0x1A) \|\
	216	FTIM1_NOR_TSEQRAD_NOR(0x13))
a8d9758d MH	217	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
a8d9758d MH	218	FTIM2_NOR_TCH(0x4) \| \
ac2785c6	219	FTIM2_NOR_TWPH(0x0E) \| \
a8d9758d MH	220	FTIM2_NOR_TWP(0x1c))
	221	#define CONFIG_SYS_NOR_FTIM3 0x0
	222
	223	/* CFI for NOR Flash */
	224	#define CONFIG_FLASH_CFI_DRIVER
	225	#define CONFIG_SYS_FLASH_CFI
	226	#define CONFIG_SYS_FLASH_EMPTY_INFO
	227	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	228
	229	/* NAND Flash on IFC */
	230	#define CONFIG_NAND_FSL_IFC
	231	#define CONFIG_SYS_NAND_BASE 0xff800000
	232	#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
	233
	234	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	235
	236	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	237	#define CONFIG_MTD_NAND_VERIFY_WRITE
	238	#define CONFIG_CMD_NAND
eb6b458c	239	#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
a8d9758d MH	240
	241	/* 8Bit NAND Flash - K9F1G08U0B */
	242	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	243	\| CSPR_PORT_SIZE_8 \
	244	\| CSPR_MSEL_NAND \
	245	\| CSPR_V)
	246	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
affd520f	247	#define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */
a8d9758d MH	248	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	249	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	250	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
affd520f PK	251	\| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
	252	\| CSOR_NAND_PGS_8K /* Page Size = 8K */ \
	253	\| CSOR_NAND_SPRZ_CSOR_EXT /oob in csor_ext/\
	254	\| CSOR_NAND_PB(128)) /128 Pages Per Block/
a8d9758d MH	255	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) \| \
	256	FTIM0_NAND_TWP(0x0c) \| \
	257	FTIM0_NAND_TWCHT(0x08) \| \
	258	FTIM0_NAND_TWH(0x06))
	259	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) \| \
	260	FTIM1_NAND_TWBE(0x1d) \| \
	261	FTIM1_NAND_TRR(0x08) \| \
	262	FTIM1_NAND_TRP(0x0c))
	263	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) \| \
	264	FTIM2_NAND_TREH(0x0a) \| \
	265	FTIM2_NAND_TWHRE(0x18))
	266	#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
	267
	268	#define CONFIG_SYS_NAND_DDR_LAW 11
	269
	270	/* Set up IFC registers for boot location NOR/NAND */
eb6b458c PL	271	#ifdef CONFIG_NAND
	272	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	273	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	274	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	275	#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
	276	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	277	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	278	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	279	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	280	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
	281	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	282	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	283	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	284	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	285	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	286	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	287	#else
a8d9758d MH	288	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
	289	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	290	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	291	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	292	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	293	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	294	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	295	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
	296	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
	297	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
affd520f	298	#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
a8d9758d MH	299	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
	300	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
	301	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
	302	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
eb6b458c	303	#endif
a8d9758d MH	304
	305	/* CPLD on IFC, selected by CS2 */
	306	#define CONFIG_SYS_CPLD_BASE 0xffdf0000
	307	#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
	308	\| CONFIG_SYS_CPLD_BASE)
	309
	310	#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
	311	\| CSPR_PORT_SIZE_8 \
	312	\| CSPR_MSEL_GPCM \
	313	\| CSPR_V)
	314	#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
	315	#define CONFIG_SYS_CSOR2 0x0
	316	/* CPLD Timing parameters for IFC CS2 */
	317	#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
	318	FTIM0_GPCM_TEADC(0x0e) \| \
	319	FTIM0_GPCM_TEAHC(0x0e))
	320	#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) \| \
	321	FTIM1_GPCM_TRAD(0x1f))
	322	#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) \| \
de519163	323	FTIM2_GPCM_TCH(0x8) \| \
a8d9758d MH	324	FTIM2_GPCM_TWP(0x1f))
	325	#define CONFIG_SYS_CS2_FTIM3 0x0
	326
	327	#if defined(CONFIG_RAMBOOT_SPIFLASH)
	328	#define CONFIG_SYS_RAMBOOT
	329	#define CONFIG_SYS_EXTRA_ENV_RELOC
	330	#endif
	331
	332	#define CONFIG_BOARD_EARLY_INIT_R
	333
	334	#define CONFIG_SYS_INIT_RAM_LOCK
	335	#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
	336	#define CONFIG_SYS_INIT_RAM_END 0x00004000
	337
	338	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
	339	- GENERATED_GBL_DATA_SIZE)
	340	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	341
9307cbab	342	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
eb6b458c PL	343	#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
	344
	345	/*
	346	* Config the L2 Cache as L2 SRAM
	347	*/
	348	#if defined(CONFIG_SPL_BUILD)
	349	#if defined(CONFIG_SDCARD) \|\| defined(CONFIG_SPIFLASH)
	350	#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
	351	#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
	352	#define CONFIG_SYS_L2_SIZE (256 << 10)
	353	#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
	354	#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
	355	#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
	356	#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
	357	#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
	358	#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
	359	#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
	360	#elif defined(CONFIG_NAND)
	361	#ifdef CONFIG_TPL_BUILD
	362	#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
	363	#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
	364	#define CONFIG_SYS_L2_SIZE (256 << 10)
	365	#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
	366	#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
	367	#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
	368	#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
	369	#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
	370	#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
	371	#else
	372	#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
	373	#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
	374	#define CONFIG_SYS_L2_SIZE (256 << 10)
	375	#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
	376	#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
	377	#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
	378	#endif
	379	#endif
	380	#endif
a8d9758d MH	381
	382	/* Serial Port */
	383	#define CONFIG_CONS_INDEX 1
	384	#define CONFIG_SYS_NS16550
	385	#define CONFIG_SYS_NS16550_SERIAL
	386	#define CONFIG_SYS_NS16550_REG_SIZE 1
	387	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	388
eb6b458c PL	389	#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
	390	#define CONFIG_NS16550_MIN_FUNCTIONS
	391	#endif
	392
a8d9758d MH	393	#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
	394	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	395
	396	#define CONFIG_SYS_BAUDRATE_TABLE \
	397	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	398
	399	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
	400	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
	401
	402	/* Use the HUSH parser */
	403	#define CONFIG_SYS_HUSH_PARSER
	404
	405	/*
	406	* Pass open firmware flat tree
	407	*/
	408	#define CONFIG_OF_LIBFDT
	409	#define CONFIG_OF_BOARD_SETUP
	410	#define CONFIG_OF_STDOUT_VIA_ALIAS
	411
	412	/* new uImage format support */
	413	#define CONFIG_FIT
	414	#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
	415
	416	#define CONFIG_SYS_I2C
	417	#define CONFIG_SYS_I2C_FSL
	418	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	419	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	420	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	421	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	422	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	423	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
	424
	425	/* I2C EEPROM */
	426	/* enable read and write access to EEPROM */
	427	#define CONFIG_CMD_EEPROM
	428	#define CONFIG_SYS_I2C_MULTI_EEPROMS
	429	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	430	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	431	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	432
	433	#define CONFIG_CMD_I2C
	434
	435	/* eSPI - Enhanced SPI */
	436	#define CONFIG_FSL_ESPI
	437	#define CONFIG_SPI_FLASH
	438	#define CONFIG_SPI_FLASH_SPANSION
	439	#define CONFIG_SPI_FLASH_EON
	440	#define CONFIG_CMD_SF
	441	#define CONFIG_SF_DEFAULT_SPEED 10000000
	442	#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
	443
	444	#ifdef CONFIG_TSEC_ENET
	445	#define CONFIG_NET_MULTI
	446	#define CONFIG_MII /* MII PHY management */
	447	#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
	448	#define CONFIG_TSEC1 1
	449	#define CONFIG_TSEC1_NAME "eTSEC1"
	450	#define CONFIG_TSEC2 1
	451	#define CONFIG_TSEC2_NAME "eTSEC2"
	452
	453	/* Default mode is RGMII mode */
	454	#define TSEC1_PHY_ADDR 0
	455	#define TSEC2_PHY_ADDR 2
	456
457	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
458	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
459
460	#define CONFIG_ETHPRIME "eTSEC1"
461
462	#define CONFIG_PHY_GIGE
463	#endif /* CONFIG_TSEC_ENET */
464
465	/*
466	* Environment
467	*/
468	#if defined(CONFIG_SYS_RAMBOOT)
469	#if defined(CONFIG_RAMBOOT_SPIFLASH)
470	#define CONFIG_ENV_IS_IN_SPI_FLASH
471	#define CONFIG_ENV_SPI_BUS 0
472	#define CONFIG_ENV_SPI_CS 0
473	#define CONFIG_ENV_SPI_MAX_HZ 10000000
474	#define CONFIG_ENV_SPI_MODE 0
475	#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
476	#define CONFIG_ENV_SECT_SIZE 0x10000
477	#define CONFIG_ENV_SIZE 0x2000
478	#endif
eb6b458c PL	479	#elif defined(CONFIG_NAND)
	480	#define CONFIG_ENV_IS_IN_NAND
	481	#ifdef CONFIG_TPL_BUILD
	482	#define CONFIG_ENV_SIZE 0x2000
	483	#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
	484	#else
	485	#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
	486	#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
	487	#endif
	488	#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE
a8d9758d MH	489	#else
a8d9758d MH	490	#define CONFIG_ENV_IS_IN_FLASH
a8d9758d	491	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
a8d9758d MH	492	#define CONFIG_ENV_SIZE 0x2000
	493	#define CONFIG_ENV_SECT_SIZE 0x20000
	494	#endif
	495
	496	#define CONFIG_LOADS_ECHO
	497	#define CONFIG_SYS_LOADS_BAUD_CHANGE
	498
	499	/*
	500	* Command line configuration.
	501	*/
	502	#include <config_cmd_default.h>
	503
	504	#define CONFIG_CMD_ERRATA
	505	#define CONFIG_CMD_ELF
	506	#define CONFIG_CMD_IRQ
	507	#define CONFIG_CMD_MII
	508	#define CONFIG_CMD_PING
	509	#define CONFIG_CMD_SETEXPR
	510	#define CONFIG_CMD_REGINFO
	511
737537ef RG	512	/* Hash command with SHA acceleration supported in hardware */
	513	#ifdef CONFIG_FSL_CAAM
	514	#define CONFIG_CMD_HASH
	515	#define CONFIG_SHA_HW_ACCEL
	516	#endif
	517
a8d9758d MH	518	/*
	519	* Miscellaneous configurable options
	520	*/
	521	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	522	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
	523	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
	524	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
a8d9758d MH	525
	526	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	527	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	528	/* Print Buffer Size */
	529	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	530	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
a8d9758d MH	531
	532	/*
	533	* For booting Linux, the board info and command line data
	534	* have to be in the first 64 MB of memory, since this is
	535	* the maximum mapped by the Linux kernel during initialization.
	536	*/
	537	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
	538	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	539
	540	/*
	541	* Environment Configuration
	542	*/
	543
	544	#ifdef CONFIG_TSEC_ENET
	545	#define CONFIG_HAS_ETH0
	546	#define CONFIG_HAS_ETH1
	547	#endif
	548
	549	#define CONFIG_ROOTPATH "/opt/nfsroot"
	550	#define CONFIG_BOOTFILE "uImage"
	551	#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
	552
	553	/* default location for tftp and bootm */
	554	#define CONFIG_LOADADDR 1000000
	555
	556	#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
	557
	558	#define CONFIG_BAUDRATE 115200
	559
9c25ee6d PL	560	#define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
9c25ee6d PL	561
a8d9758d MH	562	#define CONFIG_EXTRA_ENV_SETTINGS \
	563	"hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
	564	"netdev=eth0\0" \
	565	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
	566	"loadaddr=1000000\0" \
	567	"consoledev=ttyS0\0" \
	568	"ramdiskaddr=2000000\0" \
	569	"ramdiskfile=rootfs.ext2.gz.uboot\0" \
	570	"fdtaddr=c00000\0" \
	571	"fdtfile=name/of/device-tree.dtb\0" \
	572	"othbootargs=ramdisk_size=600000\0" \
	573
	574	#define CONFIG_RAMBOOTCOMMAND \
	575	"setenv bootargs root=/dev/ram rw " \
	576	"console=$consoledev,$baudrate $othbootargs; " \
	577	"tftp $ramdiskaddr $ramdiskfile;" \
	578	"tftp $loadaddr $bootfile;" \
	579	"tftp $fdtaddr $fdtfile;" \
	580	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	581
	582	#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
	583
	584	#endif /* __CONFIG_H */