[u-boot.git] / drivers / mmc / fsl_esdhc.c

/*
 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
 * Andy Fleming
 *
 * Based vaguely on the pxa mmc code:
 * (C) Copyright 2003
 * Kyle Harris, Nexus Technologies, Inc. [email protected]
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <common.h>
#include <command.h>
#include <hwconfig.h>
#include <mmc.h>
#include <part.h>
#include <malloc.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <fdt_support.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

struct fsl_esdhc {
	uint    dsaddr;		/* SDMA system address register */
	uint    blkattr;	/* Block attributes register */
	uint    cmdarg;		/* Command argument register */
	uint    xfertyp;	/* Transfer type register */
	uint    cmdrsp0;	/* Command response 0 register */
	uint    cmdrsp1;	/* Command response 1 register */
	uint    cmdrsp2;	/* Command response 2 register */
	uint    cmdrsp3;	/* Command response 3 register */
	uint    datport;	/* Buffer data port register */
	uint    prsstat;	/* Present state register */
	uint    proctl;		/* Protocol control register */
	uint    sysctl;		/* System Control Register */
	uint    irqstat;	/* Interrupt status register */
	uint    irqstaten;	/* Interrupt status enable register */
	uint    irqsigen;	/* Interrupt signal enable register */
	uint    autoc12err;	/* Auto CMD error status register */
	uint    hostcapblt;	/* Host controller capabilities register */
	uint    wml;		/* Watermark level register */
	uint    mixctrl;	/* For USDHC */
	char    reserved1[4];	/* reserved */
	uint    fevt;		/* Force event register */
	uint    admaes;		/* ADMA error status register */
	uint    adsaddr;	/* ADMA system address register */
	char    reserved2[160];	/* reserved */
	uint    hostver;	/* Host controller version register */
	char    reserved3[4];	/* reserved */
	uint    dmaerraddr;	/* DMA error address register */
	char    reserved4[4];	/* reserved */
	uint    dmaerrattr;	/* DMA error attribute register */
	char    reserved5[4];	/* reserved */
	uint    hostcapblt2;	/* Host controller capabilities register 2 */
	char    reserved6[8];	/* reserved */
	uint    tcr;		/* Tuning control register */
	char    reserved7[28];	/* reserved */
	uint    sddirctl;	/* SD direction control register */
	char    reserved8[712];	/* reserved */
	uint    scr;		/* eSDHC control register */
};

/* Return the XFERTYP flags for a given command and data packet */
static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
{
	uint xfertyp = 0;

	if (data) {
		xfertyp |= XFERTYP_DPSEL;
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
		xfertyp |= XFERTYP_DMAEN;
#endif
		if (data->blocks > 1) {
			xfertyp |= XFERTYP_MSBSEL;
			xfertyp |= XFERTYP_BCEN;
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
			xfertyp |= XFERTYP_AC12EN;
#endif
		}

		if (data->flags & MMC_DATA_READ)
			xfertyp |= XFERTYP_DTDSEL;
	}

	if (cmd->resp_type & MMC_RSP_CRC)
		xfertyp |= XFERTYP_CCCEN;
	if (cmd->resp_type & MMC_RSP_OPCODE)
		xfertyp |= XFERTYP_CICEN;
	if (cmd->resp_type & MMC_RSP_136)
		xfertyp |= XFERTYP_RSPTYP_136;
	else if (cmd->resp_type & MMC_RSP_BUSY)
		xfertyp |= XFERTYP_RSPTYP_48_BUSY;
	else if (cmd->resp_type & MMC_RSP_PRESENT)
		xfertyp |= XFERTYP_RSPTYP_48;

#if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS)
	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
		xfertyp |= XFERTYP_CMDTYP_ABORT;
#endif
	return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
}

#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
/*
 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
 */
static void
esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
{
	struct fsl_esdhc_cfg *cfg = mmc->priv;
	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
	uint blocks;
	char *buffer;
	uint databuf;
	uint size;
	uint irqstat;
	uint timeout;

	if (data->flags & MMC_DATA_READ) {
		blocks = data->blocks;
		buffer = data->dest;
		while (blocks) {
			timeout = PIO_TIMEOUT;
			size = data->blocksize;
			irqstat = esdhc_read32(&regs->irqstat);
			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
				&& --timeout);
			if (timeout <= 0) {
				printf("\nData Read Failed in PIO Mode.");
				return;
			}
			while (size && (!(irqstat & IRQSTAT_TC))) {
				udelay(100); /* Wait before last byte transfer complete */
				irqstat = esdhc_read32(&regs->irqstat);
				databuf = in_le32(&regs->datport);
				*((uint *)buffer) = databuf;
				buffer += 4;
				size -= 4;
			}
			blocks--;
		}
	} else {
		blocks = data->blocks;
		buffer = (char *)data->src;
		while (blocks) {
			timeout = PIO_TIMEOUT;
			size = data->blocksize;
			irqstat = esdhc_read32(&regs->irqstat);
			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
				&& --timeout);
			if (timeout <= 0) {
				printf("\nData Write Failed in PIO Mode.");
				return;
			}
			while (size && (!(irqstat & IRQSTAT_TC))) {
				udelay(100); /* Wait before last byte transfer complete */
				databuf = *((uint *)buffer);
				buffer += 4;
				size -= 4;
				irqstat = esdhc_read32(&regs->irqstat);
				out_le32(&regs->datport, databuf);
			}
			blocks--;
		}
	}
}
#endif

static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
{
	int timeout;
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
	uint wml_value;

	wml_value = data->blocksize/4;

	if (data->flags & MMC_DATA_READ) {
		if (wml_value > WML_RD_WML_MAX)
			wml_value = WML_RD_WML_MAX_VAL;

		esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
		esdhc_write32(&regs->dsaddr, (u32)data->dest);
	} else {
		flush_dcache_range((ulong)data->src,
				   (ulong)data->src+data->blocks
					 *data->blocksize);

		if (wml_value > WML_WR_WML_MAX)
			wml_value = WML_WR_WML_MAX_VAL;
		if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
			printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
			return TIMEOUT;
		}

		esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
					wml_value << 16);
		esdhc_write32(&regs->dsaddr, (u32)data->src);
	}
#else	/* CONFIG_SYS_FSL_ESDHC_USE_PIO */
	if (!(data->flags & MMC_DATA_READ)) {
		if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
			printf("\nThe SD card is locked. "
				"Can not write to a locked card.\n\n");
			return TIMEOUT;
		}
		esdhc_write32(&regs->dsaddr, (u32)data->src);
	} else
		esdhc_write32(&regs->dsaddr, (u32)data->dest);
#endif	/* CONFIG_SYS_FSL_ESDHC_USE_PIO */

	esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);

	/* Calculate the timeout period for data transactions */
	/*
	 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
	 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
	 *  So, Number of SD Clock cycles for 0.25sec should be minimum
	 *		(SD Clock/sec * 0.25 sec) SD Clock cycles
	 *		= (mmc->tran_speed * 1/4) SD Clock cycles
	 * As 1) >=  2)
	 * => (2^(timeout+13)) >= mmc->tran_speed * 1/4
	 * Taking log2 both the sides
	 * => timeout + 13 >= log2(mmc->tran_speed/4)
	 * Rounding up to next power of 2
	 * => timeout + 13 = log2(mmc->tran_speed/4) + 1
	 * => timeout + 13 = fls(mmc->tran_speed/4)
	 */
	timeout = fls(mmc->tran_speed/4);
	timeout -= 13;

	if (timeout > 14)
		timeout = 14;

	if (timeout < 0)
		timeout = 0;

#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
	if ((timeout == 4) || (timeout == 8) || (timeout == 12))
		timeout++;
#endif

	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);

	return 0;
}

static void check_and_invalidate_dcache_range
	(struct mmc_cmd *cmd,
	 struct mmc_data *data) {
	unsigned start = (unsigned)data->dest ;
	unsigned size = roundup(ARCH_DMA_MINALIGN,
				data->blocks*data->blocksize);
	unsigned end = start+size ;
	invalidate_dcache_range(start, end);
}
/*
 * Sends a command out on the bus.  Takes the mmc pointer,
 * a command pointer, and an optional data pointer.
 */
static int
esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
	uint	xfertyp;
	uint	irqstat;
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;

#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
		return 0;
#endif

	esdhc_write32(&regs->irqstat, -1);

	sync();

	/* Wait for the bus to be idle */
	while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
			(esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
		;

	while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
		;

	/* Wait at least 8 SD clock cycles before the next command */
	/*
	 * Note: This is way more than 8 cycles, but 1ms seems to
	 * resolve timing issues with some cards
	 */
	udelay(1000);

	/* Set up for a data transfer if we have one */
	if (data) {
		int err;

		err = esdhc_setup_data(mmc, data);
		if(err)
			return err;
	}

	/* Figure out the transfer arguments */
	xfertyp = esdhc_xfertyp(cmd, data);

	/* Mask all irqs */
	esdhc_write32(&regs->irqsigen, 0);

	/* Send the command */
	esdhc_write32(&regs->cmdarg, cmd->cmdarg);
#if defined(CONFIG_FSL_USDHC)
	esdhc_write32(&regs->mixctrl,
	(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
	esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
#else
	esdhc_write32(&regs->xfertyp, xfertyp);
#endif

	/* Wait for the command to complete */
	while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
		;

	irqstat = esdhc_read32(&regs->irqstat);

	/* Reset CMD and DATA portions on error */
	if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) {
		esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
			      SYSCTL_RSTC);
		while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
			;

		if (data) {
			esdhc_write32(&regs->sysctl,
				      esdhc_read32(&regs->sysctl) |
				      SYSCTL_RSTD);
			while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
				;
		}
	}

	if (irqstat & CMD_ERR)
		return COMM_ERR;

	if (irqstat & IRQSTAT_CTOE)
		return TIMEOUT;

	/* Workaround for ESDHC errata ENGcm03648 */
	if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
		int timeout = 2500;

		/* Poll on DATA0 line for cmd with busy signal for 250 ms */
		while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
					PRSSTAT_DAT0)) {
			udelay(100);
			timeout--;
		}

		if (timeout <= 0) {
			printf("Timeout waiting for DAT0 to go high!\n");
			return TIMEOUT;
		}
	}

	/* Copy the response to the response buffer */
	if (cmd->resp_type & MMC_RSP_136) {
		u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;

		cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
		cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
		cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
		cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
		cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
		cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
		cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
		cmd->response[3] = (cmdrsp0 << 8);
	} else
		cmd->response[0] = esdhc_read32(&regs->cmdrsp0);

	/* Wait until all of the blocks are transferred */
	if (data) {
#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
		esdhc_pio_read_write(mmc, data);
#else
		do {
			irqstat = esdhc_read32(&regs->irqstat);

			if (irqstat & IRQSTAT_DTOE)
				return TIMEOUT;

			if (irqstat & DATA_ERR)
				return COMM_ERR;
		} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
#endif
		if (data->flags & MMC_DATA_READ)
			check_and_invalidate_dcache_range(cmd, data);
	}

	esdhc_write32(&regs->irqstat, -1);

	return 0;
}

static void set_sysctl(struct mmc *mmc, uint clock)
{
	int div, pre_div;
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
	int sdhc_clk = cfg->sdhc_clk;
	uint clk;

	if (clock < mmc->f_min)
		clock = mmc->f_min;

	if (sdhc_clk / 16 > clock) {
		for (pre_div = 2; pre_div < 256; pre_div *= 2)
			if ((sdhc_clk / pre_div) <= (clock * 16))
				break;
	} else
		pre_div = 2;

	for (div = 1; div <= 16; div++)
		if ((sdhc_clk / (div * pre_div)) <= clock)
			break;

	pre_div >>= 1;
	div -= 1;

	clk = (pre_div << 8) | (div << 4);

	esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);

	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);

	udelay(10000);

	clk = SYSCTL_PEREN | SYSCTL_CKEN;

	esdhc_setbits32(&regs->sysctl, clk);
}

static void esdhc_set_ios(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;

	/* Set the clock speed */
	set_sysctl(mmc, mmc->clock);

	/* Set the bus width */
	esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);

	if (mmc->bus_width == 4)
		esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
	else if (mmc->bus_width == 8)
		esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);

}

static int esdhc_init(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
	int timeout = 1000;

	/* Reset the entire host controller */
	esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);

	/* Wait until the controller is available */
	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
		udelay(1000);

#ifndef ARCH_MXC
	/* Enable cache snooping */
	esdhc_write32(&regs->scr, 0x00000040);
#endif

	esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);

	/* Set the initial clock speed */
	mmc_set_clock(mmc, 400000);

	/* Disable the BRR and BWR bits in IRQSTAT */
	esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);

	/* Put the PROCTL reg back to the default */
	esdhc_write32(&regs->proctl, PROCTL_INIT);

	/* Set timout to the maximum value */
	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);

	return 0;
}

static int esdhc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
	int timeout = 1000;

#ifdef CONFIG_ESDHC_DETECT_QUIRK
	if (CONFIG_ESDHC_DETECT_QUIRK)
		return 1;
#endif
	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
		udelay(1000);

	return timeout > 0;
}

static void esdhc_reset(struct fsl_esdhc *regs)
{
	unsigned long timeout = 100; /* wait max 100 ms */

	/* reset the controller */
	esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);

	/* hardware clears the bit when it is done */
	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
		udelay(1000);
	if (!timeout)
		printf("MMC/SD: Reset never completed.\n");
}

static const struct mmc_ops esdhc_ops = {
	.send_cmd	= esdhc_send_cmd,
	.set_ios	= esdhc_set_ios,
	.init		= esdhc_init,
	.getcd		= esdhc_getcd,
};

int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
{
	struct fsl_esdhc *regs;
	struct mmc *mmc;
	u32 caps, voltage_caps;

	if (!cfg)
		return -1;

	mmc = malloc(sizeof(struct mmc));
	if (!mmc)
		return -ENOMEM;

	memset(mmc, 0, sizeof(struct mmc));
	sprintf(mmc->name, "FSL_SDHC");
	regs = (struct fsl_esdhc *)cfg->esdhc_base;

	/* First reset the eSDHC controller */
	esdhc_reset(regs);

	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
				| SYSCTL_IPGEN | SYSCTL_CKEN);

	mmc->priv = cfg;
	mmc->ops = &esdhc_ops;
	voltage_caps = 0;
	caps = regs->hostcapblt;

#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
	caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
			ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
#endif

/* T4240 host controller capabilities register should have VS33 bit */
#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
	caps = caps | ESDHC_HOSTCAPBLT_VS33;
#endif

	if (caps & ESDHC_HOSTCAPBLT_VS18)
		voltage_caps |= MMC_VDD_165_195;
	if (caps & ESDHC_HOSTCAPBLT_VS30)
		voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
	if (caps & ESDHC_HOSTCAPBLT_VS33)
		voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;

#ifdef CONFIG_SYS_SD_VOLTAGE
	mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
#else
	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
#endif
	if ((mmc->voltages & voltage_caps) == 0) {
		printf("voltage not supported by controller\n");
		return -1;
	}

	mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;

	if (cfg->max_bus_width > 0) {
		if (cfg->max_bus_width < 8)
			mmc->host_caps &= ~MMC_MODE_8BIT;
		if (cfg->max_bus_width < 4)
			mmc->host_caps &= ~MMC_MODE_4BIT;
	}

	if (caps & ESDHC_HOSTCAPBLT_HSS)
		mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;

#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
	if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
		mmc->host_caps &= ~MMC_MODE_8BIT;
#endif

	mmc->f_min = 400000;
	mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000);

	mmc->b_max = 0;
	mmc_register(mmc);

	return 0;
}

int fsl_esdhc_mmc_init(bd_t *bis)
{
	struct fsl_esdhc_cfg *cfg;

	cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
	cfg->sdhc_clk = gd->arch.sdhc_clk;
	return fsl_esdhc_initialize(bis, cfg);
}

#ifdef CONFIG_OF_LIBFDT
void fdt_fixup_esdhc(void *blob, bd_t *bd)
{
	const char *compat = "fsl,esdhc";

#ifdef CONFIG_FSL_ESDHC_PIN_MUX
	if (!hwconfig("esdhc")) {
		do_fixup_by_compat(blob, compat, "status", "disabled",
				8 + 1, 1);
		return;
	}
#endif

	do_fixup_by_compat_u32(blob, compat, "clock-frequency",
			       gd->arch.sdhc_clk, 1);

	do_fixup_by_compat(blob, compat, "status", "okay",
			   4 + 1, 1);
}
#endif
Commit	Line	Data
50586ef2	1	/*
d621da00	2	* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
50586ef2 AF	3	* Andy Fleming
	4	*
	5	* Based vaguely on the pxa mmc code:
	6	* (C) Copyright 2003
	7	* Kyle Harris, Nexus Technologies, Inc. [email protected]
	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
50586ef2 AF	10	*/
	11
	12	#include <config.h>
	13	#include <common.h>
	14	#include <command.h>
b33433a6	15	#include <hwconfig.h>
50586ef2 AF	16	#include <mmc.h>
	17	#include <part.h>
	18	#include <malloc.h>
	19	#include <mmc.h>
	20	#include <fsl_esdhc.h>
b33433a6	21	#include <fdt_support.h>
50586ef2 AF	22	#include <asm/io.h>
50586ef2 AF	23
50586ef2 AF	24	DECLARE_GLOBAL_DATA_PTR;
	25
	26	struct fsl_esdhc {
511948b2 HZ	27	uint dsaddr; /* SDMA system address register */
	28	uint blkattr; /* Block attributes register */
	29	uint cmdarg; /* Command argument register */
	30	uint xfertyp; /* Transfer type register */
	31	uint cmdrsp0; /* Command response 0 register */
	32	uint cmdrsp1; /* Command response 1 register */
	33	uint cmdrsp2; /* Command response 2 register */
	34	uint cmdrsp3; /* Command response 3 register */
	35	uint datport; /* Buffer data port register */
	36	uint prsstat; /* Present state register */
	37	uint proctl; /* Protocol control register */
	38	uint sysctl; /* System Control Register */
	39	uint irqstat; /* Interrupt status register */
	40	uint irqstaten; /* Interrupt status enable register */
	41	uint irqsigen; /* Interrupt signal enable register */
	42	uint autoc12err; /* Auto CMD error status register */
	43	uint hostcapblt; /* Host controller capabilities register */
	44	uint wml; /* Watermark level register */
	45	uint mixctrl; /* For USDHC */
	46	char reserved1[4]; /* reserved */
	47	uint fevt; /* Force event register */
	48	uint admaes; /* ADMA error status register */
	49	uint adsaddr; /* ADMA system address register */
	50	char reserved2[160]; /* reserved */
	51	uint hostver; /* Host controller version register */
	52	char reserved3[4]; /* reserved */
	53	uint dmaerraddr; /* DMA error address register */
	54	char reserved4[4]; /* reserved */
	55	uint dmaerrattr; /* DMA error attribute register */
	56	char reserved5[4]; /* reserved */
	57	uint hostcapblt2; /* Host controller capabilities register 2 */
	58	char reserved6[8]; /* reserved */
	59	uint tcr; /* Tuning control register */
	60	char reserved7[28]; /* reserved */
	61	uint sddirctl; /* SD direction control register */
	62	char reserved8[712]; /* reserved */
	63	uint scr; /* eSDHC control register */
50586ef2 AF	64	};
	65
	66	/* Return the XFERTYP flags for a given command and data packet */
eafa90a1	67	static uint esdhc_xfertyp(struct mmc_cmd cmd, struct mmc_data data)
50586ef2 AF	68	{
	69	uint xfertyp = 0;
	70
	71	if (data) {
77c1458d DD	72	xfertyp \|= XFERTYP_DPSEL;
	73	#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
	74	xfertyp \|= XFERTYP_DMAEN;
	75	#endif
50586ef2 AF	76	if (data->blocks > 1) {
	77	xfertyp \|= XFERTYP_MSBSEL;
	78	xfertyp \|= XFERTYP_BCEN;
d621da00 JH	79	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
	80	xfertyp \|= XFERTYP_AC12EN;
	81	#endif
50586ef2 AF	82	}
	83
	84	if (data->flags & MMC_DATA_READ)
	85	xfertyp \|= XFERTYP_DTDSEL;
	86	}
	87
	88	if (cmd->resp_type & MMC_RSP_CRC)
	89	xfertyp \|= XFERTYP_CCCEN;
	90	if (cmd->resp_type & MMC_RSP_OPCODE)
	91	xfertyp \|= XFERTYP_CICEN;
	92	if (cmd->resp_type & MMC_RSP_136)
	93	xfertyp \|= XFERTYP_RSPTYP_136;
	94	else if (cmd->resp_type & MMC_RSP_BUSY)
	95	xfertyp \|= XFERTYP_RSPTYP_48_BUSY;
	96	else if (cmd->resp_type & MMC_RSP_PRESENT)
	97	xfertyp \|= XFERTYP_RSPTYP_48;
	98
b8e5b072	99	#if defined(CONFIG_MX53) \|\| defined(CONFIG_T4240QDS)
4571de33 JL	100	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
	101	xfertyp \|= XFERTYP_CMDTYP_ABORT;
	102	#endif
50586ef2 AF	103	return XFERTYP_CMD(cmd->cmdidx) \| xfertyp;
	104	}
	105
77c1458d DD	106	#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
	107	/*
	108	* PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
	109	*/
7b43db92	110	static void
77c1458d DD	111	esdhc_pio_read_write(struct mmc mmc, struct mmc_data data)
77c1458d DD	112	{
8eee2bd7 IS	113	struct fsl_esdhc_cfg *cfg = mmc->priv;
8eee2bd7 IS	114	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
77c1458d DD	115	uint blocks;
	116	char *buffer;
	117	uint databuf;
	118	uint size;
	119	uint irqstat;
	120	uint timeout;
	121
	122	if (data->flags & MMC_DATA_READ) {
	123	blocks = data->blocks;
	124	buffer = data->dest;
	125	while (blocks) {
	126	timeout = PIO_TIMEOUT;
	127	size = data->blocksize;
	128	irqstat = esdhc_read32(&regs->irqstat);
	129	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
	130	&& --timeout);
	131	if (timeout <= 0) {
	132	printf("\nData Read Failed in PIO Mode.");
7b43db92	133	return;
77c1458d DD	134	}
	135	while (size && (!(irqstat & IRQSTAT_TC))) {
	136	udelay(100); /* Wait before last byte transfer complete */
	137	irqstat = esdhc_read32(&regs->irqstat);
	138	databuf = in_le32(&regs->datport);
	139	((uint )buffer) = databuf;
	140	buffer += 4;
	141	size -= 4;
	142	}
	143	blocks--;
	144	}
	145	} else {
	146	blocks = data->blocks;
7b43db92	147	buffer = (char *)data->src;
77c1458d DD	148	while (blocks) {
	149	timeout = PIO_TIMEOUT;
	150	size = data->blocksize;
	151	irqstat = esdhc_read32(&regs->irqstat);
	152	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
	153	&& --timeout);
	154	if (timeout <= 0) {
	155	printf("\nData Write Failed in PIO Mode.");
7b43db92	156	return;
77c1458d DD	157	}
	158	while (size && (!(irqstat & IRQSTAT_TC))) {
	159	udelay(100); /* Wait before last byte transfer complete */
	160	databuf = ((uint )buffer);
	161	buffer += 4;
	162	size -= 4;
	163	irqstat = esdhc_read32(&regs->irqstat);
	164	out_le32(&regs->datport, databuf);
	165	}
	166	blocks--;
	167	}
	168	}
	169	}
	170	#endif
	171
50586ef2 AF	172	static int esdhc_setup_data(struct mmc mmc, struct mmc_data data)
50586ef2 AF	173	{
50586ef2	174	int timeout;
c67bee14 SB	175	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	176	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
c2137b10	177	#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
7b43db92	178	uint wml_value;
50586ef2 AF	179
	180	wml_value = data->blocksize/4;
	181
	182	if (data->flags & MMC_DATA_READ) {
32c8cfb2 PJ	183	if (wml_value > WML_RD_WML_MAX)
32c8cfb2 PJ	184	wml_value = WML_RD_WML_MAX_VAL;
50586ef2	185
ab467c51	186	esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
c67bee14	187	esdhc_write32(&regs->dsaddr, (u32)data->dest);
50586ef2	188	} else {
e576bd90 EN	189	flush_dcache_range((ulong)data->src,
	190	(ulong)data->src+data->blocks
	191	*data->blocksize);
	192
32c8cfb2 PJ	193	if (wml_value > WML_WR_WML_MAX)
32c8cfb2 PJ	194	wml_value = WML_WR_WML_MAX_VAL;
c67bee14	195	if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
50586ef2 AF	196	printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
	197	return TIMEOUT;
	198	}
ab467c51 RZ	199
	200	esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
	201	wml_value << 16);
c67bee14	202	esdhc_write32(&regs->dsaddr, (u32)data->src);
50586ef2	203	}
7b43db92 WD	204	#else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
	205	if (!(data->flags & MMC_DATA_READ)) {
	206	if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
	207	printf("\nThe SD card is locked. "
	208	"Can not write to a locked card.\n\n");
	209	return TIMEOUT;
	210	}
	211	esdhc_write32(&regs->dsaddr, (u32)data->src);
	212	} else
	213	esdhc_write32(&regs->dsaddr, (u32)data->dest);
	214	#endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
50586ef2	215
c67bee14	216	esdhc_write32(&regs->blkattr, data->blocks << 16 \| data->blocksize);
50586ef2 AF	217
50586ef2 AF	218	/* Calculate the timeout period for data transactions */
b71ea336 PJ	219	/*
	220	* 1)Timeout period = (2^(timeout+13)) SD Clock cycles
	221	* 2)Timeout period should be minimum 0.250sec as per SD Card spec
	222	* So, Number of SD Clock cycles for 0.25sec should be minimum
	223	* (SD Clock/sec * 0.25 sec) SD Clock cycles
	224	* = (mmc->tran_speed * 1/4) SD Clock cycles
	225	* As 1) >= 2)
	226	* => (2^(timeout+13)) >= mmc->tran_speed * 1/4
	227	* Taking log2 both the sides
	228	* => timeout + 13 >= log2(mmc->tran_speed/4)
	229	* Rounding up to next power of 2
	230	* => timeout + 13 = log2(mmc->tran_speed/4) + 1
	231	* => timeout + 13 = fls(mmc->tran_speed/4)
	232	*/
	233	timeout = fls(mmc->tran_speed/4);
50586ef2 AF	234	timeout -= 13;
	235
	236	if (timeout > 14)
	237	timeout = 14;
	238
	239	if (timeout < 0)
	240	timeout = 0;
	241
5103a03a KG	242	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
	243	if ((timeout == 4) \|\| (timeout == 8) \|\| (timeout == 12))
	244	timeout++;
	245	#endif
	246
c67bee14	247	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
50586ef2 AF	248
	249	return 0;
	250	}
	251
e576bd90 EN	252	static void check_and_invalidate_dcache_range
	253	(struct mmc_cmd *cmd,
	254	struct mmc_data *data) {
	255	unsigned start = (unsigned)data->dest ;
	256	unsigned size = roundup(ARCH_DMA_MINALIGN,
	257	data->blocks*data->blocksize);
	258	unsigned end = start+size ;
	259	invalidate_dcache_range(start, end);
	260	}
50586ef2 AF	261	/*
	262	* Sends a command out on the bus. Takes the mmc pointer,
	263	* a command pointer, and an optional data pointer.
	264	*/
	265	static int
	266	esdhc_send_cmd(struct mmc mmc, struct mmc_cmd cmd, struct mmc_data *data)
	267	{
	268	uint xfertyp;
	269	uint irqstat;
c67bee14 SB	270	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	271	volatile struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
50586ef2	272
d621da00 JH	273	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
	274	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
	275	return 0;
	276	#endif
	277
c67bee14	278	esdhc_write32(&regs->irqstat, -1);
50586ef2 AF	279
	280	sync();
	281
	282	/* Wait for the bus to be idle */
c67bee14 SB	283	while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) \|\|
	284	(esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
	285	;
50586ef2	286
c67bee14 SB	287	while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
c67bee14 SB	288	;
50586ef2 AF	289
	290	/* Wait at least 8 SD clock cycles before the next command */
	291	/*
	292	* Note: This is way more than 8 cycles, but 1ms seems to
	293	* resolve timing issues with some cards
	294	*/
	295	udelay(1000);
	296
	297	/* Set up for a data transfer if we have one */
	298	if (data) {
	299	int err;
	300
	301	err = esdhc_setup_data(mmc, data);
	302	if(err)
	303	return err;
	304	}
	305
	306	/* Figure out the transfer arguments */
	307	xfertyp = esdhc_xfertyp(cmd, data);
	308
01b77353 AG	309	/* Mask all irqs */
	310	esdhc_write32(&regs->irqsigen, 0);
	311
50586ef2	312	/* Send the command */
c67bee14	313	esdhc_write32(&regs->cmdarg, cmd->cmdarg);
4692708d JL	314	#if defined(CONFIG_FSL_USDHC)
	315	esdhc_write32(&regs->mixctrl,
	316	(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) \| (xfertyp & 0x7F));
	317	esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
	318	#else
c67bee14	319	esdhc_write32(&regs->xfertyp, xfertyp);
4692708d	320	#endif
7a5b8029	321
50586ef2	322	/* Wait for the command to complete */
7a5b8029	323	while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC \| IRQSTAT_CTOE)))
c67bee14	324	;
50586ef2	325
c67bee14	326	irqstat = esdhc_read32(&regs->irqstat);
50586ef2	327
7a5b8029 DB	328	/* Reset CMD and DATA portions on error */
	329	if (irqstat & (CMD_ERR \| IRQSTAT_CTOE)) {
	330	esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) \|
	331	SYSCTL_RSTC);
	332	while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
	333	;
	334
	335	if (data) {
	336	esdhc_write32(&regs->sysctl,
	337	esdhc_read32(&regs->sysctl) \|
	338	SYSCTL_RSTD);
	339	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
	340	;
	341	}
	342	}
	343
50586ef2 AF	344	if (irqstat & CMD_ERR)
	345	return COMM_ERR;
	346
	347	if (irqstat & IRQSTAT_CTOE)
	348	return TIMEOUT;
	349
7a5b8029 DB	350	/* Workaround for ESDHC errata ENGcm03648 */
	351	if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
	352	int timeout = 2500;
	353
	354	/* Poll on DATA0 line for cmd with busy signal for 250 ms */
	355	while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
	356	PRSSTAT_DAT0)) {
	357	udelay(100);
	358	timeout--;
	359	}
	360
	361	if (timeout <= 0) {
	362	printf("Timeout waiting for DAT0 to go high!\n");
	363	return TIMEOUT;
	364	}
	365	}
	366
50586ef2 AF	367	/* Copy the response to the response buffer */
	368	if (cmd->resp_type & MMC_RSP_136) {
	369	u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
	370
c67bee14 SB	371	cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
	372	cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
	373	cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
	374	cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
998be3dd RV	375	cmd->response[0] = (cmdrsp3 << 8) \| (cmdrsp2 >> 24);
	376	cmd->response[1] = (cmdrsp2 << 8) \| (cmdrsp1 >> 24);
	377	cmd->response[2] = (cmdrsp1 << 8) \| (cmdrsp0 >> 24);
	378	cmd->response[3] = (cmdrsp0 << 8);
50586ef2	379	} else
c67bee14	380	cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
50586ef2 AF	381
	382	/* Wait until all of the blocks are transferred */
	383	if (data) {
77c1458d DD	384	#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
	385	esdhc_pio_read_write(mmc, data);
	386	#else
50586ef2	387	do {
c67bee14	388	irqstat = esdhc_read32(&regs->irqstat);
50586ef2	389
50586ef2 AF	390	if (irqstat & IRQSTAT_DTOE)
50586ef2 AF	391	return TIMEOUT;
63fb5a7e FM	392
	393	if (irqstat & DATA_ERR)
	394	return COMM_ERR;
9b74dc56	395	} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
77c1458d	396	#endif
54899fc8 EN	397	if (data->flags & MMC_DATA_READ)
54899fc8 EN	398	check_and_invalidate_dcache_range(cmd, data);
50586ef2 AF	399	}
50586ef2 AF	400
c67bee14	401	esdhc_write32(&regs->irqstat, -1);
50586ef2 AF	402
	403	return 0;
	404	}
	405
eafa90a1	406	static void set_sysctl(struct mmc *mmc, uint clock)
50586ef2	407	{
50586ef2	408	int div, pre_div;
c67bee14 SB	409	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	410	volatile struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
a2ac1b3a	411	int sdhc_clk = cfg->sdhc_clk;
50586ef2 AF	412	uint clk;
50586ef2 AF	413
c67bee14 SB	414	if (clock < mmc->f_min)
	415	clock = mmc->f_min;
	416
50586ef2 AF	417	if (sdhc_clk / 16 > clock) {
	418	for (pre_div = 2; pre_div < 256; pre_div *= 2)
	419	if ((sdhc_clk / pre_div) <= (clock * 16))
	420	break;
	421	} else
	422	pre_div = 2;
	423
	424	for (div = 1; div <= 16; div++)
	425	if ((sdhc_clk / (div * pre_div)) <= clock)
	426	break;
	427
	428	pre_div >>= 1;
	429	div -= 1;
	430
	431	clk = (pre_div << 8) \| (div << 4);
	432
cc4d1226	433	esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
c67bee14 SB	434
c67bee14 SB	435	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
50586ef2 AF	436
	437	udelay(10000);
	438
cc4d1226	439	clk = SYSCTL_PEREN \| SYSCTL_CKEN;
c67bee14 SB	440
c67bee14 SB	441	esdhc_setbits32(&regs->sysctl, clk);
50586ef2 AF	442	}
	443
	444	static void esdhc_set_ios(struct mmc *mmc)
	445	{
c67bee14 SB	446	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	447	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
50586ef2 AF	448
	449	/* Set the clock speed */
	450	set_sysctl(mmc, mmc->clock);
	451
	452	/* Set the bus width */
c67bee14	453	esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 \| PROCTL_DTW_8);
50586ef2 AF	454
50586ef2 AF	455	if (mmc->bus_width == 4)
c67bee14	456	esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
50586ef2	457	else if (mmc->bus_width == 8)
c67bee14 SB	458	esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
c67bee14 SB	459
50586ef2 AF	460	}
	461
	462	static int esdhc_init(struct mmc *mmc)
	463	{
c67bee14 SB	464	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	465	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
50586ef2 AF	466	int timeout = 1000;
50586ef2 AF	467
c67bee14	468	/* Reset the entire host controller */
a61da72b	469	esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
c67bee14 SB	470
	471	/* Wait until the controller is available */
	472	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
	473	udelay(1000);
50586ef2	474
16e43f35	475	#ifndef ARCH_MXC
2c1764ef	476	/* Enable cache snooping */
16e43f35 BT	477	esdhc_write32(&regs->scr, 0x00000040);
16e43f35 BT	478	#endif
2c1764ef	479
a61da72b	480	esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN \| SYSCTL_IPGEN);
50586ef2 AF	481
50586ef2 AF	482	/* Set the initial clock speed */
4a6ee172	483	mmc_set_clock(mmc, 400000);
50586ef2 AF	484
50586ef2 AF	485	/* Disable the BRR and BWR bits in IRQSTAT */
c67bee14	486	esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR \| IRQSTATEN_BWR);
50586ef2 AF	487
50586ef2 AF	488	/* Put the PROCTL reg back to the default */
c67bee14	489	esdhc_write32(&regs->proctl, PROCTL_INIT);
50586ef2	490
c67bee14 SB	491	/* Set timout to the maximum value */
c67bee14 SB	492	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
50586ef2	493
d48d2e21 TR	494	return 0;
d48d2e21 TR	495	}
50586ef2	496
d48d2e21 TR	497	static int esdhc_getcd(struct mmc *mmc)
	498	{
	499	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	500	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
	501	int timeout = 1000;
	502
f7e27cc5 HZ	503	#ifdef CONFIG_ESDHC_DETECT_QUIRK
	504	if (CONFIG_ESDHC_DETECT_QUIRK)
	505	return 1;
	506	#endif
d48d2e21 TR	507	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
d48d2e21 TR	508	udelay(1000);
c67bee14	509
d48d2e21	510	return timeout > 0;
50586ef2 AF	511	}
50586ef2 AF	512
48bb3bb5 JH	513	static void esdhc_reset(struct fsl_esdhc *regs)
	514	{
	515	unsigned long timeout = 100; /* wait max 100 ms */
	516
	517	/* reset the controller */
a61da72b	518	esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
48bb3bb5 JH	519
	520	/* hardware clears the bit when it is done */
	521	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
	522	udelay(1000);
	523	if (!timeout)
	524	printf("MMC/SD: Reset never completed.\n");
	525	}
	526
ab769f22 PA	527	static const struct mmc_ops esdhc_ops = {
	528	.send_cmd = esdhc_send_cmd,
	529	.set_ios = esdhc_set_ios,
	530	.init = esdhc_init,
	531	.getcd = esdhc_getcd,
	532	};
	533
c67bee14	534	int fsl_esdhc_initialize(bd_t bis, struct fsl_esdhc_cfg cfg)
50586ef2	535	{
c67bee14	536	struct fsl_esdhc *regs;
50586ef2	537	struct mmc *mmc;
030955c2	538	u32 caps, voltage_caps;
50586ef2	539
c67bee14 SB	540	if (!cfg)
	541	return -1;
	542
50586ef2	543	mmc = malloc(sizeof(struct mmc));
3f786a8b FE	544	if (!mmc)
3f786a8b FE	545	return -ENOMEM;
50586ef2	546
a54d6811	547	memset(mmc, 0, sizeof(struct mmc));
4692708d	548	sprintf(mmc->name, "FSL_SDHC");
c67bee14 SB	549	regs = (struct fsl_esdhc *)cfg->esdhc_base;
c67bee14 SB	550
48bb3bb5 JH	551	/* First reset the eSDHC controller */
	552	esdhc_reset(regs);
	553
975324a7 JH	554	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN \| SYSCTL_HCKEN
	555	\| SYSCTL_IPGEN \| SYSCTL_CKEN);
	556
c67bee14	557	mmc->priv = cfg;
ab769f22	558	mmc->ops = &esdhc_ops;
030955c2	559	voltage_caps = 0;
50586ef2	560	caps = regs->hostcapblt;
3b4456ec RZ	561
	562	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
	563	caps = caps & ~(ESDHC_HOSTCAPBLT_SRS \|
	564	ESDHC_HOSTCAPBLT_VS18 \| ESDHC_HOSTCAPBLT_VS30);
	565	#endif
ef38f3ff HZ	566
	567	/* T4240 host controller capabilities register should have VS33 bit */
	568	#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
	569	caps = caps \| ESDHC_HOSTCAPBLT_VS33;
	570	#endif
	571
50586ef2	572	if (caps & ESDHC_HOSTCAPBLT_VS18)
030955c2	573	voltage_caps \|= MMC_VDD_165_195;
50586ef2	574	if (caps & ESDHC_HOSTCAPBLT_VS30)
030955c2	575	voltage_caps \|= MMC_VDD_29_30 \| MMC_VDD_30_31;
50586ef2	576	if (caps & ESDHC_HOSTCAPBLT_VS33)
030955c2 LY	577	voltage_caps \|= MMC_VDD_32_33 \| MMC_VDD_33_34;
	578
	579	#ifdef CONFIG_SYS_SD_VOLTAGE
	580	mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
	581	#else
	582	mmc->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34;
	583	#endif
	584	if ((mmc->voltages & voltage_caps) == 0) {
	585	printf("voltage not supported by controller\n");
	586	return -1;
	587	}
50586ef2	588
fb8302bf	589	mmc->host_caps = MMC_MODE_4BIT \| MMC_MODE_8BIT \| MMC_MODE_HC;
50586ef2	590
aad4659a AR	591	if (cfg->max_bus_width > 0) {
	592	if (cfg->max_bus_width < 8)
	593	mmc->host_caps &= ~MMC_MODE_8BIT;
	594	if (cfg->max_bus_width < 4)
	595	mmc->host_caps &= ~MMC_MODE_4BIT;
	596	}
	597
50586ef2 AF	598	if (caps & ESDHC_HOSTCAPBLT_HSS)
	599	mmc->host_caps \|= MMC_MODE_HS_52MHz \| MMC_MODE_HS;
	600
d47e3d27 HZ	601	#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
	602	if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
	603	mmc->host_caps &= ~MMC_MODE_8BIT;
	604	#endif
	605
50586ef2	606	mmc->f_min = 400000;
e9adeca3	607	mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000);
50586ef2	608
1ed60d7a	609	mmc->b_max = 0;
50586ef2 AF	610	mmc_register(mmc);
	611
	612	return 0;
	613	}
	614
	615	int fsl_esdhc_mmc_init(bd_t *bis)
	616	{
c67bee14 SB	617	struct fsl_esdhc_cfg *cfg;
c67bee14 SB	618
88227a1d	619	cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
c67bee14	620	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
e9adeca3	621	cfg->sdhc_clk = gd->arch.sdhc_clk;
c67bee14	622	return fsl_esdhc_initialize(bis, cfg);
50586ef2	623	}
b33433a6	624
c67bee14	625	#ifdef CONFIG_OF_LIBFDT
b33433a6 AV	626	void fdt_fixup_esdhc(void blob, bd_t bd)
	627	{
	628	const char *compat = "fsl,esdhc";
b33433a6	629
a6da8b81	630	#ifdef CONFIG_FSL_ESDHC_PIN_MUX
b33433a6	631	if (!hwconfig("esdhc")) {
a6da8b81 CZ	632	do_fixup_by_compat(blob, compat, "status", "disabled",
	633	8 + 1, 1);
	634	return;
b33433a6	635	}
a6da8b81	636	#endif
b33433a6 AV	637
b33433a6 AV	638	do_fixup_by_compat_u32(blob, compat, "clock-frequency",
e9adeca3	639	gd->arch.sdhc_clk, 1);
a6da8b81 CZ	640
	641	do_fixup_by_compat(blob, compat, "status", "okay",
	642	4 + 1, 1);
b33433a6	643	}
c67bee14	644	#endif