[u-boot.git] / include / configs / kmvect1.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2006 Freescale Semiconductor, Inc.
 *                    Dave Liu <[email protected]>
 *
 * Copyright (C) 2007 Logic Product Development, Inc.
 *                    Peter Barada <[email protected]>
 *
 * Copyright (C) 2007 MontaVista Software, Inc.
 *                    Anton Vorontsov <[email protected]>
 *
 * (C) Copyright 2010
 * Heiko Schocher, DENX Software Engineering, [email protected].
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */

#define CONFIG_HOSTNAME		"kmvect1"
#define CONFIG_KM_BOARD_NAME   "kmvect1"
/* at end of uboot partition, before env */
#define CONFIG_SYS_QE_FW_ADDR   0xF00B0000

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1	/* E300 family */
#define CONFIG_QE		1	/* Has QE */

#define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"

/* include common defines/options for all Keymile boards */
#include "km/keymile-common.h"
#include "km/km-powerpc.h"

/*
 * System Clock Setup
 */
#define CONFIG_83XX_CLKIN		66000000
#define CONFIG_SYS_CLK_FREQ		66000000
#define CONFIG_83XX_PCICLK		66000000

/*
 * IMMR new address
 */
#define CONFIG_SYS_IMMR		0xE0000000

/*
 * Bus Arbitration Configuration Register (ACR)
 */
#define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
#define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
#define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
#define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */

/*
 * DDR Setup
 */
#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */

#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)

#define CFG_83XX_DDR_USES_CS0

/*
 * Manually set up DDR parameters
 */
#define CONFIG_DDR_II
#define CONFIG_SYS_DDR_SIZE		2048 /* MB */

/*
 * The reserved memory
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_FLASH_BASE		0xF0000000

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#endif

/* Reserve 768 kB for Mon */
#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)

/*
 * Initial RAM Base Address Setup
 */
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* End of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
						GENERATED_GBL_DATA_SIZE)

/*
 * Init Local Bus Memory Controller:
 *
 * Bank Bus     Machine PortSz  Size  Device
 * ---- ---     ------- ------  -----  ------
 *  0   Local   GPCM    16 bit  256MB FLASH
 *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 *
 */
/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_SIZE		256 /* max FLASH size is 256M */

/* FLASH */
#define CONFIG_SYS_BR0_PRELIM	(0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
#define CONFIG_SYS_OR0_PRELIM	(OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)

#define CONFIG_SYS_MAX_FLASH_BANKS	1   /* max num of flash banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	512 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }

/*
 * PRIO1/PIGGY on the local bus CS1
 */

/* KMBEC_FPGA */
#define CONFIG_SYS_BR1_PRELIM	(0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
#define CONFIG_SYS_OR1_PRELIM	(OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)

/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)

/*
 * QE UEC ethernet configuration
 */
#define CONFIG_UEC_ETH
#define CONFIG_ETHPRIME		"UEC0"

#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM	3	/* UCC4 */
#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK17
#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR	0
#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
#endif

/*
 * Environment
 */

#ifndef CONFIG_SYS_RAMBOOT
#ifndef CONFIG_ENV_ADDR
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
					CONFIG_SYS_MONITOR_LEN)
#endif
#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
#ifndef CONFIG_ENV_OFFSET
#define CONFIG_ENV_OFFSET	(CONFIG_SYS_MONITOR_LEN)
#endif

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
						CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#else /* CFG_SYS_RAMBOOT */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE		0x2000
#endif /* CFG_SYS_RAMBOOT */

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_NUM_I2C_BUSES	4
#define CONFIG_SYS_I2C_MAX_HOPS		1
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	200000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_OFFSET		0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	200000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
#define CONFIG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP} }, \
		{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
		{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
		{1, {I2C_NULL_HOP} } }

#define CONFIG_KM_IVM_BUS		2	/* I2C2 (Mux-Port 1)*/

#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_KMETER1
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		CONFIG_SYS_KMBEC_FPGA_BASE
#endif

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)

/*
 * Core HID Setup
 */
#define CONFIG_SYS_HID0_INIT		0x000000000
#define CONFIG_SYS_HID0_FINAL		(HID0_ENABLE_MACHINE_CHECK | \
					 HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2			HID2_HBE

/*
 * Internal Definitions
 */
#define BOOTFLASH_START	0xF0000000

#define CONFIG_KM_CONSOLE_TTY	"ttyS0"

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE
#ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
#define CONFIG_KM_DEF_ENV "km-common=empty\0"
#endif

#ifndef CONFIG_KM_DEF_ARCH
#define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
#endif

#define CONFIG_EXTRA_ENV_SETTINGS \
	CONFIG_KM_DEF_ENV						\
	CONFIG_KM_DEF_ARCH						\
	"newenv="							\
		"prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "	\
		"era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"		\
	"unlock=yes\0"							\
	""

#if defined(CONFIG_UEC_ETH)
#define CONFIG_HAS_ETH0
#endif

/* QE microcode/firmware address */
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
/* between the u-boot partition and env */
#ifndef CONFIG_SYS_QE_FW_ADDR
#define CONFIG_SYS_QE_FW_ADDR   0xF00C0000
#endif

/*
 * System IO Config
 */
/* 0x14000180 SICR_1 */
#define CONFIG_SYS_SICRL (0			\
		| SICR_1_UART1_UART1RTS		\
		| SICR_1_I2C_CKSTOP		\
		| SICR_1_IRQ_A_IRQ		\
		| SICR_1_IRQ_B_IRQ		\
		| SICR_1_GPIO_A_GPIO		\
		| SICR_1_GPIO_B_GPIO		\
		| SICR_1_GPIO_C_GPIO		\
		| SICR_1_GPIO_D_GPIO		\
		| SICR_1_GPIO_E_GPIO		\
		| SICR_1_GPIO_F_GPIO		\
		| SICR_1_USB_A_UART2S		\
		| SICR_1_USB_B_UART2RTS		\
		| SICR_1_FEC1_FEC1		\
		| SICR_1_FEC2_FEC2		\
		)

/* 0x00080400 SICR_2 */
#define CONFIG_SYS_SICRH (0			\
		| SICR_2_FEC3_FEC3		\
		| SICR_2_HDLC1_A_HDLC1		\
		| SICR_2_ELBC_A_LA		\
		| SICR_2_ELBC_B_LCLK		\
		| SICR_2_HDLC2_A_HDLC2		\
		| SICR_2_USB_D_GPIO		\
		| SICR_2_PCI_PCI		\
		| SICR_2_HDLC1_B_HDLC1		\
		| SICR_2_HDLC1_C_HDLC1		\
		| SICR_2_HDLC2_B_GPIO		\
		| SICR_2_HDLC2_C_HDLC2		\
		| SICR_2_QUIESCE_B		\
		)

/* GPR_1 */
#define CONFIG_SYS_GPR1  0x50008060

#define CONFIG_SYS_GP1DIR 0x00000000
#define CONFIG_SYS_GP1ODR 0x00000000
#define CONFIG_SYS_GP2DIR 0xFF000000
#define CONFIG_SYS_GP2ODR 0x00000000

#define CONFIG_SYS_DDRCDR (\
	DDRCDR_EN | \
	DDRCDR_PZ_MAXZ | \
	DDRCDR_NZ_MAXZ | \
	DDRCDR_M_ODR)

#define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
					 SDRAM_CFG_32_BE | \
					 SDRAM_CFG_SREN | \
					 SDRAM_CFG_HSE)

#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
#define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))

#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
					 CSCONFIG_ODT_RD_NEVER | \
					 CSCONFIG_ODT_WR_ONLY_CURRENT | \
					 CSCONFIG_ROW_BIT_13 | \
					 CSCONFIG_COL_BIT_10)

#define CONFIG_SYS_DDR_MODE	0x47860242
#define CONFIG_SYS_DDR_MODE2	0x8080c000

#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
				 (0 << TIMING_CFG0_WWT_SHIFT) | \
				 (0 << TIMING_CFG0_RRT_SHIFT) | \
				 (0 << TIMING_CFG0_WRT_SHIFT) | \
				 (0 << TIMING_CFG0_RWT_SHIFT))

#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
				 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
				 (3 << TIMING_CFG1_PRETOACT_SHIFT))

#define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
				 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
				 (5 << TIMING_CFG2_CPO_SHIFT))

#define CONFIG_SYS_DDR_TIMING_3	0x00000000

#define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
#define CONFIG_SYS_KMBEC_FPGA_SIZE	128

/* EEprom support */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1

/*
 * Local Bus Configuration & Clock Setup
 */
#define CONFIG_SYS_LCRR_DBYP	0x80000000
#define CONFIG_SYS_LCRR_EADC	0x00010000
#define CONFIG_SYS_LCRR_CLKDIV	0x00000002

#define CONFIG_SYS_LBC_LBCR	0x00000000

#define CONFIG_SYS_APP1_BASE		0xA0000000
#define CONFIG_SYS_APP1_SIZE		256 /* Megabytes */
#define CONFIG_SYS_APP2_BASE		0xB0000000
#define CONFIG_SYS_APP2_SIZE		256 /* Megabytes */

/* EEprom support */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1

/*
 * Init Local Bus Memory Controller:
 *
 * Bank Bus     Machine PortSz  Size  Device
 * ---- ---     ------- ------  -----  ------
 *  2   Local   UPMA    16 bit  256MB APP1
 *  3   Local   GPCM    16 bit  256MB APP2
 *
 */

/* APP1 */
#define CONFIG_SYS_BR2_PRELIM	(0xA0000000 | BR_PS_16 | BR_MS_UPMA | BR_V)
#define CONFIG_SYS_OR2_PRELIM	(OR_AM_256MB)

/* APP2 */
#define CONFIG_SYS_BR3_PRELIM	(0xB0000000 | BR_PS_16 | BR_V)
#define CONFIG_SYS_OR3_PRELIM	(OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET)

#define CONFIG_SYS_MAMR	(MxMR_GPL_x4DIS | \
			 0x0000c000 | \
			 MxMR_WLFx_2X)
/*
 * QE UEC ethernet configuration
 */
#define CONFIG_MV88E6352_SWITCH
#define CONFIG_KM_MVEXTSW_ADDR		0x10

/* ethernet port connected to simple switch 88e6122 (UEC0) */
#define CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM		0	/* UCC1 */
#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10

#define CONFIG_FIXED_PHY		0xFFFFFFFF
#define CONFIG_SYS_FIXED_PHY_ADDR	0x1E	/* unused address */
#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
		{devnum, speed, duplex}
#define CONFIG_SYS_FIXED_PHY_PORTS \
		CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)

#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR	CONFIG_SYS_FIXED_PHY_ADDR
#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100

/* ethernet port connected to piggy (UEC2) */
#define CONFIG_HAS_ETH1
#define CONFIG_UEC_ETH2
#define CONFIG_SYS_UEC2_UCC_NUM		2       /* UCC3 */
#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK12
#define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR	0
#define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC2_INTERFACE_SPEED	100

#endif /* __CONFIG_H */
Commit	Line	Data
0e0674fc MS	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* Copyright (C) 2006 Freescale Semiconductor, Inc.
	4	* Dave Liu <[email protected]>
	5	*
	6	* Copyright (C) 2007 Logic Product Development, Inc.
	7	* Peter Barada <[email protected]>
	8	*
	9	* Copyright (C) 2007 MontaVista Software, Inc.
	10	* Anton Vorontsov <[email protected]>
	11	*
	12	* (C) Copyright 2010
	13	* Heiko Schocher, DENX Software Engineering, [email protected].
	14	*/
	15
	16	#ifndef __CONFIG_H
	17	#define __CONFIG_H
	18
	19	/*
	20	* High Level Configuration Options
	21	*/
	22
0e0674fc MS	23	#define CONFIG_HOSTNAME "kmvect1"
	24	#define CONFIG_KM_BOARD_NAME "kmvect1"
	25	/* at end of uboot partition, before env */
	26	#define CONFIG_SYS_QE_FW_ADDR 0xF00B0000
0e890d4c MS	27
	28	/*
	29	* High Level Configuration Options
	30	*/
	31	#define CONFIG_E300 1 /* E300 family */
	32	#define CONFIG_QE 1 /* Has QE */
	33
	34	#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
	35
fb1b099f MS	36	/* include common defines/options for all Keymile boards */
	37	#include "km/keymile-common.h"
	38	#include "km/km-powerpc.h"
	39
	40	/*
	41	* System Clock Setup
	42	*/
	43	#define CONFIG_83XX_CLKIN 66000000
	44	#define CONFIG_SYS_CLK_FREQ 66000000
	45	#define CONFIG_83XX_PCICLK 66000000
	46
	47	/*
	48	* IMMR new address
	49	*/
	50	#define CONFIG_SYS_IMMR 0xE0000000
	51
	52	/*
	53	* Bus Arbitration Configuration Register (ACR)
	54	*/
	55	#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
	56	#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
	57	#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
	58	#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
	59
	60	/*
	61	* DDR Setup
	62	*/
	63	#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
	64	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
	65	#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
	66
	67	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
	68	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \| \
	69	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
	70
	71	#define CFG_83XX_DDR_USES_CS0
	72
	73	/*
	74	* Manually set up DDR parameters
	75	*/
	76	#define CONFIG_DDR_II
	77	#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
	78
	79	/*
	80	* The reserved memory
	81	*/
	82	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	83	#define CONFIG_SYS_FLASH_BASE 0xF0000000
	84
	85	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	86	#define CONFIG_SYS_RAMBOOT
	87	#endif
	88
	89	/* Reserve 768 kB for Mon */
	90	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
	91
	92	/*
	93	* Initial RAM Base Address Setup
	94	*/
	95	#define CONFIG_SYS_INIT_RAM_LOCK
	96	#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
	97	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
	98	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	99	GENERATED_GBL_DATA_SIZE)
100
101	/*
102	* Init Local Bus Memory Controller:
103	*
104	* Bank Bus Machine PortSz Size Device
105	* ---- --- ------- ------ ----- ------
106	* 0 Local GPCM 16 bit 256MB FLASH
107	* 1 Local GPCM 8 bit 128MB GPIO/PIGGY
108	*
109	*/
110	/*
111	* FLASH on the Local Bus
112	*/
113	#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
114
a8f97539 MS	115	/* FLASH */
	116	#define CONFIG_SYS_BR0_PRELIM (0xF0000000 \| BR_PS_16 \| BR_MS_GPCM \| BR_V)
	117	#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB \| OR_GPCM_CSNT \| OR_GPCM_ACS_DIV2 \| OR_GPCM_SCY_5 \| OR_GPCM_TRLX_SET \| OR_GPCM_EAD)
fb1b099f MS	118
	119	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
	120	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
	121	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	122
	123	/*
	124	* PRIO1/PIGGY on the local bus CS1
	125	*/
a8f97539 MS	126
	127	/* KMBEC_FPGA */
	128	#define CONFIG_SYS_BR1_PRELIM (0xE8000000 \| BR_PS_8 \| BR_MS_GPCM \| BR_V)
	129	#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB \| OR_GPCM_CSNT \| OR_GPCM_ACS_DIV2 \| OR_GPCM_SCY_2 \| OR_GPCM_TRLX_SET \| OR_GPCM_EAD)
fb1b099f MS	130
	131	/*
	132	* Serial Port
	133	*/
	134	#define CONFIG_SYS_NS16550_SERIAL
	135	#define CONFIG_SYS_NS16550_REG_SIZE 1
	136	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	137
	138	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
	139	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
	140
	141	/*
	142	* QE UEC ethernet configuration
	143	*/
	144	#define CONFIG_UEC_ETH
	145	#define CONFIG_ETHPRIME "UEC0"
	146
	147	#ifdef CONFIG_UEC_ETH1
	148	#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
	149	#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
	150	#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
	151	#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
	152	#define CONFIG_SYS_UEC1_PHY_ADDR 0
	153	#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
	154	#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
	155	#endif
	156
	157	/*
	158	* Environment
	159	*/
	160
	161	#ifndef CONFIG_SYS_RAMBOOT
	162	#ifndef CONFIG_ENV_ADDR
	163	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
	164	CONFIG_SYS_MONITOR_LEN)
	165	#endif
	166	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
	167	#ifndef CONFIG_ENV_OFFSET
	168	#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
	169	#endif
	170
	171	/* Address and size of Redundant Environment Sector */
	172	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
	173	CONFIG_ENV_SECT_SIZE)
	174	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	175
	176	#else /* CFG_SYS_RAMBOOT */
	177	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
	178	#define CONFIG_ENV_SIZE 0x2000
	179	#endif /* CFG_SYS_RAMBOOT */
	180
	181	/* I2C */
	182	#define CONFIG_SYS_I2C
	183	#define CONFIG_SYS_NUM_I2C_BUSES 4
	184	#define CONFIG_SYS_I2C_MAX_HOPS 1
	185	#define CONFIG_SYS_I2C_FSL
	186	#define CONFIG_SYS_FSL_I2C_SPEED 200000
	187	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	188	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	189	#define CONFIG_SYS_I2C_OFFSET 0x3000
	190	#define CONFIG_SYS_FSL_I2C2_SPEED 200000
	191	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	192	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
	193	#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
194	{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
195	{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
196	{1, {I2C_NULL_HOP} } }
197
198	#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
199
200	#if defined(CONFIG_CMD_NAND)
201	#define CONFIG_NAND_KMETER1
202	#define CONFIG_SYS_MAX_NAND_DEVICE 1
203	#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
204	#endif
205
206	/*
207	* For booting Linux, the board info and command line data
208	* have to be in the first 8 MB of memory, since this is
209	* the maximum mapped by the Linux kernel during initialization.
210	*/
211	#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
212
213	/*
214	* Core HID Setup
215	*/
216	#define CONFIG_SYS_HID0_INIT 0x000000000
217	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \| \
218	HID0_ENABLE_INSTRUCTION_CACHE)
219	#define CONFIG_SYS_HID2 HID2_HBE
220
fb1b099f MS	221	/*
	222	* Internal Definitions
	223	*/
	224	#define BOOTFLASH_START 0xF0000000
	225
	226	#define CONFIG_KM_CONSOLE_TTY "ttyS0"
	227
	228	/*
	229	* Environment Configuration
	230	*/
	231	#define CONFIG_ENV_OVERWRITE
	232	#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
	233	#define CONFIG_KM_DEF_ENV "km-common=empty\0"
	234	#endif
	235
	236	#ifndef CONFIG_KM_DEF_ARCH
	237	#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
	238	#endif
	239
	240	#define CONFIG_EXTRA_ENV_SETTINGS \
	241	CONFIG_KM_DEF_ENV \
	242	CONFIG_KM_DEF_ARCH \
	243	"newenv=" \
	244	"prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \
	245	"era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \
	246	"unlock=yes\0" \
	247	""
	248
	249	#if defined(CONFIG_UEC_ETH)
	250	#define CONFIG_HAS_ETH0
	251	#endif
0e890d4c MS	252
	253	/* QE microcode/firmware address */
	254	#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
	255	/* between the u-boot partition and env */
	256	#ifndef CONFIG_SYS_QE_FW_ADDR
	257	#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000
	258	#endif
	259
	260	/*
	261	* System IO Config
	262	*/
	263	/* 0x14000180 SICR_1 */
	264	#define CONFIG_SYS_SICRL (0 \
	265	\| SICR_1_UART1_UART1RTS \
	266	\| SICR_1_I2C_CKSTOP \
	267	\| SICR_1_IRQ_A_IRQ \
	268	\| SICR_1_IRQ_B_IRQ \
	269	\| SICR_1_GPIO_A_GPIO \
	270	\| SICR_1_GPIO_B_GPIO \
	271	\| SICR_1_GPIO_C_GPIO \
	272	\| SICR_1_GPIO_D_GPIO \
	273	\| SICR_1_GPIO_E_GPIO \
	274	\| SICR_1_GPIO_F_GPIO \
	275	\| SICR_1_USB_A_UART2S \
	276	\| SICR_1_USB_B_UART2RTS \
	277	\| SICR_1_FEC1_FEC1 \
	278	\| SICR_1_FEC2_FEC2 \
	279	)
	280
	281	/* 0x00080400 SICR_2 */
	282	#define CONFIG_SYS_SICRH (0 \
	283	\| SICR_2_FEC3_FEC3 \
	284	\| SICR_2_HDLC1_A_HDLC1 \
	285	\| SICR_2_ELBC_A_LA \
	286	\| SICR_2_ELBC_B_LCLK \
	287	\| SICR_2_HDLC2_A_HDLC2 \
	288	\| SICR_2_USB_D_GPIO \
	289	\| SICR_2_PCI_PCI \
	290	\| SICR_2_HDLC1_B_HDLC1 \
	291	\| SICR_2_HDLC1_C_HDLC1 \
	292	\| SICR_2_HDLC2_B_GPIO \
	293	\| SICR_2_HDLC2_C_HDLC2 \
	294	\| SICR_2_QUIESCE_B \
	295	)
	296
	297	/* GPR_1 */
	298	#define CONFIG_SYS_GPR1 0x50008060
	299
	300	#define CONFIG_SYS_GP1DIR 0x00000000
	301	#define CONFIG_SYS_GP1ODR 0x00000000
	302	#define CONFIG_SYS_GP2DIR 0xFF000000
	303	#define CONFIG_SYS_GP2ODR 0x00000000
	304
0e890d4c MS	305	#define CONFIG_SYS_DDRCDR (\
	306	DDRCDR_EN \| \
	307	DDRCDR_PZ_MAXZ \| \
	308	DDRCDR_NZ_MAXZ \| \
	309	DDRCDR_M_ODR)
	310
	311	#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
	312	#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 \| \
	313	SDRAM_CFG_32_BE \| \
	314	SDRAM_CFG_SREN \| \
	315	SDRAM_CFG_HSE)
	316
	317	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
	318	#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
	319	#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) \| \
	320	(0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
	321
	322	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \| CSCONFIG_AP \| \
	323	CSCONFIG_ODT_RD_NEVER \| \
	324	CSCONFIG_ODT_WR_ONLY_CURRENT \| \
	325	CSCONFIG_ROW_BIT_13 \| \
	326	CSCONFIG_COL_BIT_10)
	327
	328	#define CONFIG_SYS_DDR_MODE 0x47860242
	329	#define CONFIG_SYS_DDR_MODE2 0x8080c000
	330
	331	#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) \| \
	332	(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \| \
	333	(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \| \
	334	(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \| \
	335	(0 << TIMING_CFG0_WWT_SHIFT) \| \
	336	(0 << TIMING_CFG0_RRT_SHIFT) \| \
	337	(0 << TIMING_CFG0_WRT_SHIFT) \| \
	338	(0 << TIMING_CFG0_RWT_SHIFT))
	339
	340	#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) \| \
	341	(2 << TIMING_CFG1_WRTORD_SHIFT) \| \
	342	(2 << TIMING_CFG1_ACTTOACT_SHIFT) \| \
	343	(3 << TIMING_CFG1_WRREC_SHIFT) \| \
	344	(7 << TIMING_CFG1_REFREC_SHIFT) \| \
	345	(3 << TIMING_CFG1_ACTTORW_SHIFT) \| \
	346	(7 << TIMING_CFG1_ACTTOPRE_SHIFT) \| \
	347	(3 << TIMING_CFG1_PRETOACT_SHIFT))
	348
	349	#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) \| \
	350	(3 << TIMING_CFG2_CKE_PLS_SHIFT) \| \
	351	(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \| \
	352	(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \| \
	353	(3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \| \
	354	(0 << TIMING_CFG2_ADD_LAT_SHIFT) \| \
	355	(5 << TIMING_CFG2_CPO_SHIFT))
	356
	357	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
	358
	359	#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
	360	#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
	361
	362	/* EEprom support */
	363	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	364
	365	/*
	366	* Local Bus Configuration & Clock Setup
	367	*/
	368	#define CONFIG_SYS_LCRR_DBYP 0x80000000
369	#define CONFIG_SYS_LCRR_EADC 0x00010000
370	#define CONFIG_SYS_LCRR_CLKDIV 0x00000002
371
372	#define CONFIG_SYS_LBC_LBCR 0x00000000
373
0e0674fc MS	374	#define CONFIG_SYS_APP1_BASE 0xA0000000
	375	#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
	376	#define CONFIG_SYS_APP2_BASE 0xB0000000
	377	#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
	378
	379	/* EEprom support */
	380	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	381
	382	/*
	383	* Init Local Bus Memory Controller:
	384	*
	385	* Bank Bus Machine PortSz Size Device
	386	* ---- --- ------- ------ ----- ------
	387	* 2 Local UPMA 16 bit 256MB APP1
	388	* 3 Local GPCM 16 bit 256MB APP2
	389	*
	390	*/
	391
a8f97539 MS	392	/* APP1 */
a8f97539 MS	393	#define CONFIG_SYS_BR2_PRELIM (0xA0000000 \| BR_PS_16 \| BR_MS_UPMA \| BR_V)
5d2f4c96	394	#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB)
0e0674fc	395
a8f97539 MS	396	/* APP2 */
	397	#define CONFIG_SYS_BR3_PRELIM (0xB0000000 \| BR_PS_16 \| BR_V)
	398	#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB \| OR_GPCM_CSNT \| OR_GPCM_ACS_DIV4 \| OR_GPCM_SCY_3 \| OR_GPCM_TRLX_SET)
0e0674fc MS	399
	400	#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS \| \
	401	0x0000c000 \| \
	402	MxMR_WLFx_2X)
0e0674fc MS	403	/*
	404	* QE UEC ethernet configuration
	405	*/
	406	#define CONFIG_MV88E6352_SWITCH
	407	#define CONFIG_KM_MVEXTSW_ADDR 0x10
	408
	409	/* ethernet port connected to simple switch 88e6122 (UEC0) */
	410	#define CONFIG_UEC_ETH1
	411	#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
	412	#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
	413	#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
	414
	415	#define CONFIG_FIXED_PHY 0xFFFFFFFF
	416	#define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */
	417	#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
	418	{devnum, speed, duplex}
	419	#define CONFIG_SYS_FIXED_PHY_PORTS \
	420	CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
	421
	422	#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
	423	#define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
	424	#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
	425	#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
	426
	427	/* ethernet port connected to piggy (UEC2) */
	428	#define CONFIG_HAS_ETH1
	429	#define CONFIG_UEC_ETH2
	430	#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */
	431	#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
	432	#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12
	433	#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
	434	#define CONFIG_SYS_UEC2_PHY_ADDR 0
	435	#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
	436	#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
	437
	438	#endif /* __CONFIG_H */