[u-boot.git] / arch / arm / cpu / arm926ejs / kirkwood / cpu.c

/*
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Prafulla Wadaskar <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301 USA
 */

#include <common.h>
#include <netdev.h>
#include <asm/cache.h>
#include <u-boot/md5.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/kirkwood.h>
#include <hush.h>

#define BUFLEN	16

void reset_cpu(unsigned long ignored)
{
	struct kwcpu_registers *cpureg =
	    (struct kwcpu_registers *)KW_CPU_REG_BASE;

	writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
		&cpureg->rstoutn_mask);
	writel(readl(&cpureg->sys_soft_rst) | 1,
		&cpureg->sys_soft_rst);
	while (1) ;
}

/*
 * Generates Ramdom hex number reading some time varient system registers
 * and using md5 algorithm
 */
unsigned char get_random_hex(void)
{
	int i;
	u32 inbuf[BUFLEN];
	u8 outbuf[BUFLEN];

	/*
	 * in case of 88F6281/88F6282/88F6192 A0,
	 * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
	 * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are
	 * reserved regs and does not have names at this moment
	 * (no errata available)
	 */
	writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478);
	for (i = 0; i < BUFLEN; i++) {
		inbuf[i] = readl(KW_REG_UNDOC_0x1470);
	}
	md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf);
	return outbuf[outbuf[7] % 0x0f];
}

/*
 * Window Size
 * Used with the Base register to set the address window size and location.
 * Must be programmed from LSB to MSB as sequence of ones followed by
 * sequence of zeros. The number of ones specifies the size of the window in
 * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
 * NOTE: A value of 0x0 specifies 64-KByte size.
 */
unsigned int kw_winctrl_calcsize(unsigned int sizeval)
{
	int i;
	unsigned int j = 0;
	u32 val = sizeval >> 1;

	for (i = 0; val >= 0x10000; i++) {
		j |= (1 << i);
		val = val >> 1;
	}
	return (0x0000ffff & j);
}

/*
 * kw_config_adr_windows - Configure address Windows
 *
 * There are 8 address windows supported by Kirkwood Soc to addess different
 * devices. Each window can be configured for size, BAR and remap addr
 * Below configuration is standard for most of the cases
 *
 * If remap function not used, remap_lo must be set as base
 *
 * Reference Documentation:
 * Mbus-L to Mbus Bridge Registers Configuration.
 * (Sec 25.1 and 25.3 of Datasheet)
 */
int kw_config_adr_windows(void)
{
	struct kwwin_registers *winregs =
		(struct kwwin_registers *)KW_CPU_WIN_BASE;

	/* Window 0: PCIE MEM address space */
	writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
		KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);

	writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
	writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
	writel(0x0, &winregs[0].remap_hi);

	/* Window 1: PCIE IO address space */
	writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
		KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
	writel(KW_DEFADR_PCI_IO, &winregs[1].base);
	writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
	writel(0x0, &winregs[1].remap_hi);

	/* Window 2: NAND Flash address space */
	writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
		KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
	writel(KW_DEFADR_NANDF, &winregs[2].base);
	writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
	writel(0x0, &winregs[2].remap_hi);

	/* Window 3: SPI Flash address space */
	writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
		KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
	writel(KW_DEFADR_SPIF, &winregs[3].base);
	writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
	writel(0x0, &winregs[3].remap_hi);

	/* Window 4: BOOT Memory address space */
	writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
		KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
	writel(KW_DEFADR_BOOTROM, &winregs[4].base);

	/* Window 5: Security SRAM address space */
	writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
		KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
	writel(KW_DEFADR_SASRAM, &winregs[5].base);

	/* Window 6-7: Disabled */
	writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
	writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);

	return 0;
}

/*
 * kw_config_gpio - GPIO configuration
 */
void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
{
	struct kwgpio_registers *gpio0reg =
		(struct kwgpio_registers *)KW_GPIO0_BASE;
	struct kwgpio_registers *gpio1reg =
		(struct kwgpio_registers *)KW_GPIO1_BASE;

	/* Init GPIOS to default values as per board requirement */
	writel(gpp0_oe_val, &gpio0reg->dout);
	writel(gpp1_oe_val, &gpio1reg->dout);
	writel(gpp0_oe, &gpio0reg->oe);
	writel(gpp1_oe, &gpio1reg->oe);
}

/*
 * kw_config_mpp - Multi-Purpose Pins Functionality configuration
 *
 * Each MPP can be configured to different functionality through
 * MPP control register, ref (sec 6.1 of kirkwood h/w specification)
 *
 * There are maximum 64 Multi-Pourpose Pins on Kirkwood
 * Each MPP functionality can be configuration by a 4bit value
 * of MPP control reg, the value and associated functionality depends
 * upon used SoC varient
 */
int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31,
		u32 mpp32_39, u32 mpp40_47, u32 mpp48_55)
{
	u32 *mppreg = (u32 *) KW_MPP_BASE;

	/* program mpp registers */
	writel(mpp0_7, &mppreg[0]);
	writel(mpp8_15, &mppreg[1]);
	writel(mpp16_23, &mppreg[2]);
	writel(mpp24_31, &mppreg[3]);
	writel(mpp32_39, &mppreg[4]);
	writel(mpp40_47, &mppreg[5]);
	writel(mpp48_55, &mppreg[6]);
	return 0;
}

/*
 * SYSRSTn Duration Counter Support
 *
 * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
 * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
 * The SYSRSTn duration counter is useful for implementing a manufacturer
 * or factory reset. Upon a long reset assertion that is greater than a
 * pre-configured environment variable value for sysrstdelay,
 * The counter value is stored in the SYSRSTn Length Counter Register
 * The counter is based on the 25-MHz reference clock (40ns)
 * It is a 29-bit counter, yielding a maximum counting duration of
 * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
 * it remains at this value until counter reset is triggered by setting
 * bit 31 of KW_REG_SYSRST_CNT
 */
static void kw_sysrst_action(void)
{
	int ret;
	char *s = getenv("sysrstcmd");

	if (!s) {
		debug("Error.. %s failed, check sysrstcmd\n",
			__FUNCTION__);
		return;
	}

	debug("Starting %s process...\n", __FUNCTION__);
#if !defined(CONFIG_SYS_HUSH_PARSER)
	ret = run_command (s, 0);
#else
	ret = parse_string_outer(s, FLAG_PARSE_SEMICOLON
				  | FLAG_EXIT_FROM_LOOP);
#endif
	if (ret < 0)
		debug("Error.. %s failed\n", __FUNCTION__);
	else
		debug("%s process finished\n", __FUNCTION__);
}

static void kw_sysrst_check(void)
{
	u32 sysrst_cnt, sysrst_dly;
	char *s;

	/*
	 * no action if sysrstdelay environment variable is not defined
	 */
	s = getenv("sysrstdelay");
	if (s == NULL)
		return;

	/* read sysrstdelay value */
	sysrst_dly = (u32) simple_strtoul(s, NULL, 10);

	/* read SysRst Length counter register (bits 28:0) */
	sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
	debug("H/w Rst hold time: %d.%d secs\n",
		sysrst_cnt / SYSRST_CNT_1SEC_VAL,
		sysrst_cnt % SYSRST_CNT_1SEC_VAL);

	/* clear the counter for next valid read*/
	writel(1 << 31, KW_REG_SYSRST_CNT);

	/*
	 * sysrst_action:
	 * if H/w Reset key is pressed and hold for time
	 * more than sysrst_dly in seconds
	 */
	if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
		kw_sysrst_action();
}

#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
	char *rev;
	u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
	u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;

	if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
		printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
		return -1;
	}

	switch (revid) {
	case 0:
		rev = "Z0";
		break;
	case 2:
		rev = "A0";
		break;
	case 3:
		rev = "A1";
		break;
	default:
		rev = "??";
		break;
	}

	printf("SoC:   Kirkwood 88F%04x_%s\n", devid, rev);
	return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */

#ifdef CONFIG_ARCH_CPU_INIT
int arch_cpu_init(void)
{
	u32 reg;
	struct kwcpu_registers *cpureg =
		(struct kwcpu_registers *)KW_CPU_REG_BASE;

	/* Linux expects` the internal registers to be at 0xf1000000 */
	writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);

	/* Enable and invalidate L2 cache in write through mode */
	writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
	invalidate_l2_cache();

	kw_config_adr_windows();

#ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
	/*
	 * Configures the I/O voltage of the pads connected to Egigabit
	 * Ethernet interface to 1.8V
	 * By defult it is set to 3.3V
	 */
	reg = readl(KW_REG_MPP_OUT_DRV_REG);
	reg |= (1 << 7);
	writel(reg, KW_REG_MPP_OUT_DRV_REG);
#endif
#ifdef CONFIG_KIRKWOOD_EGIGA_INIT
	/*
	 * Set egiga port0/1 in normal functional mode
	 * This is required becasue on kirkwood by default ports are in reset mode
	 * OS egiga driver may not have provision to set them in normal mode
	 * and if u-boot is build without network support, network may fail at OS level
	 */
	reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
	reg &= ~(1 << 4);	/* Clear PortReset Bit */
	writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
	reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
	reg &= ~(1 << 4);	/* Clear PortReset Bit */
	writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
#endif
#ifdef CONFIG_KIRKWOOD_PCIE_INIT
	/*
	 * Enable PCI Express Port0
	 */
	reg = readl(&cpureg->ctrl_stat);
	reg |= (1 << 0);	/* Set PEX0En Bit */
	writel(reg, &cpureg->ctrl_stat);
#endif
	return 0;
}
#endif /* CONFIG_ARCH_CPU_INIT */

/*
 * SOC specific misc init
 */
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
	volatile u32 temp;

	/*CPU streaming & write allocate */
	temp = readfr_extra_feature_reg();
	temp &= ~(1 << 28);	/* disable wr alloc */
	writefr_extra_feature_reg(temp);

	temp = readfr_extra_feature_reg();
	temp &= ~(1 << 29);	/* streaming disabled */
	writefr_extra_feature_reg(temp);

	/* L2Cache settings */
	temp = readfr_extra_feature_reg();
	/* Disable L2C pre fetch - Set bit 24 */
	temp |= (1 << 24);
	/* enable L2C - Set bit 22 */
	temp |= (1 << 22);
	writefr_extra_feature_reg(temp);

	icache_enable();
	/* Change reset vector to address 0x0 */
	temp = get_cr();
	set_cr(temp & ~CR_V);

	/* checks and execute resset to factory event */
	kw_sysrst_check();

	return 0;
}
#endif /* CONFIG_ARCH_MISC_INIT */

#ifdef CONFIG_MVGBE
int cpu_eth_init(bd_t *bis)
{
	mvgbe_initialize(bis);
	return 0;
}
#endif
Commit	Line	Data
4efb77d4 PW	1	/*
	2	* (C) Copyright 2009
	3	* Marvell Semiconductor <www.marvell.com>
	4	* Written-by: Prafulla Wadaskar <[email protected]>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	22	* MA 02110-1301 USA
	23	*/
	24
	25	#include <common.h>
	26	#include <netdev.h>
	27	#include <asm/cache.h>
	28	#include <u-boot/md5.h>
a7efd719 LW	29	#include <asm/io.h>
a7efd719 LW	30	#include <asm/arch/cpu.h>
4efb77d4	31	#include <asm/arch/kirkwood.h>
9df20ce2	32	#include <hush.h>
4efb77d4 PW	33
	34	#define BUFLEN 16
	35
	36	void reset_cpu(unsigned long ignored)
	37	{
	38	struct kwcpu_registers *cpureg =
	39	(struct kwcpu_registers *)KW_CPU_REG_BASE;
	40
	41	writel(readl(&cpureg->rstoutn_mask) \| (1 << 2),
	42	&cpureg->rstoutn_mask);
	43	writel(readl(&cpureg->sys_soft_rst) \| 1,
	44	&cpureg->sys_soft_rst);
	45	while (1) ;
	46	}
	47
	48	/*
	49	* Generates Ramdom hex number reading some time varient system registers
	50	* and using md5 algorithm
	51	*/
	52	unsigned char get_random_hex(void)
	53	{
	54	int i;
	55	u32 inbuf[BUFLEN];
	56	u8 outbuf[BUFLEN];
	57
	58	/*
c0cd0207	59	* in case of 88F6281/88F6282/88F6192 A0,
4efb77d4	60	* Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
c0cd0207 PW	61	* Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are
	62	* reserved regs and does not have names at this moment
	63	* (no errata available)
4efb77d4 PW	64	*/
	65	writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478);
	66	for (i = 0; i < BUFLEN; i++) {
	67	inbuf[i] = readl(KW_REG_UNDOC_0x1470);
	68	}
	69	md5((u8 ) inbuf, (BUFLEN sizeof(u32)), outbuf);
	70	return outbuf[outbuf[7] % 0x0f];
	71	}
	72
	73	/*
	74	* Window Size
	75	* Used with the Base register to set the address window size and location.
	76	* Must be programmed from LSB to MSB as sequence of ones followed by
	77	* sequence of zeros. The number of ones specifies the size of the window in
	78	* 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
	79	* NOTE: A value of 0x0 specifies 64-KByte size.
	80	*/
78eabb90	81	unsigned int kw_winctrl_calcsize(unsigned int sizeval)
4efb77d4 PW	82	{
	83	int i;
	84	unsigned int j = 0;
	85	u32 val = sizeval >> 1;
	86
f1060560	87	for (i = 0; val >= 0x10000; i++) {
4efb77d4 PW	88	j \|= (1 << i);
	89	val = val >> 1;
	90	}
	91	return (0x0000ffff & j);
	92	}
	93
4efb77d4 PW	94	/*
	95	* kw_config_adr_windows - Configure address Windows
	96	*
	97	* There are 8 address windows supported by Kirkwood Soc to addess different
	98	* devices. Each window can be configured for size, BAR and remap addr
	99	* Below configuration is standard for most of the cases
	100	*
	101	* If remap function not used, remap_lo must be set as base
	102	*
	103	* Reference Documentation:
	104	* Mbus-L to Mbus Bridge Registers Configuration.
	105	* (Sec 25.1 and 25.3 of Datasheet)
	106	*/
	107	int kw_config_adr_windows(void)
	108	{
	109	struct kwwin_registers *winregs =
	110	(struct kwwin_registers *)KW_CPU_WIN_BASE;
	111
	112	/* Window 0: PCIE MEM address space */
	113	writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
	114	KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
	115
	116	writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
	117	writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
	118	writel(0x0, &winregs[0].remap_hi);
	119
	120	/* Window 1: PCIE IO address space */
	121	writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
	122	KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
	123	writel(KW_DEFADR_PCI_IO, &winregs[1].base);
	124	writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
	125	writel(0x0, &winregs[1].remap_hi);
	126
	127	/* Window 2: NAND Flash address space */
	128	writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
	129	KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
	130	writel(KW_DEFADR_NANDF, &winregs[2].base);
	131	writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
	132	writel(0x0, &winregs[2].remap_hi);
	133
	134	/* Window 3: SPI Flash address space */
	135	writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
	136	KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
	137	writel(KW_DEFADR_SPIF, &winregs[3].base);
	138	writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
	139	writel(0x0, &winregs[3].remap_hi);
	140
	141	/* Window 4: BOOT Memory address space */
	142	writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
	143	KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
	144	writel(KW_DEFADR_BOOTROM, &winregs[4].base);
	145
	146	/* Window 5: Security SRAM address space */
	147	writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
	148	KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
	149	writel(KW_DEFADR_SASRAM, &winregs[5].base);
	150
	151	/* Window 6-7: Disabled */
	152	writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
	153	writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
	154
	155	return 0;
	156	}
	157
158	/*
159	* kw_config_gpio - GPIO configuration
160	*/
161	void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
162	{
163	struct kwgpio_registers *gpio0reg =
164	(struct kwgpio_registers *)KW_GPIO0_BASE;
165	struct kwgpio_registers *gpio1reg =
166	(struct kwgpio_registers *)KW_GPIO1_BASE;
167
168	/* Init GPIOS to default values as per board requirement */
169	writel(gpp0_oe_val, &gpio0reg->dout);
170	writel(gpp1_oe_val, &gpio1reg->dout);
171	writel(gpp0_oe, &gpio0reg->oe);
172	writel(gpp1_oe, &gpio1reg->oe);
173	}
174
175	/*
176	* kw_config_mpp - Multi-Purpose Pins Functionality configuration
177	*
178	* Each MPP can be configured to different functionality through
179	* MPP control register, ref (sec 6.1 of kirkwood h/w specification)
180	*
181	* There are maximum 64 Multi-Pourpose Pins on Kirkwood
182	* Each MPP functionality can be configuration by a 4bit value
183	* of MPP control reg, the value and associated functionality depends
184	* upon used SoC varient
185	*/
186	int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31,
187	u32 mpp32_39, u32 mpp40_47, u32 mpp48_55)
188	{
189	u32 mppreg = (u32 ) KW_MPP_BASE;
190
191	/* program mpp registers */
192	writel(mpp0_7, &mppreg[0]);
193	writel(mpp8_15, &mppreg[1]);
194	writel(mpp16_23, &mppreg[2]);
195	writel(mpp24_31, &mppreg[3]);
196	writel(mpp32_39, &mppreg[4]);
197	writel(mpp40_47, &mppreg[5]);
198	writel(mpp48_55, &mppreg[6]);
199	return 0;
200	}
201
49d2cb4d PW	202	/*
	203	* SYSRSTn Duration Counter Support
	204	*
	205	* Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
	206	* When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
	207	* The SYSRSTn duration counter is useful for implementing a manufacturer
	208	* or factory reset. Upon a long reset assertion that is greater than a
	209	* pre-configured environment variable value for sysrstdelay,
	210	* The counter value is stored in the SYSRSTn Length Counter Register
	211	* The counter is based on the 25-MHz reference clock (40ns)
	212	* It is a 29-bit counter, yielding a maximum counting duration of
	213	* 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
	214	* it remains at this value until counter reset is triggered by setting
	215	* bit 31 of KW_REG_SYSRST_CNT
	216	*/
	217	static void kw_sysrst_action(void)
	218	{
	219	int ret;
	220	char *s = getenv("sysrstcmd");
	221
	222	if (!s) {
	223	debug("Error.. %s failed, check sysrstcmd\n",
	224	__FUNCTION__);
	225	return;
	226	}
	227
	228	debug("Starting %s process...\n", __FUNCTION__);
	229	#if !defined(CONFIG_SYS_HUSH_PARSER)
	230	ret = run_command (s, 0);
	231	#else
	232	ret = parse_string_outer(s, FLAG_PARSE_SEMICOLON
	233	\| FLAG_EXIT_FROM_LOOP);
	234	#endif
	235	if (ret < 0)
	236	debug("Error.. %s failed\n", __FUNCTION__);
	237	else
	238	debug("%s process finished\n", __FUNCTION__);
	239	}
	240
	241	static void kw_sysrst_check(void)
	242	{
	243	u32 sysrst_cnt, sysrst_dly;
	244	char *s;
	245
	246	/*
	247	* no action if sysrstdelay environment variable is not defined
	248	*/
	249	s = getenv("sysrstdelay");
	250	if (s == NULL)
	251	return;
	252
	253	/* read sysrstdelay value */
	254	sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
	255
	256	/* read SysRst Length counter register (bits 28:0) */
	257	sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
	258	debug("H/w Rst hold time: %d.%d secs\n",
	259	sysrst_cnt / SYSRST_CNT_1SEC_VAL,
	260	sysrst_cnt % SYSRST_CNT_1SEC_VAL);
	261
	262	/* clear the counter for next valid read*/
	263	writel(1 << 31, KW_REG_SYSRST_CNT);
	264
	265	/*
266	* sysrst_action:
267	* if H/w Reset key is pressed and hold for time
268	* more than sysrst_dly in seconds
269	*/
270	if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
271	kw_sysrst_action();
272	}
273
4efb77d4 PW	274	#if defined(CONFIG_DISPLAY_CPUINFO)
	275	int print_cpuinfo(void)
	276	{
c0cd0207 PW	277	char *rev;
	278	u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
	279	u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
4efb77d4	280
c0cd0207 PW	281	if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
	282	printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
	283	return -1;
	284	}
	285
	286	switch (revid) {
	287	case 0:
	288	rev = "Z0";
4efb77d4 PW	289	break;
4efb77d4 PW	290	case 2:
c0cd0207 PW	291	rev = "A0";
	292	break;
	293	case 3:
	294	rev = "A1";
4efb77d4 PW	295	break;
4efb77d4 PW	296	default:
c0cd0207 PW	297	rev = "??";
c0cd0207 PW	298	break;
4efb77d4	299	}
c0cd0207 PW	300
c0cd0207 PW	301	printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev);
4efb77d4 PW	302	return 0;
	303	}
	304	#endif /* CONFIG_DISPLAY_CPUINFO */
	305
	306	#ifdef CONFIG_ARCH_CPU_INIT
	307	int arch_cpu_init(void)
	308	{
	309	u32 reg;
	310	struct kwcpu_registers *cpureg =
	311	(struct kwcpu_registers *)KW_CPU_REG_BASE;
	312
	313	/* Linux expects` the internal registers to be at 0xf1000000 */
	314	writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
	315
	316	/* Enable and invalidate L2 cache in write through mode */
	317	writel(readl(&cpureg->l2_cfg) \| 0x18, &cpureg->l2_cfg);
	318	invalidate_l2_cache();
	319
	320	kw_config_adr_windows();
	321
	322	#ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
	323	/*
	324	* Configures the I/O voltage of the pads connected to Egigabit
	325	* Ethernet interface to 1.8V
	326	* By defult it is set to 3.3V
	327	*/
	328	reg = readl(KW_REG_MPP_OUT_DRV_REG);
	329	reg \|= (1 << 7);
	330	writel(reg, KW_REG_MPP_OUT_DRV_REG);
	331	#endif
	332	#ifdef CONFIG_KIRKWOOD_EGIGA_INIT
	333	/*
	334	* Set egiga port0/1 in normal functional mode
	335	* This is required becasue on kirkwood by default ports are in reset mode
	336	* OS egiga driver may not have provision to set them in normal mode
	337	* and if u-boot is build without network support, network may fail at OS level
	338	*/
	339	reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
	340	reg &= ~(1 << 4); /* Clear PortReset Bit */
	341	writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
	342	reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
	343	reg &= ~(1 << 4); /* Clear PortReset Bit */
	344	writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
	345	#endif
	346	#ifdef CONFIG_KIRKWOOD_PCIE_INIT
	347	/*
	348	* Enable PCI Express Port0
	349	*/
	350	reg = readl(&cpureg->ctrl_stat);
	351	reg \|= (1 << 0); /* Set PEX0En Bit */
	352	writel(reg, &cpureg->ctrl_stat);
	353	#endif
	354	return 0;
	355	}
	356	#endif /* CONFIG_ARCH_CPU_INIT */
	357
	358	/*
	359	* SOC specific misc init
	360	*/
	361	#if defined(CONFIG_ARCH_MISC_INIT)
	362	int arch_misc_init(void)
	363	{
	364	volatile u32 temp;
	365
366	/CPU streaming & write allocate /
367	temp = readfr_extra_feature_reg();
368	temp &= ~(1 << 28); /* disable wr alloc */
369	writefr_extra_feature_reg(temp);
370
371	temp = readfr_extra_feature_reg();
372	temp &= ~(1 << 29); /* streaming disabled */
373	writefr_extra_feature_reg(temp);
374
375	/* L2Cache settings */
376	temp = readfr_extra_feature_reg();
377	/* Disable L2C pre fetch - Set bit 24 */
378	temp \|= (1 << 24);
379	/* enable L2C - Set bit 22 */
380	temp \|= (1 << 22);
381	writefr_extra_feature_reg(temp);
382
383	icache_enable();
384	/* Change reset vector to address 0x0 */
385	temp = get_cr();
386	set_cr(temp & ~CR_V);
387
49d2cb4d PW	388	/* checks and execute resset to factory event */
	389	kw_sysrst_check();
	390
4efb77d4 PW	391	return 0;
	392	}
	393	#endif /* CONFIG_ARCH_MISC_INIT */
	394
d44265ad	395	#ifdef CONFIG_MVGBE
4efb77d4 PW	396	int cpu_eth_init(bd_t *bis)
4efb77d4 PW	397	{
d44265ad	398	mvgbe_initialize(bis);
4efb77d4 PW	399	return 0;
	400	}
	401	#endif