[u-boot.git] / tools / mtk_nand_headers.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * MediaTek BootROM NAND header definitions
 *
 * Copyright (C) 2022 MediaTek Inc.
 * Author: Weijie Gao <[email protected]>
 */

#ifndef _MTK_NAND_HEADERS_H
#define _MTK_NAND_HEADERS_H

#include <stdint.h>
#include <stdbool.h>

struct nand_header_info {
	uint32_t page_size;
	uint32_t spare_size;
	uint32_t gfh_offset;
	bool snfi;
};

/* AP BROM Header for NAND */
union nand_boot_header {
	struct {
		char name[12];
		char version[4];
		char id[8];
		uint16_t ioif;			/* I/O interface */
		uint16_t pagesize;		/* NAND page size */
		uint16_t addrcycles;		/* Address cycles */
		uint16_t oobsize;		/* NAND page spare size */
		uint16_t pages_of_block;	/* Pages of one block */
		uint16_t numblocks;		/* Total blocks of NAND chip */
		uint16_t writesize_shift;
		uint16_t erasesize_shift;
		uint8_t dummy[60];
		uint8_t ecc_parity[28];		/* ECC parity of this header */
	};

	uint8_t data[0x80];
};

/* HSM BROM Header for NAND */
union hsm_nand_boot_header {
	struct {
		char id[8];
		uint32_t version;		/* Header version */
		uint32_t config;		/* Header config */
		uint32_t sector_size;		/* ECC step size */
		uint32_t fdm_size;		/* User OOB size of a step */
		uint32_t fdm_ecc_size;		/* ECC parity size of a step */
		uint32_t lbs;
		uint32_t page_size;		/* NAND page size */
		uint32_t spare_size;		/* NAND page spare size */
		uint32_t page_per_block;	/* Pages of one block */
		uint32_t blocks;		/* Total blocks of NAND chip */
		uint32_t plane_sel_position;	/* Plane bit position */
		uint32_t pll;			/* Value of pll reg */
		uint32_t acccon;		/* Value of access timing reg */
		uint32_t strobe_sel;		/* Value of DQS selection reg*/
		uint32_t acccon1;		/* Value of access timing reg */
		uint32_t dqs_mux;		/* Value of DQS mux reg */
		uint32_t dqs_ctrl;		/* Value of DQS control reg */
		uint32_t delay_ctrl;		/* Value of delay ctrl reg */
		uint32_t latch_lat;		/* Value of latch latency reg */
		uint32_t sample_delay;		/* Value of sample delay reg */
		uint32_t driving;		/* Value of driving reg */
		uint32_t bl_start;		/* Bootloader start addr */
		uint32_t bl_end;		/* Bootloader end addr */
		uint8_t ecc_parity[42];		/* ECC parity of this header */
	};

	uint8_t data[0x8E];
};

/* HSM2.0 BROM Header for NAND */
union hsm20_nand_boot_header {
	struct {
		char id[8];
		uint32_t version;		/* Header version */
		uint32_t config;		/* Header config */
		uint32_t sector_size;		/* ECC step size */
		uint32_t fdm_size;		/* User OOB size of a step */
		uint32_t fdm_ecc_size;		/* ECC parity size of a step */
		uint32_t lbs;
		uint32_t page_size;		/* NAND page size */
		uint32_t spare_size;		/* NAND page spare size */
		uint32_t page_per_block;	/* Pages of one block */
		uint32_t blocks;		/* Total blocks of NAND chip */
		uint32_t plane_sel_position;	/* Plane bit position */
		uint32_t pll;			/* Value of pll reg */
		uint32_t acccon;		/* Value of access timing reg */
		uint32_t strobe_sel;		/* Value of DQS selection reg*/
		uint32_t acccon1;		/* Value of access timing reg */
		uint32_t dqs_mux;		/* Value of DQS mux reg */
		uint32_t dqs_ctrl;		/* Value of DQS control reg */
		uint32_t delay_ctrl;		/* Value of delay ctrl reg */
		uint32_t latch_lat;		/* Value of latch latency reg */
		uint32_t sample_delay;		/* Value of sample delay reg */
		uint32_t driving;		/* Value of driving reg */
		uint32_t reserved;
		uint32_t bl0_start;		/* Bootloader start addr */
		uint32_t bl0_end;		/* Bootloader end addr */
		uint32_t bl0_type;		/* Bootloader type */
		uint8_t bl_reserve[84];
		uint8_t ecc_parity[42];		/* ECC parity of this header */
	};

	uint8_t data[0xEA];
};

/* SPIM BROM Header for SPI-NAND */
union spim_nand_boot_header {
	struct {
		char id[8];
		uint32_t version;		/* Header version */
		uint32_t config;		/* Header config */
		uint32_t page_size;		/* NAND page size */
		uint32_t spare_size;		/* NAND page spare size */
		uint16_t page_per_block;	/* Pages of one block */
		uint16_t plane_sel_position;	/* Plane bit position */
		uint16_t reserve_reg;
		uint16_t reserve_val;
		uint16_t ecc_error;		/* ECC error reg addr */
		uint16_t ecc_mask;		/* ECC error bit mask */
		uint32_t bl_start;		/* Bootloader start addr */
		uint32_t bl_end;		/* Bootloader end addr */
		uint8_t ecc_parity[32];		/* ECC parity of this header */
		uint32_t integrity_crc;		/* CRC of this header */
	};

	uint8_t data[0x50];
};

enum nand_boot_header_type {
	NAND_BOOT_AP_HEADER,
	NAND_BOOT_HSM_HEADER,
	NAND_BOOT_HSM20_HEADER,
	NAND_BOOT_SPIM_HEADER
};

#define NAND_BOOT_NAME		"BOOTLOADER!"
#define NAND_BOOT_VERSION	"V006"
#define NAND_BOOT_ID		"NFIINFO"

#define HSM_NAND_BOOT_NAME	"NANDCFG!"
#define SPIM_NAND_BOOT_NAME	"SPINAND!"

/* Find nand header data by name */
const struct nand_header_type *mtk_nand_header_find(const char *name);

/* Device header size using this nand header */
uint32_t mtk_nand_header_size(const struct nand_header_type *hdr_nand);

/* Get nand info from nand header (page size, spare size, ...) */
int mtk_nand_header_info(const void *ptr, struct nand_header_info *info);

/* Whether given header data is valid */
bool is_mtk_nand_header(const void *ptr);

/* Generate Device header using give nand header */
uint32_t mtk_nand_header_put(const struct nand_header_type *hdr_nand,
			     void *ptr);

#endif /* _MTK_NAND_HEADERS_H */
Commit	Line	Data
cadb1a85 WG	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* MediaTek BootROM NAND header definitions
	4	*
	5	* Copyright (C) 2022 MediaTek Inc.
	6	* Author: Weijie Gao <[email protected]>
	7	*/
	8
	9	#ifndef _MTK_NAND_HEADERS_H
	10	#define _MTK_NAND_HEADERS_H
	11
	12	#include <stdint.h>
	13	#include <stdbool.h>
	14
	15	struct nand_header_info {
	16	uint32_t page_size;
	17	uint32_t spare_size;
	18	uint32_t gfh_offset;
3e333213	19	bool snfi;
cadb1a85 WG	20	};
	21
	22	/* AP BROM Header for NAND */
	23	union nand_boot_header {
	24	struct {
	25	char name[12];
	26	char version[4];
	27	char id[8];
	28	uint16_t ioif; /* I/O interface */
	29	uint16_t pagesize; /* NAND page size */
	30	uint16_t addrcycles; /* Address cycles */
	31	uint16_t oobsize; /* NAND page spare size */
	32	uint16_t pages_of_block; /* Pages of one block */
	33	uint16_t numblocks; /* Total blocks of NAND chip */
	34	uint16_t writesize_shift;
	35	uint16_t erasesize_shift;
	36	uint8_t dummy[60];
	37	uint8_t ecc_parity[28]; /* ECC parity of this header */
	38	};
	39
	40	uint8_t data[0x80];
	41	};
	42
3e333213 WG	43	/* HSM BROM Header for NAND */
	44	union hsm_nand_boot_header {
	45	struct {
	46	char id[8];
	47	uint32_t version; /* Header version */
	48	uint32_t config; /* Header config */
	49	uint32_t sector_size; /* ECC step size */
	50	uint32_t fdm_size; /* User OOB size of a step */
	51	uint32_t fdm_ecc_size; /* ECC parity size of a step */
	52	uint32_t lbs;
	53	uint32_t page_size; /* NAND page size */
	54	uint32_t spare_size; /* NAND page spare size */
	55	uint32_t page_per_block; /* Pages of one block */
	56	uint32_t blocks; /* Total blocks of NAND chip */
	57	uint32_t plane_sel_position; /* Plane bit position */
	58	uint32_t pll; /* Value of pll reg */
	59	uint32_t acccon; /* Value of access timing reg */
	60	uint32_t strobe_sel; /* Value of DQS selection reg*/
	61	uint32_t acccon1; /* Value of access timing reg */
	62	uint32_t dqs_mux; /* Value of DQS mux reg */
	63	uint32_t dqs_ctrl; /* Value of DQS control reg */
	64	uint32_t delay_ctrl; /* Value of delay ctrl reg */
	65	uint32_t latch_lat; /* Value of latch latency reg */
	66	uint32_t sample_delay; /* Value of sample delay reg */
	67	uint32_t driving; /* Value of driving reg */
	68	uint32_t bl_start; /* Bootloader start addr */
	69	uint32_t bl_end; /* Bootloader end addr */
	70	uint8_t ecc_parity[42]; /* ECC parity of this header */
	71	};
	72
	73	uint8_t data[0x8E];
	74	};
	75
	76	/* HSM2.0 BROM Header for NAND */
	77	union hsm20_nand_boot_header {
	78	struct {
	79	char id[8];
	80	uint32_t version; /* Header version */
	81	uint32_t config; /* Header config */
	82	uint32_t sector_size; /* ECC step size */
	83	uint32_t fdm_size; /* User OOB size of a step */
	84	uint32_t fdm_ecc_size; /* ECC parity size of a step */
	85	uint32_t lbs;
	86	uint32_t page_size; /* NAND page size */
	87	uint32_t spare_size; /* NAND page spare size */
	88	uint32_t page_per_block; /* Pages of one block */
	89	uint32_t blocks; /* Total blocks of NAND chip */
	90	uint32_t plane_sel_position; /* Plane bit position */
	91	uint32_t pll; /* Value of pll reg */
	92	uint32_t acccon; /* Value of access timing reg */
	93	uint32_t strobe_sel; /* Value of DQS selection reg*/
	94	uint32_t acccon1; /* Value of access timing reg */
	95	uint32_t dqs_mux; /* Value of DQS mux reg */
	96	uint32_t dqs_ctrl; /* Value of DQS control reg */
	97	uint32_t delay_ctrl; /* Value of delay ctrl reg */
	98	uint32_t latch_lat; /* Value of latch latency reg */
	99	uint32_t sample_delay; /* Value of sample delay reg */
	100	uint32_t driving; /* Value of driving reg */
	101	uint32_t reserved;
	102	uint32_t bl0_start; /* Bootloader start addr */
	103	uint32_t bl0_end; /* Bootloader end addr */
	104	uint32_t bl0_type; /* Bootloader type */
	105	uint8_t bl_reserve[84];
	106	uint8_t ecc_parity[42]; /* ECC parity of this header */
107	};
108
109	uint8_t data[0xEA];
110	};
111
112	/* SPIM BROM Header for SPI-NAND */
113	union spim_nand_boot_header {
114	struct {
115	char id[8];
116	uint32_t version; /* Header version */
117	uint32_t config; /* Header config */
118	uint32_t page_size; /* NAND page size */
119	uint32_t spare_size; /* NAND page spare size */
120	uint16_t page_per_block; /* Pages of one block */
121	uint16_t plane_sel_position; /* Plane bit position */
122	uint16_t reserve_reg;
123	uint16_t reserve_val;
124	uint16_t ecc_error; /* ECC error reg addr */
125	uint16_t ecc_mask; /* ECC error bit mask */
126	uint32_t bl_start; /* Bootloader start addr */
127	uint32_t bl_end; /* Bootloader end addr */
128	uint8_t ecc_parity[32]; /* ECC parity of this header */
129	uint32_t integrity_crc; /* CRC of this header */
130	};
131
132	uint8_t data[0x50];
133	};
134
135	enum nand_boot_header_type {
136	NAND_BOOT_AP_HEADER,
137	NAND_BOOT_HSM_HEADER,
138	NAND_BOOT_HSM20_HEADER,
139	NAND_BOOT_SPIM_HEADER
140	};
141
cadb1a85 WG	142	#define NAND_BOOT_NAME "BOOTLOADER!"
	143	#define NAND_BOOT_VERSION "V006"
	144	#define NAND_BOOT_ID "NFIINFO"
	145
3e333213 WG	146	#define HSM_NAND_BOOT_NAME "NANDCFG!"
	147	#define SPIM_NAND_BOOT_NAME "SPINAND!"
	148
cadb1a85	149	/* Find nand header data by name */
3e333213	150	const struct nand_header_type mtk_nand_header_find(const char name);
cadb1a85 WG	151
cadb1a85 WG	152	/* Device header size using this nand header */
3e333213	153	uint32_t mtk_nand_header_size(const struct nand_header_type *hdr_nand);
cadb1a85 WG	154
	155	/* Get nand info from nand header (page size, spare size, ...) */
	156	int mtk_nand_header_info(const void ptr, struct nand_header_info info);
	157
	158	/* Whether given header data is valid */
	159	bool is_mtk_nand_header(const void *ptr);
	160
	161	/* Generate Device header using give nand header */
3e333213 WG	162	uint32_t mtk_nand_header_put(const struct nand_header_type *hdr_nand,
3e333213 WG	163	void *ptr);
cadb1a85 WG	164
cadb1a85 WG	165	#endif /* _MTK_NAND_HEADERS_H */