[u-boot.git] / include / configs / ti_armv7_keystone2.h

/*
 * Common configuration header file for all Keystone II EVM platforms
 *
 * (C) Copyright 2012-2014
 *     Texas Instruments Incorporated, <www.ti.com>
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#ifndef __CONFIG_KS2_EVM_H
#define __CONFIG_KS2_EVM_H

#define CONFIG_SOC_KEYSTONE

/* U-Boot Build Configuration */
#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 2nd stage loader */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_CPUINFO

/* SoC Configuration */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_ARCH_TIMER
#define CONFIG_SYS_TEXT_BASE		0x0c000000
#define CONFIG_SPL_TARGET		"u-boot-spi.gph"
#define CONFIG_SYS_DCACHE_OFF

/* Memory Configuration */
#define CONFIG_NR_DRAM_BANKS		2
#define CONFIG_SYS_LPAE_SDRAM_BASE	0x800000000
#define CONFIG_MAX_RAM_BANK_SIZE	(2 << 30)       /* 2GB */
#define CONFIG_STACKSIZE		(512 << 10)     /* 512 KiB */
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SPL_TEXT_BASE - \
					GENERATED_GBL_DATA_SIZE)

#ifdef CONFIG_SYS_MALLOC_F_LEN
#define SPL_MALLOC_F_SIZE	CONFIG_SYS_MALLOC_F_LEN
#else
#define SPL_MALLOC_F_SIZE	0
#endif

/* SPL SPI Loader Configuration */
#define CONFIG_SPL_PAD_TO		65536
#define CONFIG_SPL_MAX_SIZE		(CONFIG_SPL_PAD_TO - 8)
#define CONFIG_SPL_BSS_START_ADDR	(CONFIG_SPL_TEXT_BASE + \
					CONFIG_SPL_MAX_SIZE)
#define CONFIG_SPL_BSS_MAX_SIZE		(32 * 1024)
#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
					CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE	(32 * 1024)
#define CONFIG_SPL_STACK_SIZE		(8 * 1024)
#define CONFIG_SPL_STACK		(CONFIG_SYS_SPL_MALLOC_START + \
					CONFIG_SYS_SPL_MALLOC_SIZE + \
					SPL_MALLOC_F_SIZE + \
					CONFIG_SPL_STACK_SIZE - 4)
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS	CONFIG_SPL_PAD_TO

/* UART Configuration */
#define CONFIG_SYS_NS16550_MEM32
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#endif
#define CONFIG_SYS_NS16550_COM1		KS2_UART0_BASE
#define CONFIG_SYS_NS16550_COM2		KS2_UART1_BASE
#define CONFIG_CONS_INDEX		1

#ifndef CONFIG_SOC_K2G
#define CONFIG_SYS_NS16550_CLK		clk_get_rate(KS2_CLK1_6)
#else
#define CONFIG_SYS_NS16550_CLK		clk_get_rate(uart_pll_clk) / 2
#endif

/* SPI Configuration */
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_CLK		clk_get_rate(KS2_CLK1_6)
#define CONFIG_SF_DEFAULT_SPEED		30000000
#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
#define CONFIG_SYS_SPI0
#define CONFIG_SYS_SPI_BASE		KS2_SPI0_BASE
#define CONFIG_SYS_SPI0_NUM_CS		4
#define CONFIG_SYS_SPI1
#define CONFIG_SYS_SPI1_BASE		KS2_SPI1_BASE
#define CONFIG_SYS_SPI1_NUM_CS		4
#define CONFIG_SYS_SPI2
#define CONFIG_SYS_SPI2_BASE		KS2_SPI2_BASE
#define CONFIG_SYS_SPI2_NUM_CS		4

/* Network Configuration */
#define CONFIG_PHYLIB
#define CONFIG_PHY_MARVELL
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT		32
#define CONFIG_SYS_SGMII_REFCLK_MHZ	312
#define CONFIG_SYS_SGMII_LINERATE_MHZ	1250
#define CONFIG_SYS_SGMII_RATESCALE	2

/* Keyston Navigator Configuration */
#define CONFIG_TI_KSNAV
#define CONFIG_KSNAV_QM_BASE_ADDRESS		KS2_QM_BASE_ADDRESS
#define CONFIG_KSNAV_QM_CONF_BASE		KS2_QM_CONF_BASE
#define CONFIG_KSNAV_QM_DESC_SETUP_BASE		KS2_QM_DESC_SETUP_BASE
#define CONFIG_KSNAV_QM_STATUS_RAM_BASE		KS2_QM_STATUS_RAM_BASE
#define CONFIG_KSNAV_QM_INTD_CONF_BASE		KS2_QM_INTD_CONF_BASE
#define CONFIG_KSNAV_QM_PDSP1_CMD_BASE		KS2_QM_PDSP1_CMD_BASE
#define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE		KS2_QM_PDSP1_CTRL_BASE
#define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE		KS2_QM_PDSP1_IRAM_BASE
#define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE	KS2_QM_MANAGER_QUEUES_BASE
#define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE	KS2_QM_MANAGER_Q_PROXY_BASE
#define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE	KS2_QM_QUEUE_STATUS_BASE
#define CONFIG_KSNAV_QM_LINK_RAM_BASE		KS2_QM_LINK_RAM_BASE
#define CONFIG_KSNAV_QM_REGION_NUM		KS2_QM_REGION_NUM
#define CONFIG_KSNAV_QM_QPOOL_NUM		KS2_QM_QPOOL_NUM

/* NETCP pktdma */
#define CONFIG_KSNAV_PKTDMA_NETCP
#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE	KS2_NETCP_PDMA_CTRL_BASE
#define CONFIG_KSNAV_NETCP_PDMA_TX_BASE		KS2_NETCP_PDMA_TX_BASE
#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM	KS2_NETCP_PDMA_TX_CH_NUM
#define CONFIG_KSNAV_NETCP_PDMA_RX_BASE		KS2_NETCP_PDMA_RX_BASE
#define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM	KS2_NETCP_PDMA_RX_CH_NUM
#define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE	KS2_NETCP_PDMA_SCHED_BASE
#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE	KS2_NETCP_PDMA_RX_FLOW_BASE
#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM	KS2_NETCP_PDMA_RX_FLOW_NUM
#define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE	KS2_NETCP_PDMA_RX_FREE_QUEUE
#define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE	KS2_NETCP_PDMA_RX_RCV_QUEUE
#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE	KS2_NETCP_PDMA_TX_SND_QUEUE

/* Keystone net */
#define CONFIG_DRIVER_TI_KEYSTONE_NET
#define CONFIG_KSNET_MAC_ID_BASE		KS2_MAC_ID_BASE_ADDR
#define CONFIG_KSNET_NETCP_BASE			KS2_NETCP_BASE
#define CONFIG_KSNET_SERDES_SGMII_BASE		KS2_SGMII_SERDES_BASE
#define CONFIG_KSNET_SERDES_SGMII2_BASE		KS2_SGMII_SERDES2_BASE
#define CONFIG_KSNET_SERDES_LANES_PER_SGMII	KS2_LANES_PER_SGMII_SERDES

/* SerDes */
#define CONFIG_TI_KEYSTONE_SERDES

/* AEMIF */
#define CONFIG_TI_AEMIF
#define CONFIG_AEMIF_CNTRL_BASE		KS2_AEMIF_CNTRL_BASE

/* I2C Configuration */
#define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_DAVINCI_I2C_SPEED	100000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE	0x10 /* SMBus host address */
#define CONFIG_SYS_DAVINCI_I2C_SPEED1	100000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE1	0x10 /* SMBus host address */
#define CONFIG_SYS_DAVINCI_I2C_SPEED2	100000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE2	0x10 /* SMBus host address */
#define I2C_BUS_MAX			3

/* EEPROM definitions */
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
#define CONFIG_ENV_EEPROM_IS_ON_I2C

/* NAND Configuration */
#define CONFIG_NAND_DAVINCI
#define CONFIG_KEYSTONE_RBL_NAND
#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE	CONFIG_ENV_OFFSET
#define CONFIG_SYS_NAND_MASK_CLE		0x4000
#define CONFIG_SYS_NAND_MASK_ALE		0x2000
#define CONFIG_SYS_NAND_CS			2
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST

#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_BASE_LIST		{ 0x30000000, }
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_MAX_CHIPS		1
#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
#define CONFIG_ENV_SIZE				(256 << 10)  /* 256 KiB */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET			0x100000
#define CONFIG_MTD_PARTITIONS
#define CONFIG_RBTREE
#define CONFIG_LZO
#define MTDIDS_DEFAULT			"nand0=davinci_nand.0"
#define MTDPARTS_DEFAULT		"mtdparts=davinci_nand.0:" \
					"1024k(bootloader)ro,512k(params)ro," \
					"-(ubifs)"

/* USB Configuration */
#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI_KEYSTONE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
#define CONFIG_EFI_PARTITION
#define CONFIG_FS_FAT
#define CONFIG_SYS_CACHELINE_SIZE		64
#define CONFIG_USB_SS_BASE			KS2_USB_SS_BASE
#define CONFIG_USB_HOST_XHCI_BASE		KS2_USB_HOST_XHCI_BASE
#define CONFIG_DEV_USB_PHY_BASE			KS2_DEV_USB_PHY_BASE
#define CONFIG_USB_PHY_CFG_BASE			KS2_USB_PHY_CFG_BASE

/* U-Boot command configuration */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_NAND
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_SF
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_USB

/* U-Boot general configuration */
#define CONFIG_MISC_INIT_R
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
#define CONFIG_TIMESTAMP

/* EDMA3 */
#define CONFIG_TI_EDMA3

#define CONFIG_EXTRA_ENV_SETTINGS					\
	DEFAULT_LINUX_BOOT_ENV						\
	CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS				\
	"boot=ubi\0"							\
	"tftp_root=/\0"							\
	"nfs_root=/export\0"						\
	"mem_lpae=1\0"							\
	"mem_reserve=512M\0"						\
	"addr_ubi=0x82000000\0"						\
	"addr_secdb_key=0xc000000\0"					\
	"name_kern=zImage\0"						\
	"run_mon=mon_install ${addr_mon}\0"				\
	"run_kern=bootz ${loadaddr} - ${fdtaddr}\0"			\
	"init_net=run args_all args_net\0"				\
	"init_ubi=run args_all args_ubi; "				\
		"ubi part ubifs; ubifsmount ubi:boot;"			\
		"ubifsload ${addr_secdb_key} securedb.key.bin;\0"       \
	"get_fdt_net=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0"	\
	"get_fdt_ubi=ubifsload ${fdtaddr} ${name_fdt}\0"		\
	"get_kern_net=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0"	\
	"get_kern_ubi=ubifsload ${loadaddr} ${name_kern}\0"		\
	"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0"	\
	"get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0"		\
	"get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0"	\
	"burn_uboot_spi=sf probe; sf erase 0 0x100000; "		\
		"sf write ${loadaddr} 0 ${filesize}\0"		\
	"burn_uboot_nand=nand erase 0 0x100000; "			\
		"nand write ${loadaddr} 0 ${filesize}\0"		\
	"args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0"	\
	"args_net=setenv bootargs ${bootargs} rootfstype=nfs "		\
		"root=/dev/nfs rw nfsroot=${serverip}:${nfs_root},"	\
		"${nfs_options} ip=dhcp\0"				\
	"nfs_options=v3,tcp,rsize=4096,wsize=4096\0"			\
	"get_fdt_ramfs=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0"	\
	"get_kern_ramfs=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0"	\
	"get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0"	\
	"get_fs_ramfs=dhcp ${rdaddr} ${tftp_root}/${name_fs}\0"	\
	"get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0"	\
	"burn_ubi=nand erase.part ubifs; "				\
		"nand write ${addr_ubi} ubifs ${filesize}\0"		\
	"init_ramfs=run args_all args_ramfs get_fs_ramfs\0"		\
	"args_ramfs=setenv bootargs ${bootargs} "			\
		"rdinit=/sbin/init rw root=/dev/ram0 "			\
		"initrd=0x808080000,80M\0"				\
	"no_post=1\0"							\
	"mtdparts=mtdparts=davinci_nand.0:"				\
		"1024k(bootloader)ro,512k(params)ro,-(ubifs)\0"

#define CONFIG_BOOTCOMMAND						\
	"run init_${boot} get_fdt_${boot} get_mon_${boot} "		\
		"get_kern_${boot} run_mon run_kern"

#define CONFIG_BOOTARGS							\

/* Linux interfacing */
#define CONFIG_OF_BOARD_SETUP

/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>

/* We wont be loading up OS from SPL for now.. */
#undef CONFIG_SPL_OS_BOOT

/* We do not have MMC support.. yet.. */
#undef CONFIG_SPL_LIBDISK_SUPPORT
#undef CONFIG_SPL_MMC_SUPPORT
#undef CONFIG_SPL_FAT_SUPPORT
#undef CONFIG_SPL_EXT_SUPPORT
#undef CONFIG_MMC
#undef CONFIG_GENERIC_MMC
#undef CONFIG_CMD_MMC

/* And no support for GPIO, yet.. */
#undef CONFIG_SPL_GPIO_SUPPORT

/* we may include files below only after all above definitions */
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#ifndef CONFIG_SOC_K2G
#define CONFIG_SYS_HZ_CLOCK		clk_get_rate(KS2_CLK1_6)
#else
#define CONFIG_SYS_HZ_CLOCK		external_clk[sys_clk]
#endif

#endif /* __CONFIG_KS2_EVM_H */
Commit	Line	Data
2221cd12 HZ	1	/*
	2	* Common configuration header file for all Keystone II EVM platforms
	3	*
	4	* (C) Copyright 2012-2014
	5	* Texas Instruments Incorporated, <www.ti.com>
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
	10	#ifndef __CONFIG_KS2_EVM_H
	11	#define __CONFIG_KS2_EVM_H
	12
	13	#define CONFIG_SOC_KEYSTONE
	14
	15	/* U-Boot Build Configuration */
	16	#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */
2221cd12	17	#define CONFIG_BOARD_EARLY_INIT_F
aeabe652	18	#define CONFIG_DISPLAY_CPUINFO
2221cd12 HZ	19
2221cd12 HZ	20	/* SoC Configuration */
2221cd12 HZ	21	#define CONFIG_ARCH_CPU_INIT
2221cd12 HZ	22	#define CONFIG_SYS_ARCH_TIMER
401f2d91	23	#define CONFIG_SYS_TEXT_BASE 0x0c000000
2221cd12 HZ	24	#define CONFIG_SPL_TARGET "u-boot-spi.gph"
	25	#define CONFIG_SYS_DCACHE_OFF
	26
	27	/* Memory Configuration */
	28	#define CONFIG_NR_DRAM_BANKS 2
2221cd12 HZ	29	#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000
	30	#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */
	31	#define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */
401f2d91	32	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE - \
2221cd12 HZ	33	GENERATED_GBL_DATA_SIZE)
2221cd12 HZ	34
aaf461f9 LV	35	#ifdef CONFIG_SYS_MALLOC_F_LEN
	36	#define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN
	37	#else
	38	#define SPL_MALLOC_F_SIZE 0
	39	#endif
	40
2221cd12 HZ	41	/* SPL SPI Loader Configuration */
	42	#define CONFIG_SPL_PAD_TO 65536
	43	#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8)
	44	#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \
	45	CONFIG_SPL_MAX_SIZE)
	46	#define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024)
	47	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
	48	CONFIG_SPL_BSS_MAX_SIZE)
	49	#define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024)
	50	#define CONFIG_SPL_STACK_SIZE (8 * 1024)
	51	#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \
	52	CONFIG_SYS_SPL_MALLOC_SIZE + \
aaf461f9	53	SPL_MALLOC_F_SIZE + \
2221cd12	54	CONFIG_SPL_STACK_SIZE - 4)
2221cd12 HZ	55	#define CONFIG_SPL_SPI_FLASH_SUPPORT
2221cd12 HZ	56	#define CONFIG_SPL_SPI_SUPPORT
2221cd12	57	#define CONFIG_SPL_SPI_LOAD
2221cd12	58	#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
2221cd12 HZ	59
2221cd12 HZ	60	/* UART Configuration */
2221cd12	61	#define CONFIG_SYS_NS16550_MEM32
391839fb LV	62	#if defined(CONFIG_SPL_BUILD) \|\| !defined(CONFIG_DM_SERIAL)
391839fb LV	63	#define CONFIG_SYS_NS16550_SERIAL
2221cd12	64	#define CONFIG_SYS_NS16550_REG_SIZE -4
391839fb	65	#endif
2221cd12 HZ	66	#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
2221cd12 HZ	67	#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
2221cd12	68	#define CONFIG_CONS_INDEX 1
2221cd12	69
e6d71e1c VA	70	#ifndef CONFIG_SOC_K2G
	71	#define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6)
	72	#else
	73	#define CONFIG_SYS_NS16550_CLK clk_get_rate(uart_pll_clk) / 2
	74	#endif
	75
2221cd12	76	/* SPI Configuration */
2221cd12 HZ	77	#define CONFIG_SPI_FLASH_STMICRO
2221cd12 HZ	78	#define CONFIG_DAVINCI_SPI
4dca7f0a	79	#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6)
2221cd12 HZ	80	#define CONFIG_SF_DEFAULT_SPEED 30000000
	81	#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	82	#define CONFIG_SYS_SPI0
	83	#define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE
	84	#define CONFIG_SYS_SPI0_NUM_CS 4
	85	#define CONFIG_SYS_SPI1
	86	#define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE
	87	#define CONFIG_SYS_SPI1_NUM_CS 4
	88	#define CONFIG_SYS_SPI2
	89	#define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE
	90	#define CONFIG_SYS_SPI2_NUM_CS 4
	91
	92	/* Network Configuration */
3fe93623 KI	93	#define CONFIG_PHYLIB
3fe93623 KI	94	#define CONFIG_PHY_MARVELL
2221cd12 HZ	95	#define CONFIG_MII
	96	#define CONFIG_BOOTP_DEFAULT
	97	#define CONFIG_BOOTP_DNS
	98	#define CONFIG_BOOTP_DNS2
	99	#define CONFIG_BOOTP_SEND_HOSTNAME
	100	#define CONFIG_NET_RETRY_COUNT 32
2221cd12 HZ	101	#define CONFIG_SYS_SGMII_REFCLK_MHZ 312
	102	#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250
	103	#define CONFIG_SYS_SGMII_RATESCALE 2
	104
ef454717	105	/* Keyston Navigator Configuration */
796bcee6	106	#define CONFIG_TI_KSNAV
ef454717 KI	107	#define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS
	108	#define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE
	109	#define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE
	110	#define CONFIG_KSNAV_QM_STATUS_RAM_BASE KS2_QM_STATUS_RAM_BASE
	111	#define CONFIG_KSNAV_QM_INTD_CONF_BASE KS2_QM_INTD_CONF_BASE
	112	#define CONFIG_KSNAV_QM_PDSP1_CMD_BASE KS2_QM_PDSP1_CMD_BASE
	113	#define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE KS2_QM_PDSP1_CTRL_BASE
	114	#define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE KS2_QM_PDSP1_IRAM_BASE
	115	#define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE KS2_QM_MANAGER_QUEUES_BASE
	116	#define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE KS2_QM_MANAGER_Q_PROXY_BASE
	117	#define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE KS2_QM_QUEUE_STATUS_BASE
	118	#define CONFIG_KSNAV_QM_LINK_RAM_BASE KS2_QM_LINK_RAM_BASE
	119	#define CONFIG_KSNAV_QM_REGION_NUM KS2_QM_REGION_NUM
	120	#define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM
	121
	122	/* NETCP pktdma */
796bcee6	123	#define CONFIG_KSNAV_PKTDMA_NETCP
ef454717 KI	124	#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE
	125	#define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE
	126	#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM
	127	#define CONFIG_KSNAV_NETCP_PDMA_RX_BASE KS2_NETCP_PDMA_RX_BASE
	128	#define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM KS2_NETCP_PDMA_RX_CH_NUM
	129	#define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE KS2_NETCP_PDMA_SCHED_BASE
	130	#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE KS2_NETCP_PDMA_RX_FLOW_BASE
	131	#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM KS2_NETCP_PDMA_RX_FLOW_NUM
	132	#define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE KS2_NETCP_PDMA_RX_FREE_QUEUE
	133	#define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE
	134	#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE
	135
0935cac6	136	/* Keystone net */
796bcee6	137	#define CONFIG_DRIVER_TI_KEYSTONE_NET
92a16c81 HZ	138	#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR
	139	#define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE
	140	#define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE
3c61502a	141	#define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE
92a16c81	142	#define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES
0935cac6	143
87ac27bd KI	144	/* SerDes */
	145	#define CONFIG_TI_KEYSTONE_SERDES
	146
2221cd12 HZ	147	/* AEMIF */
	148	#define CONFIG_TI_AEMIF
	149	#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
	150
	151	/* I2C Configuration */
2221cd12 HZ	152	#define CONFIG_SYS_I2C_DAVINCI
	153	#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000
	154	#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
	155	#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000
	156	#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */
	157	#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000
	158	#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */
	159	#define I2C_BUS_MAX 3
	160
	161	/* EEPROM definitions */
	162	#define CONFIG_SYS_I2C_MULTI_EEPROMS
	163	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	164	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	165	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
	166	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
	167	#define CONFIG_ENV_EEPROM_IS_ON_I2C
	168
	169	/* NAND Configuration */
	170	#define CONFIG_NAND_DAVINCI
	171	#define CONFIG_KEYSTONE_RBL_NAND
	172	#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET
	173	#define CONFIG_SYS_NAND_MASK_CLE 0x4000
	174	#define CONFIG_SYS_NAND_MASK_ALE 0x2000
	175	#define CONFIG_SYS_NAND_CS 2
	176	#define CONFIG_SYS_NAND_USE_FLASH_BBT
	177	#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
	178
	179	#define CONFIG_SYS_NAND_LARGEPAGE
	180	#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, }
	181	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	182	#define CONFIG_SYS_NAND_MAX_CHIPS 1
	183	#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
	184	#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
	185	#define CONFIG_ENV_IS_IN_NAND
	186	#define CONFIG_ENV_OFFSET 0x100000
	187	#define CONFIG_MTD_PARTITIONS
2221cd12 HZ	188	#define CONFIG_RBTREE
	189	#define CONFIG_LZO
	190	#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
	191	#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \
	192	"1024k(bootloader)ro,512k(params)ro," \
	193	"-(ubifs)"
	194
bc0e8d7c WK	195	/* USB Configuration */
bc0e8d7c WK	196	#define CONFIG_USB_XHCI
792651f0	197	#define CONFIG_USB_XHCI_DWC3
bc0e8d7c WK	198	#define CONFIG_USB_XHCI_KEYSTONE
bc0e8d7c WK	199	#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
bc0e8d7c WK	200	#define CONFIG_EFI_PARTITION
	201	#define CONFIG_FS_FAT
	202	#define CONFIG_SYS_CACHELINE_SIZE 64
	203	#define CONFIG_USB_SS_BASE KS2_USB_SS_BASE
	204	#define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE
	205	#define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE
	206	#define CONFIG_USB_PHY_CFG_BASE KS2_USB_PHY_CFG_BASE
	207
2221cd12	208	/* U-Boot command configuration */
2221cd12	209	#define CONFIG_CMD_DHCP
2221cd12 HZ	210	#define CONFIG_CMD_PING
2221cd12 HZ	211	#define CONFIG_CMD_SAVES
2221cd12 HZ	212	#define CONFIG_CMD_NAND
	213	#define CONFIG_CMD_UBI
	214	#define CONFIG_CMD_UBIFS
	215	#define CONFIG_CMD_SF
	216	#define CONFIG_CMD_EEPROM
bc0e8d7c	217	#define CONFIG_CMD_USB
2221cd12 HZ	218
2221cd12 HZ	219	/* U-Boot general configuration */
8347210a	220	#define CONFIG_MISC_INIT_R
2221cd12 HZ	221	#define CONFIG_CRC32_VERIFY
2221cd12 HZ	222	#define CONFIG_MX_CYCLIC
2221cd12 HZ	223	#define CONFIG_TIMESTAMP
	224
	225	/* EDMA3 */
	226	#define CONFIG_TI_EDMA3
	227
2221cd12	228	#define CONFIG_EXTRA_ENV_SETTINGS \
fd72d318	229	DEFAULT_LINUX_BOOT_ENV \
349c26dd	230	CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
b7d9f9ca	231	"boot=ubi\0" \
2221cd12 HZ	232	"tftp_root=/\0" \
	233	"nfs_root=/export\0" \
	234	"mem_lpae=1\0" \
	235	"mem_reserve=512M\0" \
2221cd12 HZ	236	"addr_ubi=0x82000000\0" \
2221cd12 HZ	237	"addr_secdb_key=0xc000000\0" \
bad773f4	238	"name_kern=zImage\0" \
2221cd12	239	"run_mon=mon_install ${addr_mon}\0" \
bad773f4	240	"run_kern=bootz ${loadaddr} - ${fdtaddr}\0" \
2221cd12 HZ	241	"init_net=run args_all args_net\0" \
2221cd12 HZ	242	"init_ubi=run args_all args_ubi; " \
ff52e3b4	243	"ubi part ubifs; ubifsmount ubi:boot;" \
2221cd12	244	"ubifsload ${addr_secdb_key} securedb.key.bin;\0" \
fd72d318 NM	245	"get_fdt_net=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \
	246	"get_fdt_ubi=ubifsload ${fdtaddr} ${name_fdt}\0" \
	247	"get_kern_net=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \
	248	"get_kern_ubi=ubifsload ${loadaddr} ${name_kern}\0" \
2221cd12 HZ	249	"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
2221cd12 HZ	250	"get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \
8889e984	251	"get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \
2221cd12	252	"burn_uboot_spi=sf probe; sf erase 0 0x100000; " \
8889e984	253	"sf write ${loadaddr} 0 ${filesize}\0" \
2221cd12	254	"burn_uboot_nand=nand erase 0 0x100000; " \
8889e984	255	"nand write ${loadaddr} 0 ${filesize}\0" \
2221cd12	256	"args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \
2221cd12 HZ	257	"args_net=setenv bootargs ${bootargs} rootfstype=nfs " \
	258	"root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \
	259	"${nfs_options} ip=dhcp\0" \
	260	"nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \
fd72d318 NM	261	"get_fdt_ramfs=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \
fd72d318 NM	262	"get_kern_ramfs=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \
2221cd12	263	"get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
fd72d318	264	"get_fs_ramfs=dhcp ${rdaddr} ${tftp_root}/${name_fs}\0" \
2221cd12 HZ	265	"get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \
	266	"burn_ubi=nand erase.part ubifs; " \
	267	"nand write ${addr_ubi} ubifs ${filesize}\0" \
	268	"init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \
	269	"args_ramfs=setenv bootargs ${bootargs} " \
	270	"rdinit=/sbin/init rw root=/dev/ram0 " \
f06b454b	271	"initrd=0x808080000,80M\0" \
2221cd12 HZ	272	"no_post=1\0" \
	273	"mtdparts=mtdparts=davinci_nand.0:" \
	274	"1024k(bootloader)ro,512k(params)ro,-(ubifs)\0"
	275
	276	#define CONFIG_BOOTCOMMAND \
	277	"run init_${boot} get_fdt_${boot} get_mon_${boot} " \
	278	"get_kern_${boot} run_mon run_kern"
	279
	280	#define CONFIG_BOOTARGS \
	281
	282	/* Linux interfacing */
2221cd12	283	#define CONFIG_OF_BOARD_SETUP
2221cd12	284
e07cff11 NM	285	/* Now for the remaining common defines */
	286	#include <configs/ti_armv7_common.h>
	287
	288	/* We wont be loading up OS from SPL for now.. */
	289	#undef CONFIG_SPL_OS_BOOT
	290
	291	/* We do not have MMC support.. yet.. */
	292	#undef CONFIG_SPL_LIBDISK_SUPPORT
	293	#undef CONFIG_SPL_MMC_SUPPORT
	294	#undef CONFIG_SPL_FAT_SUPPORT
	295	#undef CONFIG_SPL_EXT_SUPPORT
	296	#undef CONFIG_MMC
	297	#undef CONFIG_GENERIC_MMC
	298	#undef CONFIG_CMD_MMC
	299
	300	/* And no support for GPIO, yet.. */
	301	#undef CONFIG_SPL_GPIO_SUPPORT
2221cd12 HZ	302
	303	/* we may include files below only after all above definitions */
	304	#include <asm/arch/hardware.h>
	305	#include <asm/arch/clock.h>
e6d71e1c	306	#ifndef CONFIG_SOC_K2G
2221cd12	307	#define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6)
e6d71e1c VA	308	#else
	309	#define CONFIG_SYS_HZ_CLOCK external_clk[sys_clk]
	310	#endif
2221cd12	311
2221cd12	312	#endif /* __CONFIG_KS2_EVM_H */