[u-boot.git] / board / omap5912osk / lowlevel_init.S

/*
 * Board specific setup info
 *
 * (C) Copyright 2003
 * Texas Instruments, <www.ti.com>
 * Kshitij Gupta <[email protected]>
 *
 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
 *
 * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <version.h>

#if defined(CONFIG_OMAP1610)
#include <./configs/omap1510.h>
#endif


_TEXT_BASE:
	.word	TEXT_BASE	/* sdram load addr from config.mk */

.globl lowlevel_init
lowlevel_init:

	/*------------------------------------------------------*
	 * Ensure i-cache is enabled                            *
	 * To configure TC regs without fetching instruction    *
	 *------------------------------------------------------*/
	mrc	p15, 0, r0, c1, c0
	orr	r0, r0, #0x1000
	mcr	p15, 0, r0, c1, c0

	/*------------------------------------------------------*
	 *mask all IRQs by setting all bits in the INTMR default*
	 *------------------------------------------------------*/
	mov	r1, #0xffffffff
	ldr	r0, =REG_IHL1_MIR
	str	r1, [r0]
	ldr	r0, =REG_IHL2_MIR
	str	r1, [r0]

	/*------------------------------------------------------*
	 * Set up ARM CLM registers (IDLECT1)                   *
	 *------------------------------------------------------*/
	ldr	r0,	REG_ARM_IDLECT1
	ldr	r1,	VAL_ARM_IDLECT1
	str	r1,	[r0]

	/*------------------------------------------------------*
	 * Set up ARM CLM registers (IDLECT2)                   *
	 *------------------------------------------------------*/
	ldr	r0,	REG_ARM_IDLECT2
	ldr	r1,	VAL_ARM_IDLECT2
	str	r1,	[r0]

	/*------------------------------------------------------*
	 * Set up ARM CLM registers (IDLECT3)                   *
	 *------------------------------------------------------*/
	ldr	r0,	REG_ARM_IDLECT3
	ldr	r1,	VAL_ARM_IDLECT3
	str	r1,	[r0]

	mov	r1,	#0x01               /* PER_EN bit */
	ldr	r0,	REG_ARM_RSTCT2
	strh	r1,	[r0]            /* CLKM; Peripheral reset. */

	/* Set CLKM to Sync-Scalable */
	mov	r1,	#0x1000
	ldr	r0,	REG_ARM_SYSST

	mov	r2,	#0
1:	cmp	r2,	#1
	streqh	r1,	[r0]
	add	r2,	r2,	#1
	cmp	r2,	#0x100              /* wait for any bubbles to finish */
	bne	1b

	ldr	r1,	VAL_ARM_CKCTL
	ldr	r0,	REG_ARM_CKCTL
	strh	r1,	[r0]

	/* a few nops to let settle */
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop

	/* setup DPLL 1 */
	/* Ramp up the clock to 96Mhz */
	ldr	r1,	VAL_DPLL1_CTL
	ldr	r0,	REG_DPLL1_CTL
	strh	r1,	[r0]
	ands	r1,	r1,	#0x10       /* Check if PLL is enabled. */
	beq	lock_end                /* Do not look for lock if BYPASS selected */
2:
	ldrh	r1,	[r0]
	ands	r1,	r1,	#0x01       /* Check the LOCK bit.*/
	beq 2b                      /* loop until bit goes hi. */
lock_end:

	/*------------------------------------------------------*
	 * Turn off the watchdog during init...                 *
 	 *------------------------------------------------------*/
	ldr	r0,	REG_WATCHDOG
	ldr	r1,	WATCHDOG_VAL1
	str	r1,	[r0]
	ldr	r1,	WATCHDOG_VAL2
	str	r1,	[r0]
	ldr	r0,	REG_WSPRDOG
	ldr	r1,	WSPRDOG_VAL1
	str	r1,	[r0]
	ldr	r0,	REG_WWPSDOG

watch1Wait:
	ldr	r1,	[r0]
	tst	r1,	#0x10
	bne	watch1Wait

	ldr	r0,	REG_WSPRDOG
	ldr	r1,	WSPRDOG_VAL2
	str	r1,	[r0]
	ldr	r0,	REG_WWPSDOG
watch2Wait:
	ldr	r1,	[r0]
	tst	r1,	#0x10
	bne	watch2Wait

	/* Set memory timings corresponding to the new clock speed */
	ldr	r3, VAL_SDRAM_CONFIG_SDF0

	/* Check execution location to determine current execution location
	 * and branch to appropriate initialization code.
	 */
	mov	r0,	#0x10000000         /* Load physical SDRAM base. */
	mov	r1,	pc                  /* Get current execution location. */
	cmp	r1,	r0                  /* Compare. */
	bge	skip_sdram              /* Skip over EMIF-fast initialization if running from SDRAM. */

	/* identify the device revision, -- TMX or TMP(TMS) */
	ldr	r0, REG_DEVICE_ID
	ldr	r1, [r0]

	ldr	r0, VAL_DEVICE_ID_TMP
	mov	r1, r1, lsl #15
	mov	r1, r1, lsr #16
	cmp	r0, r1
	bne	skip_TMP_Patch

	/* Enable TMP/TMS device new features */
	mov	r0, #1
	ldr	r1, REG_TC_EMIFF_DOUBLER
	str	r0, [r1]

	/* Enable new ac parameters */
	mov	r0, #0x0b
	ldr	r1, REG_SDRAM_CONFIG2
	str	r0, [r1]

	ldr	r3, VAL_SDRAM_CONFIG_SDF1

skip_TMP_Patch:

	/*
	* Delay for SDRAM initialization.
	*/
	mov	r0,	#0x1800		/* value should be checked */
3:
	subs	r0,	r0,	#0x1	/* Decrement count */
	bne 	3b

	/*
	 * Set SDRAM control values. Disable refresh before MRS command.
	 */

	/* mobile ddr operation */
	ldr	r0,	REG_SDRAM_OPERATION
	mov	r2,	#07
	str	r2,	[r0]

	/* config register */
	ldr	r0,	REG_SDRAM_CONFIG
	str	r3,	[r0]

	/* manual command register */
	ldr	r0,	REG_SDRAM_MANUAL_CMD

	/* issue set cke high */
	mov	r1,	#CMD_SDRAM_CKE_SET_HIGH
	str	r1,	[r0]

	/* issue nop */
	mov	r1,	#CMD_SDRAM_NOP
	str	r1,	[r0]

	mov	r2,	#0x0100
waitMDDR1:
	subs	r2,	r2,	 #1
	bne	waitMDDR1	/* delay loop */

	/* issue precharge */
	mov	r1,	#CMD_SDRAM_PRECHARGE
	str	r1,	[r0]

	/* issue autorefresh x 2 */
	mov	r1,	#CMD_SDRAM_AUTOREFRESH
	str	r1,	[r0]
	str	r1,	[r0]

	/* mrs register ddr mobile */
	ldr	r0,	REG_SDRAM_MRS
	mov	r1,	#0x33
	str	r1,	[r0]

	/* emrs1 low-power register */
	ldr	r0,	REG_SDRAM_EMRS1
	/* self refresh on all banks */
	mov	r1,	#0
	str	r1,	[r0]

	ldr	r0,	REG_DLL_URD_CONTROL
	ldr	r1,	DLL_URD_CONTROL_VAL
	str	r1,	[r0]

	ldr	r0,	REG_DLL_LRD_CONTROL
	ldr	r1,	DLL_LRD_CONTROL_VAL
	str	r1,	[r0]

	ldr	r0,	REG_DLL_WRT_CONTROL
	ldr	r1,	DLL_WRT_CONTROL_VAL
	str	r1,	[r0]

	/* delay loop */
	mov	r0,	#0x0100
waitMDDR2:
	subs	r0,	r0,	#1
	bne	waitMDDR2

	/*
	 * Delay for SDRAM initialization.
	 */
	mov	r0,	#0x1800
4:
	subs	r0,	r0,	#1	/* Decrement count. */
	bne	4b
	b	common_tc

skip_sdram:
	ldr	r0,	REG_SDRAM_CONFIG
	str	r3,	[r0]

common_tc:
	/* slow interface */
	ldr	r1,	VAL_TC_EMIFS_CS0_CONFIG
	ldr	r0,	REG_TC_EMIFS_CS0_CONFIG
	str	r1,	[r0] /* Chip Select 0 */

	ldr	r1,	VAL_TC_EMIFS_CS1_CONFIG
	ldr	r0,	REG_TC_EMIFS_CS1_CONFIG
	str	r1,	[r0] /* Chip Select 1 */

	ldr	r1,	VAL_TC_EMIFS_CS3_CONFIG
	ldr	r0,	REG_TC_EMIFS_CS3_CONFIG
	str	r1,	[r0] /* Chip Select 3 */

	ldr	r1,	VAL_TC_EMIFS_DWS
	ldr	r0,	REG_TC_EMIFS_DWS
	str	r1,	[r0] /* Enable EMIFS.RDY for CS1 (ether) */

#ifdef CONFIG_H2_OMAP1610
	/* inserting additional 2 clock cycle hold time for LAN */
	ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
	ldr    	r1,     VAL_TC_EMIFS_CS1_ADVANCED
	str     r1,     [r0]
#endif
	/* Start MPU Timer 1 */
	ldr	r0,	REG_MPU_LOAD_TIMER
	ldr	r1,	VAL_MPU_LOAD_TIMER
	str	r1,	[r0]

	ldr	r0,	REG_MPU_CNTL_TIMER
	ldr	r1,	VAL_MPU_CNTL_TIMER
	str	r1,	[r0]

	/* back to arch calling code */
	mov	pc,	lr

	/* the literal pools origin */
	.ltorg

REG_DEVICE_ID:			/* 32 bits */
	.word 0xfffe2004
REG_TC_EMIFS_CONFIG:
	.word 0xfffecc0c
REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
	.word 0xfffecc10
REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
	.word 0xfffecc14
REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
	.word 0xfffecc18
REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
	.word 0xfffecc1c
REG_TC_EMIFS_DWS:		/* 32 bits */
	.word 0xfffecc40
#ifdef CONFIG_H2_OMAP1610
REG_TC_EMIFS_CS1_ADVANCED:	/* 32 bits */
	.word 0xfffecc54
#endif

/* MPU clock/reset/power mode control registers */
REG_ARM_CKCTL:			/* 16 bits */
	.word 0xfffece00
REG_ARM_IDLECT3:		/* 16 bits */
	.word 0xfffece24
REG_ARM_IDLECT2:		/* 16 bits */
	.word 0xfffece08
REG_ARM_IDLECT1:		/* 16 bits */
	.word 0xfffece04
REG_ARM_RSTCT2:			/* 16 bits */
	.word 0xfffece14
REG_ARM_SYSST:			/* 16 bits */
	.word 0xfffece18

/* DPLL control registers */
REG_DPLL1_CTL:			/* 16 bits */
	.word 0xfffecf00

/* Watch Dog register */
/* secure watchdog stop */
REG_WSPRDOG:
	.word 0xfffeb048
/* watchdog write pending */
REG_WWPSDOG:
	.word 0xfffeb034

WSPRDOG_VAL1:
	.word 0x0000aaaa
WSPRDOG_VAL2:
	.word 0x00005555

/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
 counter @8192 rows, 10 ns, 8 burst */
REG_SDRAM_CONFIG:
	.word 0xfffecc20
REG_SDRAM_CONFIG2:
	.word 0xfffecc3c
REG_TC_EMIFF_DOUBLER:		/* 32 bits */
	.word 0xfffecc60

/* Operation register */
REG_SDRAM_OPERATION:
	.word 0xfffecc80

/* Manual command register */
REG_SDRAM_MANUAL_CMD:
	.word 0xfffecc84

/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
REG_SDRAM_MRS:
	.word 0xfffecc70

/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
REG_SDRAM_EMRS1:
	.word 0xfffecc78

/* WRT DLL register */
REG_DLL_WRT_CONTROL:
	.word 0xfffecc68
DLL_WRT_CONTROL_VAL:
	.word 0x03f00002    /* Phase of 72deg, write offset +31  */

/* URD DLL register */
REG_DLL_URD_CONTROL:
	.word 0xfffeccc0
DLL_URD_CONTROL_VAL:
	.word 0x00800002    /* Phase of 72deg, read offset +31  */

/* LRD DLL register */
REG_DLL_LRD_CONTROL:
	.word 0xfffecccc
DLL_LRD_CONTROL_VAL:
	.word 0x00800002    /* read offset +31  */

REG_WATCHDOG:
	.word 0xfffec808
WATCHDOG_VAL1:
	.word 0x000000f5
WATCHDOG_VAL2:
	.word 0x000000a0

REG_MPU_LOAD_TIMER:
	.word 0xfffec504
REG_MPU_CNTL_TIMER:
	.word 0xfffec500
VAL_MPU_LOAD_TIMER:
	.word 0xffffffff
VAL_MPU_CNTL_TIMER:
	.word 0xffffffa1

/* 96 MHz Samsung Mobile DDR */
/* Original setting for TMX device */
VAL_SDRAM_CONFIG_SDF0:
    .word 0x0014e6fe

/* NEW_SYS_FREQ mode (valid only TMP/TMS devices) */
VAL_SDRAM_CONFIG_SDF1:
    .word 0x0114e6fe

VAL_ARM_CKCTL:
	.word 0x2000		/* was:	0x3000, now use CLK_REF for timer input */
VAL_DPLL1_CTL:
	.word 0x2830

#ifdef CONFIG_OSK_OMAP5912
VAL_TC_EMIFS_CS0_CONFIG:
	.word 0x002130b0
VAL_TC_EMIFS_CS1_CONFIG:
	.word 0x00001133
VAL_TC_EMIFS_CS2_CONFIG:
	.word 0x000055f0
VAL_TC_EMIFS_CS3_CONFIG:
	.word 0x88013141
VAL_TC_EMIFS_DWS:	/* Enable EMIFS.RDY for CS1 access (ether) */
	.word 0x000000c0
VAL_DEVICE_ID_TMP:	/* TMP/TMS=0xb65f, TMX=0xb58c */
	.word 0xb65f
#endif

#ifdef CONFIG_H2_OMAP1610
VAL_TC_EMIFS_CS0_CONFIG:
	.word 0x00203331
VAL_TC_EMIFS_CS1_CONFIG:
	.word 0x8180fff3
VAL_TC_EMIFS_CS2_CONFIG:
	.word 0xf800f22a
VAL_TC_EMIFS_CS3_CONFIG:
	.word 0x88013141
VAL_TC_EMIFS_CS1_ADVANCED:
	.word 0x00000022
#endif

VAL_ARM_IDLECT1:
	.word 0x00000400
VAL_ARM_IDLECT2:
	.word 0x00000886
VAL_ARM_IDLECT3:
	.word 0x00000015

/* command values */
.equ CMD_SDRAM_NOP,             0x00000000
.equ CMD_SDRAM_PRECHARGE,       0x00000001
.equ CMD_SDRAM_AUTOREFRESH,     0x00000002
.equ CMD_SDRAM_CKE_SET_HIGH,    0x00000007
Commit	Line	Data
1eaeb58e WD	1	/*
	2	* Board specific setup info
	3	*
	4	* (C) Copyright 2003
	5	* Texas Instruments, <www.ti.com>
	6	* Kshitij Gupta <[email protected]>
	7	*
	8	* Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
	9	*
	10	* Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
	30	#include <config.h>
	31	#include <version.h>
	32
	33	#if defined(CONFIG_OMAP1610)
	34	#include <./configs/omap1510.h>
	35	#endif
	36
	37
	38	_TEXT_BASE:
	39	.word TEXT_BASE /* sdram load addr from config.mk */
	40
87cb6862 WD	41	.globl lowlevel_init
87cb6862 WD	42	lowlevel_init:
1eaeb58e	43
6080a0eb SR	44	/------------------------------------------------------
	45	* Ensure i-cache is enabled *
	46	* To configure TC regs without fetching instruction *
	47	------------------------------------------------------/
	48	mrc p15, 0, r0, c1, c0
	49	orr r0, r0, #0x1000
	50	mcr p15, 0, r0, c1, c0
1eaeb58e WD	51
	52	/------------------------------------------------------
	53	mask all IRQs by setting all bits in the INTMR default
	54	------------------------------------------------------/
	55	mov r1, #0xffffffff
	56	ldr r0, =REG_IHL1_MIR
	57	str r1, [r0]
	58	ldr r0, =REG_IHL2_MIR
	59	str r1, [r0]
	60
	61	/------------------------------------------------------
	62	* Set up ARM CLM registers (IDLECT1) *
	63	------------------------------------------------------/
	64	ldr r0, REG_ARM_IDLECT1
	65	ldr r1, VAL_ARM_IDLECT1
	66	str r1, [r0]
	67
	68	/------------------------------------------------------
6080a0eb	69	* Set up ARM CLM registers (IDLECT2) *
1eaeb58e WD	70	------------------------------------------------------/
	71	ldr r0, REG_ARM_IDLECT2
	72	ldr r1, VAL_ARM_IDLECT2
	73	str r1, [r0]
	74
	75	/------------------------------------------------------
6080a0eb	76	* Set up ARM CLM registers (IDLECT3) *
1eaeb58e WD	77	------------------------------------------------------/
	78	ldr r0, REG_ARM_IDLECT3
	79	ldr r1, VAL_ARM_IDLECT3
	80	str r1, [r0]
	81
6080a0eb	82	mov r1, #0x01 /* PER_EN bit */
1eaeb58e	83	ldr r0, REG_ARM_RSTCT2
6080a0eb	84	strh r1, [r0] /* CLKM; Peripheral reset. */
1eaeb58e	85
6080a0eb SR	86	/* Set CLKM to Sync-Scalable */
6080a0eb SR	87	mov r1, #0x1000
1eaeb58e	88	ldr r0, REG_ARM_SYSST
6080a0eb SR	89
	90	mov r2, #0
	91	1: cmp r2, #1
	92	streqh r1, [r0]
	93	add r2, r2, #1
	94	cmp r2, #0x100 /* wait for any bubbles to finish */
1eaeb58e	95	bne 1b
6080a0eb	96
1eaeb58e WD	97	ldr r1, VAL_ARM_CKCTL
	98	ldr r0, REG_ARM_CKCTL
	99	strh r1, [r0]
	100
	101	/* a few nops to let settle */
	102	nop
	103	nop
	104	nop
	105	nop
	106	nop
	107	nop
	108	nop
	109	nop
	110	nop
	111	nop
	112
	113	/* setup DPLL 1 */
	114	/* Ramp up the clock to 96Mhz */
	115	ldr r1, VAL_DPLL1_CTL
	116	ldr r0, REG_DPLL1_CTL
	117	strh r1, [r0]
6080a0eb SR	118	ands r1, r1, #0x10 /* Check if PLL is enabled. */
6080a0eb SR	119	beq lock_end /* Do not look for lock if BYPASS selected */
1eaeb58e WD	120	2:
1eaeb58e WD	121	ldrh r1, [r0]
6080a0eb SR	122	ands r1, r1, #0x01 /* Check the LOCK bit.*/
6080a0eb SR	123	beq 2b /* loop until bit goes hi. */
1eaeb58e WD	124	lock_end:
1eaeb58e WD	125
1eaeb58e	126	/------------------------------------------------------
6080a0eb	127	* Turn off the watchdog during init... *
1eaeb58e WD	128	------------------------------------------------------/
	129	ldr r0, REG_WATCHDOG
	130	ldr r1, WATCHDOG_VAL1
	131	str r1, [r0]
	132	ldr r1, WATCHDOG_VAL2
	133	str r1, [r0]
	134	ldr r0, REG_WSPRDOG
	135	ldr r1, WSPRDOG_VAL1
	136	str r1, [r0]
	137	ldr r0, REG_WWPSDOG
	138
	139	watch1Wait:
	140	ldr r1, [r0]
	141	tst r1, #0x10
	142	bne watch1Wait
	143
	144	ldr r0, REG_WSPRDOG
	145	ldr r1, WSPRDOG_VAL2
	146	str r1, [r0]
	147	ldr r0, REG_WWPSDOG
	148	watch2Wait:
	149	ldr r1, [r0]
	150	tst r1, #0x10
	151	bne watch2Wait
	152
1eaeb58e	153	/* Set memory timings corresponding to the new clock speed */
6080a0eb	154	ldr r3, VAL_SDRAM_CONFIG_SDF0
1eaeb58e WD	155
	156	/* Check execution location to determine current execution location
	157	* and branch to appropriate initialization code.
	158	*/
6080a0eb SR	159	mov r0, #0x10000000 /* Load physical SDRAM base. */
	160	mov r1, pc /* Get current execution location. */
	161	cmp r1, r0 /* Compare. */
	162	bge skip_sdram /* Skip over EMIF-fast initialization if running from SDRAM. */
	163
	164	/* identify the device revision, -- TMX or TMP(TMS) */
	165	ldr r0, REG_DEVICE_ID
	166	ldr r1, [r0]
	167
	168	ldr r0, VAL_DEVICE_ID_TMP
	169	mov r1, r1, lsl #15
	170	mov r1, r1, lsr #16
	171	cmp r0, r1
	172	bne skip_TMP_Patch
	173
	174	/* Enable TMP/TMS device new features */
	175	mov r0, #1
	176	ldr r1, REG_TC_EMIFF_DOUBLER
	177	str r0, [r1]
	178
	179	/* Enable new ac parameters */
	180	mov r0, #0x0b
	181	ldr r1, REG_SDRAM_CONFIG2
	182	str r0, [r1]
	183
	184	ldr r3, VAL_SDRAM_CONFIG_SDF1
	185
	186	skip_TMP_Patch:
1eaeb58e WD	187
	188	/*
	189	* Delay for SDRAM initialization.
	190	*/
6080a0eb	191	mov r0, #0x1800 /* value should be checked */
1eaeb58e	192	3:
6080a0eb	193	subs r0, r0, #0x1 /* Decrement count */
1eaeb58e WD	194	bne 3b
1eaeb58e WD	195
1eaeb58e WD	196	/*
	197	* Set SDRAM control values. Disable refresh before MRS command.
	198	*/
	199
	200	/* mobile ddr operation */
	201	ldr r0, REG_SDRAM_OPERATION
	202	mov r2, #07
	203	str r2, [r0]
	204
	205	/* config register */
	206	ldr r0, REG_SDRAM_CONFIG
6080a0eb	207	str r3, [r0]
1eaeb58e WD	208
	209	/* manual command register */
	210	ldr r0, REG_SDRAM_MANUAL_CMD
6080a0eb	211
1eaeb58e WD	212	/* issue set cke high */
	213	mov r1, #CMD_SDRAM_CKE_SET_HIGH
	214	str r1, [r0]
6080a0eb	215
1eaeb58e WD	216	/* issue nop */
	217	mov r1, #CMD_SDRAM_NOP
	218	str r1, [r0]
	219
	220	mov r2, #0x0100
	221	waitMDDR1:
	222	subs r2, r2, #1
	223	bne waitMDDR1 /* delay loop */
	224
	225	/* issue precharge */
	226	mov r1, #CMD_SDRAM_PRECHARGE
	227	str r1, [r0]
	228
	229	/* issue autorefresh x 2 */
	230	mov r1, #CMD_SDRAM_AUTOREFRESH
	231	str r1, [r0]
	232	str r1, [r0]
	233
	234	/* mrs register ddr mobile */
	235	ldr r0, REG_SDRAM_MRS
	236	mov r1, #0x33
	237	str r1, [r0]
	238
	239	/* emrs1 low-power register */
	240	ldr r0, REG_SDRAM_EMRS1
	241	/* self refresh on all banks */
	242	mov r1, #0
	243	str r1, [r0]
	244
	245	ldr r0, REG_DLL_URD_CONTROL
	246	ldr r1, DLL_URD_CONTROL_VAL
	247	str r1, [r0]
	248
	249	ldr r0, REG_DLL_LRD_CONTROL
	250	ldr r1, DLL_LRD_CONTROL_VAL
	251	str r1, [r0]
	252
	253	ldr r0, REG_DLL_WRT_CONTROL
	254	ldr r1, DLL_WRT_CONTROL_VAL
	255	str r1, [r0]
	256
	257	/* delay loop */
6080a0eb	258	mov r0, #0x0100
1eaeb58e	259	waitMDDR2:
6080a0eb	260	subs r0, r0, #1
1eaeb58e WD	261	bne waitMDDR2
	262
	263	/*
	264	* Delay for SDRAM initialization.
	265	*/
6080a0eb	266	mov r0, #0x1800
1eaeb58e	267	4:
6080a0eb	268	subs r0, r0, #1 /* Decrement count. */
1eaeb58e WD	269	bne 4b
	270	b common_tc
	271
	272	skip_sdram:
1eaeb58e	273	ldr r0, REG_SDRAM_CONFIG
6080a0eb	274	str r3, [r0]
1eaeb58e WD	275
	276	common_tc:
	277	/* slow interface */
	278	ldr r1, VAL_TC_EMIFS_CS0_CONFIG
	279	ldr r0, REG_TC_EMIFS_CS0_CONFIG
	280	str r1, [r0] /* Chip Select 0 */
	281
	282	ldr r1, VAL_TC_EMIFS_CS1_CONFIG
	283	ldr r0, REG_TC_EMIFS_CS1_CONFIG
	284	str r1, [r0] /* Chip Select 1 */
6080a0eb	285
1eaeb58e WD	286	ldr r1, VAL_TC_EMIFS_CS3_CONFIG
	287	ldr r0, REG_TC_EMIFS_CS3_CONFIG
	288	str r1, [r0] /* Chip Select 3 */
	289
6080a0eb SR	290	ldr r1, VAL_TC_EMIFS_DWS
	291	ldr r0, REG_TC_EMIFS_DWS
	292	str r1, [r0] /* Enable EMIFS.RDY for CS1 (ether) */
	293
1eaeb58e WD	294	#ifdef CONFIG_H2_OMAP1610
	295	/* inserting additional 2 clock cycle hold time for LAN */
	296	ldr r0, REG_TC_EMIFS_CS1_ADVANCED
	297	ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
	298	str r1, [r0]
	299	#endif
	300	/* Start MPU Timer 1 */
	301	ldr r0, REG_MPU_LOAD_TIMER
	302	ldr r1, VAL_MPU_LOAD_TIMER
	303	str r1, [r0]
	304
	305	ldr r0, REG_MPU_CNTL_TIMER
	306	ldr r1, VAL_MPU_CNTL_TIMER
	307	str r1, [r0]
	308
	309	/* back to arch calling code */
	310	mov pc, lr
	311
	312	/* the literal pools origin */
	313	.ltorg
	314
6080a0eb SR	315	REG_DEVICE_ID: /* 32 bits */
	316	.word 0xfffe2004
	317	REG_TC_EMIFS_CONFIG:
1eaeb58e WD	318	.word 0xfffecc0c
	319	REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
	320	.word 0xfffecc10
	321	REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
	322	.word 0xfffecc14
	323	REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
	324	.word 0xfffecc18
	325	REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
	326	.word 0xfffecc1c
6080a0eb SR	327	REG_TC_EMIFS_DWS: /* 32 bits */
6080a0eb SR	328	.word 0xfffecc40
1eaeb58e WD	329	#ifdef CONFIG_H2_OMAP1610
	330	REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
	331	.word 0xfffecc54
	332	#endif
	333
	334	/* MPU clock/reset/power mode control registers */
	335	REG_ARM_CKCTL: /* 16 bits */
	336	.word 0xfffece00
1eaeb58e WD	337	REG_ARM_IDLECT3: /* 16 bits */
	338	.word 0xfffece24
	339	REG_ARM_IDLECT2: /* 16 bits */
	340	.word 0xfffece08
	341	REG_ARM_IDLECT1: /* 16 bits */
	342	.word 0xfffece04
1eaeb58e WD	343	REG_ARM_RSTCT2: /* 16 bits */
	344	.word 0xfffece14
	345	REG_ARM_SYSST: /* 16 bits */
	346	.word 0xfffece18
6080a0eb	347
1eaeb58e WD	348	/* DPLL control registers */
	349	REG_DPLL1_CTL: /* 16 bits */
	350	.word 0xfffecf00
	351
	352	/* Watch Dog register */
	353	/* secure watchdog stop */
	354	REG_WSPRDOG:
	355	.word 0xfffeb048
	356	/* watchdog write pending */
	357	REG_WWPSDOG:
	358	.word 0xfffeb034
	359
	360	WSPRDOG_VAL1:
	361	.word 0x0000aaaa
	362	WSPRDOG_VAL2:
	363	.word 0x00005555
	364
	365	/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
	366	counter @8192 rows, 10 ns, 8 burst */
	367	REG_SDRAM_CONFIG:
	368	.word 0xfffecc20
6080a0eb SR	369	REG_SDRAM_CONFIG2:
	370	.word 0xfffecc3c
	371	REG_TC_EMIFF_DOUBLER: /* 32 bits */
	372	.word 0xfffecc60
1eaeb58e WD	373
	374	/* Operation register */
	375	REG_SDRAM_OPERATION:
	376	.word 0xfffecc80
	377
	378	/* Manual command register */
	379	REG_SDRAM_MANUAL_CMD:
	380	.word 0xfffecc84
	381
	382	/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
	383	REG_SDRAM_MRS:
	384	.word 0xfffecc70
	385
	386	/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
	387	REG_SDRAM_EMRS1:
	388	.word 0xfffecc78
	389
	390	/* WRT DLL register */
	391	REG_DLL_WRT_CONTROL:
	392	.word 0xfffecc68
	393	DLL_WRT_CONTROL_VAL:
6080a0eb	394	.word 0x03f00002 /* Phase of 72deg, write offset +31 */
1eaeb58e WD	395
	396	/* URD DLL register */
	397	REG_DLL_URD_CONTROL:
	398	.word 0xfffeccc0
	399	DLL_URD_CONTROL_VAL:
6080a0eb	400	.word 0x00800002 /* Phase of 72deg, read offset +31 */
1eaeb58e WD	401
	402	/* LRD DLL register */
	403	REG_DLL_LRD_CONTROL:
	404	.word 0xfffecccc
6080a0eb SR	405	DLL_LRD_CONTROL_VAL:
6080a0eb SR	406	.word 0x00800002 /* read offset +31 */
1eaeb58e WD	407
	408	REG_WATCHDOG:
	409	.word 0xfffec808
6080a0eb SR	410	WATCHDOG_VAL1:
	411	.word 0x000000f5
	412	WATCHDOG_VAL2:
	413	.word 0x000000a0
1eaeb58e WD	414
1eaeb58e WD	415	REG_MPU_LOAD_TIMER:
6080a0eb	416	.word 0xfffec504
1eaeb58e WD	417	REG_MPU_CNTL_TIMER:
1eaeb58e WD	418	.word 0xfffec500
6080a0eb SR	419	VAL_MPU_LOAD_TIMER:
	420	.word 0xffffffff
	421	VAL_MPU_CNTL_TIMER:
	422	.word 0xffffffa1
1eaeb58e WD	423
1eaeb58e WD	424	/* 96 MHz Samsung Mobile DDR */
6080a0eb SR	425	/* Original setting for TMX device */
	426	VAL_SDRAM_CONFIG_SDF0:
	427	.word 0x0014e6fe
1eaeb58e	428
6080a0eb SR	429	/* NEW_SYS_FREQ mode (valid only TMP/TMS devices) */
	430	VAL_SDRAM_CONFIG_SDF1:
	431	.word 0x0114e6fe
1eaeb58e WD	432
1eaeb58e WD	433	VAL_ARM_CKCTL:
6080a0eb	434	.word 0x2000 /* was: 0x3000, now use CLK_REF for timer input */
1eaeb58e WD	435	VAL_DPLL1_CTL:
	436	.word 0x2830
	437
	438	#ifdef CONFIG_OSK_OMAP5912
	439	VAL_TC_EMIFS_CS0_CONFIG:
	440	.word 0x002130b0
	441	VAL_TC_EMIFS_CS1_CONFIG:
d1dd22f9	442	.word 0x00001133
1eaeb58e WD	443	VAL_TC_EMIFS_CS2_CONFIG:
	444	.word 0x000055f0
	445	VAL_TC_EMIFS_CS3_CONFIG:
6080a0eb SR	446	.word 0x88013141
	447	VAL_TC_EMIFS_DWS: /* Enable EMIFS.RDY for CS1 access (ether) */
	448	.word 0x000000c0
	449	VAL_DEVICE_ID_TMP: /* TMP/TMS=0xb65f, TMX=0xb58c */
	450	.word 0xb65f
1eaeb58e WD	451	#endif
	452
	453	#ifdef CONFIG_H2_OMAP1610
	454	VAL_TC_EMIFS_CS0_CONFIG:
	455	.word 0x00203331
	456	VAL_TC_EMIFS_CS1_CONFIG:
	457	.word 0x8180fff3
	458	VAL_TC_EMIFS_CS2_CONFIG:
	459	.word 0xf800f22a
	460	VAL_TC_EMIFS_CS3_CONFIG:
6080a0eb	461	.word 0x88013141
1eaeb58e WD	462	VAL_TC_EMIFS_CS1_ADVANCED:
	463	.word 0x00000022
	464	#endif
	465
1eaeb58e WD	466	VAL_ARM_IDLECT1:
1eaeb58e WD	467	.word 0x00000400
1eaeb58e WD	468	VAL_ARM_IDLECT2:
	469	.word 0x00000886
	470	VAL_ARM_IDLECT3:
	471	.word 0x00000015
	472
1eaeb58e	473	/* command values */
6080a0eb SR	474	.equ CMD_SDRAM_NOP, 0x00000000
	475	.equ CMD_SDRAM_PRECHARGE, 0x00000001
	476	.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
	477	.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007