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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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2 | /* |
3 | * Configuation settings for the WB45N CPU Module. | |
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4 | */ |
5 | ||
6 | #ifndef __CONFIG_H__ | |
7 | #define __CONFIG_H__ | |
8 | ||
9 | #include <asm/hardware.h> | |
10 | ||
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11 | /* ARM asynchronous clock */ |
12 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 | |
13 | #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ | |
14 | ||
15 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
16 | #define CONFIG_SETUP_MEMORY_TAGS | |
17 | #define CONFIG_INITRD_TAG | |
18 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
19 | ||
20 | /* general purpose I/O */ | |
21 | #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ | |
22 | #define CONFIG_AT91_GPIO | |
23 | ||
24 | /* serial console */ | |
25 | #define CONFIG_ATMEL_USART | |
26 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU | |
27 | #define CONFIG_USART_ID ATMEL_ID_SYS | |
28 | ||
29 | /* | |
30 | * BOOTP options | |
31 | */ | |
32 | #define CONFIG_BOOTP_BOOTFILESIZE | |
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33 | |
34 | /* SDRAM */ | |
35 | #define CONFIG_NR_DRAM_BANKS 1 | |
36 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 | |
37 | #define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */ | |
38 | ||
39 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
40 | (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) | |
41 | ||
42 | /* NAND flash */ | |
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43 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
44 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
45 | /* our ALE is AD21 */ | |
46 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) | |
47 | /* our CLE is AD22 */ | |
48 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) | |
49 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 | |
50 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 | |
51 | ||
52 | /* PMECC & PMERRLOC */ | |
53 | #define CONFIG_ATMEL_NAND_HWECC 1 | |
54 | #define CONFIG_ATMEL_NAND_HW_PMECC 1 | |
55 | #define CONFIG_PMECC_CAP 4 | |
56 | #define CONFIG_PMECC_SECTOR_SIZE 512 | |
57 | ||
5aaef600 | 58 | #define CONFIG_CMD_MTDPARTS |
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59 | #define CONFIG_RBTREE |
60 | #define CONFIG_LZO | |
61 | ||
62 | /* Ethernet */ | |
63 | #define CONFIG_MACB | |
64 | #define CONFIG_RMII | |
65 | #define CONFIG_NET_RETRY_COUNT 20 | |
66 | #define CONFIG_MACB_SEARCH_PHY | |
67 | #define CONFIG_ETHADDR C0:EE:40:00:00:00 | |
68 | #define CONFIG_ENV_OVERWRITE 1 | |
69 | ||
70 | /* System */ | |
71 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ | |
72 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
73 | #define CONFIG_SYS_MEMTEST_END 0x23e00000 | |
74 | ||
75 | #ifdef CONFIG_SYS_USE_NANDFLASH | |
76 | /* bootstrap + u-boot + env + linux in nandflash */ | |
77 | #define CONFIG_ENV_OFFSET 0xa0000 | |
78 | #define CONFIG_ENV_OFFSET_REDUND 0xc0000 | |
79 | #define CONFIG_ENV_SIZE 0x20000 /* 1 block = 128 kB */ | |
80 | ||
81 | #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xe0000 0x280000; " \ | |
82 | "run _mtd; bootm" | |
83 | ||
84 | #define MTDIDS_DEFAULT "nand0=atmel_nand" | |
85 | #define MTDPARTS_DEFAULT "mtdparts=atmel_nand:" \ | |
86 | "128K(at91bs)," \ | |
87 | "512K(u-boot)," \ | |
88 | "128K(u-boot-env)," \ | |
89 | "128K(redund-env)," \ | |
90 | "2560K(kernel-a)," \ | |
91 | "2560K(kernel-b)," \ | |
92 | "38912K(rootfs-a)," \ | |
93 | "38912K(rootfs-b)," \ | |
94 | "46208K(user)," \ | |
95 | "512K(logs)" | |
96 | ||
97 | #else | |
98 | #error No boot method selected, please select 'CONFIG_SYS_USE_NANDFLASH' | |
99 | #endif | |
100 | ||
101 | #define CONFIG_BOOTARGS "console=ttyS0,115200 earlyprintk " \ | |
102 | "rw noinitrd mem=64M " \ | |
103 | "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=6" | |
104 | ||
105 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
106 | "_mtd=mtdparts default; setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
107 | "autoload=no\0" \ | |
108 | "autostart=no\0" \ | |
109 | "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ | |
110 | "\0" | |
111 | ||
112 | #define CONFIG_SYS_CBSIZE 256 | |
113 | #define CONFIG_SYS_MAXARGS 16 | |
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114 | |
115 | /* | |
116 | * Size of malloc() pool | |
117 | */ | |
118 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) | |
119 | ||
120 | /* SPL */ | |
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121 | #define CONFIG_SPL_TEXT_BASE 0x300000 |
122 | #define CONFIG_SPL_MAX_SIZE 0x6000 | |
123 | #define CONFIG_SPL_STACK 0x308000 | |
124 | ||
125 | #define CONFIG_SPL_BSS_START_ADDR 0x20000000 | |
126 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
127 | #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 | |
128 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 | |
129 | ||
130 | #define CONFIG_SYS_MONITOR_LEN (512 << 10) | |
131 | ||
132 | #define CONFIG_SYS_MASTER_CLOCK 132096000 | |
133 | #define CONFIG_SYS_AT91_PLLA 0x20c73f03 | |
134 | #define CONFIG_SYS_MCKR 0x1301 | |
135 | #define CONFIG_SYS_MCKR_CSS 0x1302 | |
136 | ||
137 | #define CONFIG_SPL_NAND_DRIVERS | |
138 | #define CONFIG_SPL_NAND_BASE | |
139 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 | |
140 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
141 | #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 | |
142 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
143 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
144 | #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 | |
145 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 | |
146 | #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER | |
147 | ||
148 | #endif /* __CONFIG_H__ */ |