[u-boot.git] / board / menlo / m53menlo / m53menlo.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Menlosystems M53Menlo board
 *
 * Copyright (C) 2012-2017 Marek Vasut <[email protected]>
 * Copyright (C) 2014-2017 Olaf Mandel <[email protected]>
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
#include <asm/mach-imx/mx5_video.h>
#include <asm/mach-imx/video.h>
#include <asm/gpio.h>
#include <asm/spl.h>
#include <fdt_support.h>
#include <fsl_esdhc.h>
#include <i2c.h>
#include <ipu_pixfmt.h>
#include <linux/errno.h>
#include <linux/fb.h>
#include <mmc.h>
#include <netdev.h>
#include <spl.h>
#include <splash.h>
#include <usb/ehci-ci.h>

DECLARE_GLOBAL_DATA_PTR;

static u32 mx53_dram_size[2];

ulong board_get_usable_ram_top(ulong total_size)
{
	/*
	 * WARNING: We must override get_effective_memsize() function here
	 * to report only the size of the first DRAM bank. This is to make
	 * U-Boot relocator place U-Boot into valid memory, that is, at the
	 * end of the first DRAM bank. If we did not override this function
	 * like so, U-Boot would be placed at the address of the first DRAM
	 * bank + total DRAM size - sizeof(uboot), which in the setup where
	 * each DRAM bank contains 512MiB of DRAM would result in placing
	 * U-Boot into invalid memory area close to the end of the first
	 * DRAM bank.
	 */
	return PHYS_SDRAM_2 + mx53_dram_size[1];
}

int dram_init(void)
{
	mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
	mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);

	gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];

	return 0;
}

int dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size = mx53_dram_size[0];

	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	gd->bd->bi_dram[1].size = mx53_dram_size[1];

	return 0;
}

static void setup_iomux_uart(void)
{
	static const iomux_v3_cfg_t uart_pads[] = {
		MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
		MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
	};

	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}

#ifdef CONFIG_USB_EHCI_MX5
int board_ehci_hcd_init(int port)
{
	if (port == 0) {
		/* USB OTG PWRON */
		imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
						    PAD_CTL_PKE |
						    PAD_CTL_DSE_HIGH));
		gpio_request(IMX_GPIO_NR(1, 4), "USB_OTG_PWRON");
		gpio_direction_output(IMX_GPIO_NR(1, 4), 0);

		/* USB OTG Over Current */
		imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13);
	} else if (port == 1) {
		/* USB Host PWRON */
		imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
						    PAD_CTL_PKE |
						    PAD_CTL_DSE_HIGH));
		gpio_request(IMX_GPIO_NR(1, 2), "USB_HOST_PWRON");
		gpio_direction_output(IMX_GPIO_NR(1, 2), 0);

		/* USB Host Over Current */
		imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC);
	}

	return 0;
}
#endif

static void setup_iomux_fec(void)
{
	static const iomux_v3_cfg_t fec_pads[] = {
		/* MDIO pads */
		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),

		/* FEC 0 pads */
		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),

		/* FEC 1 pads */
		NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
	};

	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}

#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg = {
	MMC_SDHC1_BASE_ADDR,
};

int board_mmc_getcd(struct mmc *mmc)
{
	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
	gpio_direction_input(IMX_GPIO_NR(1, 1));

	return !gpio_get_value(IMX_GPIO_NR(1, 1));
}

#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
				 PAD_CTL_PUS_100K_UP)
#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
				 PAD_CTL_DSE_HIGH)

int board_mmc_init(bd_t *bis)
{
	static const iomux_v3_cfg_t sd1_pads[] = {
		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
	};

	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);

	imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));

	return fsl_esdhc_initialize(bis, &esdhc_cfg);
}
#endif

#ifdef CONFIG_VIDEO
static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
{
	static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
	int ret;

	/* For ETM0430G0DH6 model, this must be enabled before the clock. */
	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);

	/*
	 * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
	 * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
	 */
	ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
	if (ret)
		puts("IPU:   Failed to configure LDB clock\n");

	/* Configure CCM_CSCMR2 */
	clrsetbits_le32(&mxc_ccm->cscmr2,
			(0x7 << 26) | BIT(10) | BIT(8),
			(0x5 << 26) | BIT(10) | BIT(8));

	/* Configure LDB_CTRL */
	writel(0x201, 0x53fa8008);
}

static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
{
	gpio_request(IMX_GPIO_NR(6, 0), "LCD");

	/* For ETM0430G0DH6 model, this must be enabled before the clock. */
	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);

	/*
	 * Set LVDS clock to 9 MHz for the display. The PLL4 is set to
	 * 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
	 */
	enable_lvds_clock(dev, 63);
}

static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
{
	gpio_request(IMX_GPIO_NR(6, 0), "LCD");

	/*
	 * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
	 * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
	 */
	enable_lvds_clock(dev, 233);

	/* For ETM0700G0DH6 model, this may be enabled after the clock. */
	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
}

static const char *lvds_compat_string;

static int detect_lvds(struct display_info_t const *dev)
{
	u8 touchid[23];
	u8 *touchptr = &touchid[0];
	int ret;

	ret = i2c_set_bus_num(0);
	if (ret)
		return 0;

	/* Touchscreen is at address 0x38, ID register is 0xbb. */
	ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
	if (ret)
		return 0;

	/* EP0430 prefixes the response with 0xbb, skip it. */
	if (*touchptr == 0xbb)
		touchptr++;

	/* Skip the 'EP' prefix. */
	touchptr += 2;

	ret = !memcmp(touchptr, &dev->mode.name[7], 4);
	if (ret)
		lvds_compat_string = dev->mode.name;

	return ret;
}

void board_preboot_os(void)
{
	/* Power off the LCD to prevent awful color flicker */
	gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
}

int ft_board_setup(void *blob, bd_t *bd)
{
	if (lvds_compat_string)
		do_fixup_by_path_string(blob, "/panel", "compatible",
					lvds_compat_string);

	return 0;
}

struct display_info_t const displays[] = {
	{
		.bus	= 0,
		.addr	= 0,
		.detect	= detect_lvds,
		.enable	= enable_lvds_etm0430g0dh6,
		.pixfmt	= IPU_PIX_FMT_RGB666,
		.mode	= {
			.name		= "edt,etm0430g0dh6",
			.refresh	= 60,
			.xres		= 480,
			.yres		= 272,
			.pixclock	= 111111, /* picosecond (9 MHz) */
			.left_margin	= 2,
			.right_margin	= 2,
			.upper_margin	= 2,
			.lower_margin	= 2,
			.hsync_len	= 41,
			.vsync_len	= 10,
			.sync		= 0x40000000,
			.vmode          = FB_VMODE_NONINTERLACED
		}
	}, {
		.bus	= 0,
		.addr	= 0,
		.detect	= detect_lvds,
		.enable	= enable_lvds_etm0700g0dh6,
		.pixfmt	= IPU_PIX_FMT_RGB666,
		.mode	= {
			.name		= "edt,etm0700g0dh6",
			.refresh	= 60,
			.xres		= 800,
			.yres		= 480,
			.pixclock	= 30048, /* picosecond (33.28 MHz) */
			.left_margin	= 40,
			.right_margin	= 88,
			.upper_margin	= 10,
			.lower_margin	= 33,
			.hsync_len	= 128,
			.vsync_len	= 2,
			.sync		= FB_SYNC_EXT,
			.vmode          = FB_VMODE_NONINTERLACED
		}
	}
};

size_t display_count = ARRAY_SIZE(displays);
#endif

#ifdef CONFIG_SPLASH_SCREEN
static struct splash_location default_splash_locations[] = {
	{
		.name		= "mmc_fs",
		.storage	= SPLASH_STORAGE_MMC,
		.flags		= SPLASH_STORAGE_FS,
		.devpart	= "0:1",
	},
};

int splash_screen_prepare(void)
{
	return splash_source_load(default_splash_locations,
				  ARRAY_SIZE(default_splash_locations));
}
#endif

#define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)

static void setup_iomux_i2c(void)
{
	static const iomux_v3_cfg_t i2c_pads[] = {
		/* I2C1 */
		NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
		/* I2C2 */
		NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
	};

	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
}

static void setup_iomux_video(void)
{
	static const iomux_v3_cfg_t lcd_pads[] = {
		MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
		MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
		MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
		MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
		MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
	};

	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
}

static void setup_iomux_nand(void)
{
	static const iomux_v3_cfg_t nand_pads[] = {
		NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
			     PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
			     PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
			     PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
			     PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
			     PAD_CTL_PUS_100K_UP),
		NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
			     PAD_CTL_PUS_100K_UP),
		NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
			     PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
	};

	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
}

static void m53_set_clock(void)
{
	int ret;
	const u32 ref_clk = MXC_HCLK;
	const u32 dramclk = 400;
	u32 cpuclk;

	gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK");

	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
					    PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
	gpio_direction_input(IMX_GPIO_NR(4, 0));

	/* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
	cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;

	ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
	if (ret)
		printf("CPU:   Switch CPU clock to %dMHz failed\n", cpuclk);

	ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
	if (ret) {
		printf("CPU:   Switch peripheral clock to %dMHz failed\n",
		       dramclk);
	}

	ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
	if (ret)
		printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
}

static void m53_set_nand(void)
{
	u32 i;

	/* NAND flash is muxed on ATA pins */
	setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);

	/* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
	for (i = 0x4; i < 0x94; i += 0x18) {
		clrbits_le32(WEIM_BASE_ADDR + i,
			     WEIM_GCR2_MUX16_BYP_GRANT_MASK);
	}

	mxc_set_clock(0, 33, MXC_NFC_CLK);
	enable_nfc_clk(1);
}

int board_early_init_f(void)
{
	setup_iomux_uart();
	setup_iomux_fec();
	setup_iomux_i2c();
	setup_iomux_nand();
	setup_iomux_video();

	m53_set_clock();

	mxc_set_sata_internal_clock();

	/* NAND clock @ 33MHz */
	m53_set_nand();

	return 0;
}

int board_init(void)
{
	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;

	return 0;
}

int checkboard(void)
{
	puts("Board: Menlosystems M53Menlo\n");

	return 0;
}

/*
 * NAND SPL
 */
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
	setup_iomux_nand();
	m53_set_clock();
	m53_set_nand();
}

u32 spl_boot_device(void)
{
	return BOOT_DEVICE_NAND;
}
#endif
Commit	Line	Data
39cb4f3c MV	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Menlosystems M53Menlo board
	4	*
	5	* Copyright (C) 2012-2017 Marek Vasut <[email protected]>
	6	* Copyright (C) 2014-2017 Olaf Mandel <[email protected]>
	7	*/
	8
	9	#include <common.h>
	10	#include <asm/io.h>
	11	#include <asm/arch/imx-regs.h>
	12	#include <asm/arch/sys_proto.h>
	13	#include <asm/arch/crm_regs.h>
	14	#include <asm/arch/clock.h>
	15	#include <asm/arch/iomux-mx53.h>
	16	#include <asm/mach-imx/mx5_video.h>
	17	#include <asm/mach-imx/video.h>
	18	#include <asm/gpio.h>
	19	#include <asm/spl.h>
	20	#include <fdt_support.h>
	21	#include <fsl_esdhc.h>
	22	#include <i2c.h>
	23	#include <ipu_pixfmt.h>
	24	#include <linux/errno.h>
	25	#include <linux/fb.h>
	26	#include <mmc.h>
	27	#include <netdev.h>
	28	#include <spl.h>
	29	#include <splash.h>
	30	#include <usb/ehci-ci.h>
	31
	32	DECLARE_GLOBAL_DATA_PTR;
	33
	34	static u32 mx53_dram_size[2];
	35
	36	ulong board_get_usable_ram_top(ulong total_size)
	37	{
	38	/*
	39	* WARNING: We must override get_effective_memsize() function here
	40	* to report only the size of the first DRAM bank. This is to make
	41	* U-Boot relocator place U-Boot into valid memory, that is, at the
	42	* end of the first DRAM bank. If we did not override this function
	43	* like so, U-Boot would be placed at the address of the first DRAM
	44	* bank + total DRAM size - sizeof(uboot), which in the setup where
	45	* each DRAM bank contains 512MiB of DRAM would result in placing
	46	* U-Boot into invalid memory area close to the end of the first
	47	* DRAM bank.
	48	*/
	49	return PHYS_SDRAM_2 + mx53_dram_size[1];
	50	}
	51
	52	int dram_init(void)
	53	{
	54	mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
	55	mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
	56
	57	gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
	58
	59	return 0;
	60	}
	61
	62	int dram_init_banksize(void)
	63	{
	64	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
65	gd->bd->bi_dram[0].size = mx53_dram_size[0];
66
67	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
68	gd->bd->bi_dram[1].size = mx53_dram_size[1];
69
70	return 0;
71	}
72
73	static void setup_iomux_uart(void)
74	{
75	static const iomux_v3_cfg_t uart_pads[] = {
76	MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
77	MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
78	};
79
80	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
81	}
82
83	#ifdef CONFIG_USB_EHCI_MX5
84	int board_ehci_hcd_init(int port)
85	{
86	if (port == 0) {
87	/* USB OTG PWRON */
88	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
89	PAD_CTL_PKE \|
90	PAD_CTL_DSE_HIGH));
9b352ae1	91	gpio_request(IMX_GPIO_NR(1, 4), "USB_OTG_PWRON");
39cb4f3c MV	92	gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
	93
	94	/* USB OTG Over Current */
	95	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13);
	96	} else if (port == 1) {
	97	/* USB Host PWRON */
	98	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
	99	PAD_CTL_PKE \|
	100	PAD_CTL_DSE_HIGH));
9b352ae1	101	gpio_request(IMX_GPIO_NR(1, 2), "USB_HOST_PWRON");
39cb4f3c MV	102	gpio_direction_output(IMX_GPIO_NR(1, 2), 0);
	103
	104	/* USB Host Over Current */
	105	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC);
	106	}
	107
	108	return 0;
	109	}
	110	#endif
	111
	112	static void setup_iomux_fec(void)
	113	{
	114	static const iomux_v3_cfg_t fec_pads[] = {
	115	/* MDIO pads */
	116	NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS \|
	117	PAD_CTL_DSE_HIGH \| PAD_CTL_PUS_22K_UP \| PAD_CTL_ODE),
	118	NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
	119
	120	/* FEC 0 pads */
	121	NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
	122	PAD_CTL_HYS \| PAD_CTL_PKE),
	123	NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
	124	PAD_CTL_HYS \| PAD_CTL_PKE),
	125	NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
	126	PAD_CTL_HYS \| PAD_CTL_PKE),
	127	NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
	128	NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
	129	PAD_CTL_HYS \| PAD_CTL_PKE),
	130	NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
	131	PAD_CTL_HYS \| PAD_CTL_PKE),
	132	NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
	133	NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
	134
	135	/* FEC 1 pads */
	136	NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
	137	PAD_CTL_HYS \| PAD_CTL_PKE),
	138	NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
	139	PAD_CTL_HYS \| PAD_CTL_PKE),
	140	NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
	141	PAD_CTL_HYS \| PAD_CTL_PKE),
	142	NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
	143	PAD_CTL_HYS \| PAD_CTL_PKE),
	144	NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
	145	PAD_CTL_HYS \| PAD_CTL_PKE),
	146	NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
	147	NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
	148	PAD_CTL_HYS \| PAD_CTL_PKE),
	149	NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
	150	};
	151
	152	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
	153	}
	154
	155	#ifdef CONFIG_FSL_ESDHC
	156	struct fsl_esdhc_cfg esdhc_cfg = {
	157	MMC_SDHC1_BASE_ADDR,
	158	};
	159
	160	int board_mmc_getcd(struct mmc *mmc)
	161	{
	162	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
	163	gpio_direction_input(IMX_GPIO_NR(1, 1));
	164
	165	return !gpio_get_value(IMX_GPIO_NR(1, 1));
166	}
167
168	#define SD_CMD_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_DSE_HIGH \| \
169	PAD_CTL_PUS_100K_UP)
170	#define SD_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_47K_UP \| \
171	PAD_CTL_DSE_HIGH)
172
173	int board_mmc_init(bd_t *bis)
174	{
175	static const iomux_v3_cfg_t sd1_pads[] = {
176	NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
177	NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
178	NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
179	NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
180	NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
181	NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
182	};
183
184	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
185
186	imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
187
188	return fsl_esdhc_initialize(bis, &esdhc_cfg);
189	}
190	#endif
191
192	#ifdef CONFIG_VIDEO
193	static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
194	{
195	static struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )MXC_CCM_BASE;
196	int ret;
197
198	/* For ETM0430G0DH6 model, this must be enabled before the clock. */
199	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
200
201	/*
202	* Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
203	* 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
204	*/
205	ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
206	if (ret)
207	puts("IPU: Failed to configure LDB clock\n");
208
209	/* Configure CCM_CSCMR2 */
210	clrsetbits_le32(&mxc_ccm->cscmr2,
211	(0x7 << 26) \| BIT(10) \| BIT(8),
212	(0x5 << 26) \| BIT(10) \| BIT(8));
213
214	/* Configure LDB_CTRL */
215	writel(0x201, 0x53fa8008);
216	}
217
218	static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
219	{
9b352ae1 MV	220	gpio_request(IMX_GPIO_NR(6, 0), "LCD");
9b352ae1 MV	221
39cb4f3c MV	222	/* For ETM0430G0DH6 model, this must be enabled before the clock. */
	223	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
	224
	225	/*
	226	* Set LVDS clock to 9 MHz for the display. The PLL4 is set to
	227	* 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
	228	*/
	229	enable_lvds_clock(dev, 63);
	230	}
	231
	232	static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
	233	{
9b352ae1 MV	234	gpio_request(IMX_GPIO_NR(6, 0), "LCD");
9b352ae1 MV	235
39cb4f3c MV	236	/*
	237	* Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
	238	* 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
	239	*/
	240	enable_lvds_clock(dev, 233);
	241
	242	/* For ETM0700G0DH6 model, this may be enabled after the clock. */
	243	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
	244	}
	245
	246	static const char *lvds_compat_string;
	247
	248	static int detect_lvds(struct display_info_t const *dev)
	249	{
	250	u8 touchid[23];
	251	u8 *touchptr = &touchid[0];
	252	int ret;
	253
	254	ret = i2c_set_bus_num(0);
	255	if (ret)
	256	return 0;
	257
	258	/* Touchscreen is at address 0x38, ID register is 0xbb. */
	259	ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
	260	if (ret)
	261	return 0;
	262
	263	/* EP0430 prefixes the response with 0xbb, skip it. */
	264	if (*touchptr == 0xbb)
	265	touchptr++;
	266
	267	/* Skip the 'EP' prefix. */
	268	touchptr += 2;
	269
	270	ret = !memcmp(touchptr, &dev->mode.name[7], 4);
	271	if (ret)
	272	lvds_compat_string = dev->mode.name;
	273
	274	return ret;
	275	}
	276
	277	void board_preboot_os(void)
	278	{
	279	/* Power off the LCD to prevent awful color flicker */
	280	gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
	281	}
	282
	283	int ft_board_setup(void blob, bd_t bd)
	284	{
	285	if (lvds_compat_string)
	286	do_fixup_by_path_string(blob, "/panel", "compatible",
	287	lvds_compat_string);
	288
	289	return 0;
	290	}
	291
	292	struct display_info_t const displays[] = {
	293	{
	294	.bus = 0,
	295	.addr = 0,
	296	.detect = detect_lvds,
	297	.enable = enable_lvds_etm0430g0dh6,
	298	.pixfmt = IPU_PIX_FMT_RGB666,
	299	.mode = {
300	.name = "edt,etm0430g0dh6",
301	.refresh = 60,
302	.xres = 480,
303	.yres = 272,
304	.pixclock = 111111, /* picosecond (9 MHz) */
305	.left_margin = 2,
306	.right_margin = 2,
307	.upper_margin = 2,
308	.lower_margin = 2,
309	.hsync_len = 41,
310	.vsync_len = 10,
311	.sync = 0x40000000,
312	.vmode = FB_VMODE_NONINTERLACED
313	}
314	}, {
315	.bus = 0,
316	.addr = 0,
317	.detect = detect_lvds,
318	.enable = enable_lvds_etm0700g0dh6,
319	.pixfmt = IPU_PIX_FMT_RGB666,
320	.mode = {
321	.name = "edt,etm0700g0dh6",
322	.refresh = 60,
323	.xres = 800,
324	.yres = 480,
325	.pixclock = 30048, /* picosecond (33.28 MHz) */
326	.left_margin = 40,
327	.right_margin = 88,
328	.upper_margin = 10,
329	.lower_margin = 33,
330	.hsync_len = 128,
331	.vsync_len = 2,
332	.sync = FB_SYNC_EXT,
333	.vmode = FB_VMODE_NONINTERLACED
334	}
335	}
336	};
337
338	size_t display_count = ARRAY_SIZE(displays);
339	#endif
340
341	#ifdef CONFIG_SPLASH_SCREEN
342	static struct splash_location default_splash_locations[] = {
343	{
344	.name = "mmc_fs",
345	.storage = SPLASH_STORAGE_MMC,
346	.flags = SPLASH_STORAGE_FS,
347	.devpart = "0:1",
348	},
349	};
350
351	int splash_screen_prepare(void)
352	{
353	return splash_source_load(default_splash_locations,
354	ARRAY_SIZE(default_splash_locations));
355	}
356	#endif
357
358	#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST \| PAD_CTL_DSE_HIGH \| \
359	PAD_CTL_PUS_100K_UP \| PAD_CTL_ODE)
360
361	static void setup_iomux_i2c(void)
362	{
363	static const iomux_v3_cfg_t i2c_pads[] = {
364	/* I2C1 */
365	NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
366	NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
367	/* I2C2 */
368	NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
369	NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
370	};
371
372	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
373	}
374
375	static void setup_iomux_video(void)
376	{
377	static const iomux_v3_cfg_t lcd_pads[] = {
378	MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
379	MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
380	MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
381	MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
382	MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
383	};
384
385	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
386	}
387
388	static void setup_iomux_nand(void)
389	{
390	static const iomux_v3_cfg_t nand_pads[] = {
391	NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
392	PAD_CTL_DSE_HIGH),
393	NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
394	PAD_CTL_DSE_HIGH),
395	NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
396	PAD_CTL_DSE_HIGH),
397	NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
398	PAD_CTL_DSE_HIGH),
399	NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
400	PAD_CTL_PUS_100K_UP),
401	NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
402	PAD_CTL_PUS_100K_UP),
403	NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
404	PAD_CTL_DSE_HIGH),
405	NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
406	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
407	NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
408	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
409	NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
410	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
411	NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
412	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
413	NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
414	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
415	NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
416	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
417	NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
418	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
419	NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
420	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
421	};
422
423	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
424	}
425
426	static void m53_set_clock(void)
427	{
428	int ret;
429	const u32 ref_clk = MXC_HCLK;
430	const u32 dramclk = 400;
431	u32 cpuclk;
432
9b352ae1 MV	433	gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK");
9b352ae1 MV	434
39cb4f3c MV	435	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
	436	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE));
	437	gpio_direction_input(IMX_GPIO_NR(4, 0));
	438
	439	/* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
	440	cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
	441
	442	ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
	443	if (ret)
	444	printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk);
	445
	446	ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
	447	if (ret) {
	448	printf("CPU: Switch peripheral clock to %dMHz failed\n",
	449	dramclk);
	450	}
	451
	452	ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
	453	if (ret)
	454	printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk);
	455	}
	456
	457	static void m53_set_nand(void)
	458	{
	459	u32 i;
	460
	461	/* NAND flash is muxed on ATA pins */
	462	setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
	463
	464	/* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
	465	for (i = 0x4; i < 0x94; i += 0x18) {
	466	clrbits_le32(WEIM_BASE_ADDR + i,
	467	WEIM_GCR2_MUX16_BYP_GRANT_MASK);
	468	}
	469
	470	mxc_set_clock(0, 33, MXC_NFC_CLK);
	471	enable_nfc_clk(1);
	472	}
	473
	474	int board_early_init_f(void)
	475	{
	476	setup_iomux_uart();
	477	setup_iomux_fec();
	478	setup_iomux_i2c();
	479	setup_iomux_nand();
	480	setup_iomux_video();
	481
	482	m53_set_clock();
	483
	484	mxc_set_sata_internal_clock();
	485
	486	/* NAND clock @ 33MHz */
	487	m53_set_nand();
	488
	489	return 0;
	490	}
	491
	492	int board_init(void)
	493	{
	494	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
	495
	496	return 0;
	497	}
	498
499	int checkboard(void)
500	{
501	puts("Board: Menlosystems M53Menlo\n");
502
503	return 0;
504	}
505
506	/*
507	* NAND SPL
508	*/
509	#ifdef CONFIG_SPL_BUILD
510	void spl_board_init(void)
511	{
512	setup_iomux_nand();
513	m53_set_clock();
514	m53_set_nand();
515	}
516
517	u32 spl_boot_device(void)
518	{
519	return BOOT_DEVICE_NAND;
520	}
521	#endif