[u-boot.git] / include / configs / versatile.h

/*
 * (C) Copyright 2003
 * Texas Instruments.
 * Kshitij Gupta <[email protected]>
 * Configuation settings for the TI OMAP Innovator board.
 *
 * (C) Copyright 2004
 * ARM Ltd.
 * Philippe Robin, <[email protected]>
 * Configuration for Versatile PB.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_ARM926EJS	1	/* This is an arm926ejs CPU core  */
#define CONFIG_VERSATILE	1	/* in Versatile Platform Board	*/
#define CONFIG_ARCH_VERSATILE   1	/* Specifically, a Versatile	*/


#define CFG_MEMTEST_START       0x100000
#define CFG_MEMTEST_END         0x10000000
#define CFG_HZ                  (1000000 / 256)
#define CFG_TIMERBASE           0x101E2000	/* Timer 0 and 1 base */

#define CFG_TIMER_INTERVAL	10000
#define CFG_TIMER_RELOAD	(CFG_TIMER_INTERVAL >> 4)	/* Divide by 16 */
#define CFG_TIMER_CTRL          0x84				/* Enable, Clock / 16 */

/*
 * control registers
 */
#define VERSATILE_SCTL_BASE            0x101E0000	/* System controller */

/*
 * System controller bit assignment
 */
#define VERSATILE_REFCLK	0
#define VERSATILE_TIMCLK	1

#define VERSATILE_TIMER1_EnSel	15
#define VERSATILE_TIMER2_EnSel	17
#define VERSATILE_TIMER3_EnSel	19
#define VERSATILE_TIMER4_EnSel	21

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs  */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_MISC_INIT_R		1	/* call misc_init_r during start up */
/*
 * Size of malloc() pool
 */
#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */

/*
 * Hardware drivers
 */

#define CONFIG_DRIVER_SMC91111
#define CONFIG_SMC_USE_32_BIT
#define CONFIG_SMC91111_BASE	0x10010000
#undef CONFIG_SMC91111_EXT_PHY

/*
 * NS16550 Configuration
 */
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK	24000000
#define CONFIG_PL01x_PORTS	{ (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
#define CONFIG_CONS_INDEX	0

#define CONFIG_BAUDRATE         38400
#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
#define CFG_SERIAL0		0x101F1000
#define CFG_SERIAL1		0x101F2000


/*
 * Command line configuration.
 */

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_IMI
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_BDI
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_ENV


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH


#define CONFIG_BOOTDELAY	2
#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=25,0,0xf1010000,0xf1010010,eth0"
/*#define CONFIG_BOOTCOMMAND "bootp ; bootm" */

/*
 * Static configuration when assigning fixed address
 */
/*#define CONFIG_NETMASK	255.255.255.0	/--* talk on MY local net */
/*#define CONFIG_IPADDR		xx.xx.xx.xx	/--* static IP I currently own */
/*#define CONFIG_SERVERIP	xx.xx.xx.xx	/--* current IP of my dev pc */
#define CONFIG_BOOTFILE	    "/tftpboot/uImage" /* file to load */


/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP	/* undef to save memory     */
#define CFG_PROMPT	"Versatile # "	/* Monitor Command Prompt   */
#define CFG_CBSIZE	256		/* Console I/O Buffer Size  */
/* Print Buffer Size */
#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
#define CFG_MAXARGS	16		/* max number of command args   */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size    */

#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR	0x7fc0	/* default load address */

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS    1	/* we have 1 bank of DRAM */
#define PHYS_SDRAM_1            0x00000000	/* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE       0x08000000	/* 128 MB */

#define CFG_FLASH_BASE          0x34000000

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

#define VERSATILE_SYS_BASE                    0x10000000
#define VERSATILE_SYS_FLASH_OFFSET            0x4C
#define VERSATILE_FLASHCTRL		      (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
#define VERSATILE_FLASHPROG_FLVPPEN	      (1 << 0)	/* Enable writing to flash */

#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
#define PHYS_FLASH_SIZE         0x34000000	/* 64MB */
/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Write */
#define CFG_MAX_FLASH_SECT	(256)

#define PHYS_FLASH_1		(CFG_FLASH_BASE)

#define CFG_ENV_IS_IN_FLASH     1               /* env in flash instead of CONFIG_ENV_IS_NOWHERE */
#define CFG_ENV_SECT_SIZE       0x00020000      /* 256 KB sectors (x2) */
#define CFG_ENV_SIZE            0x10000         /* Total Size of Environment Sector */
#define CFG_ENV_OFFSET          0x01f00000      /* environment starts here  */
#define CFG_ENV_ADDR            (CFG_FLASH_BASE + CFG_ENV_OFFSET)

#endif							/* __CONFIG_H */
Commit	Line	Data
3d3befa7 WD	1	/*
	2	* (C) Copyright 2003
	3	* Texas Instruments.
	4	* Kshitij Gupta <[email protected]>
	5	* Configuation settings for the TI OMAP Innovator board.
	6	*
	7	* (C) Copyright 2004
	8	* ARM Ltd.
	9	* Philippe Robin, <[email protected]>
	10	* Configuration for Versatile PB.
	11	*
	12	* See file CREDITS for list of people who contributed to this
	13	* project.
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License as
	17	* published by the Free Software Foundation; either version 2 of
	18	* the License, or (at your option) any later version.
	19	*
	20	* This program is distributed in the hope that it will be useful,
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
	24	*
	25	* You should have received a copy of the GNU General Public License
	26	* along with this program; if not, write to the Free Software
	27	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	28	* MA 02111-1307 USA
	29	*/
	30
	31	#ifndef __CONFIG_H
	32	#define __CONFIG_H
	33
	34	/*
	35	* High Level Configuration Options
	36	* (easy to change)
	37	*/
	38	#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
	39	#define CONFIG_VERSATILE 1 /* in Versatile Platform Board */
	40	#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */
	41
	42
	43	#define CFG_MEMTEST_START 0x100000
	44	#define CFG_MEMTEST_END 0x10000000
	45	#define CFG_HZ (1000000 / 256)
	46	#define CFG_TIMERBASE 0x101E2000 /* Timer 0 and 1 base */
	47
	48	#define CFG_TIMER_INTERVAL 10000
	49	#define CFG_TIMER_RELOAD (CFG_TIMER_INTERVAL >> 4) /* Divide by 16 */
	50	#define CFG_TIMER_CTRL 0x84 /* Enable, Clock / 16 */
	51
	52	/*
	53	* control registers
	54	*/
	55	#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
	56
	57	/*
	58	* System controller bit assignment
	59	*/
	60	#define VERSATILE_REFCLK 0
	61	#define VERSATILE_TIMCLK 1
	62
	63	#define VERSATILE_TIMER1_EnSel 15
	64	#define VERSATILE_TIMER2_EnSel 17
65	#define VERSATILE_TIMER3_EnSel 19
66	#define VERSATILE_TIMER4_EnSel 21
67
68	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
69	#define CONFIG_SETUP_MEMORY_TAGS 1
70	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */
71	/*
72	* Size of malloc() pool
73	*/
74	#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
42dfe7a1	75	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
3d3befa7 WD	76
	77	/*
	78	* Hardware drivers
	79	*/
	80
	81	#define CONFIG_DRIVER_SMC91111
	82	#define CONFIG_SMC_USE_32_BIT
53677ef1	83	#define CONFIG_SMC91111_BASE 0x10010000
3d3befa7 WD	84	#undef CONFIG_SMC91111_EXT_PHY
	85
	86	/*
	87	* NS16550 Configuration
	88	*/
48d0192f	89	#define CONFIG_PL011_SERIAL
6705d81e WD	90	#define CONFIG_PL011_CLOCK 24000000
6705d81e WD	91	#define CONFIG_PL01x_PORTS { (void )CFG_SERIAL0, (void )CFG_SERIAL1 }
3d3befa7	92	#define CONFIG_CONS_INDEX 0
6705d81e	93
3d3befa7 WD	94	#define CONFIG_BAUDRATE 38400
	95	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	96	#define CFG_SERIAL0 0x101F1000
	97	#define CFG_SERIAL1 0x101F2000
	98
3d3befa7	99
dca3b3d6 JL	100	/*
	101	* Command line configuration.
	102	*/
3d3befa7	103
dca3b3d6 JL	104	#define CONFIG_CMD_DHCP
	105	#define CONFIG_CMD_IMI
	106	#define CONFIG_CMD_NET
	107	#define CONFIG_CMD_PING
	108	#define CONFIG_CMD_BDI
	109	#define CONFIG_CMD_MEMORY
	110	#define CONFIG_CMD_FLASH
	111	#define CONFIG_CMD_ENV
3d3befa7	112
dca3b3d6	113
d3b8c1a7 JL	114	/*
	115	* BOOTP options
	116	*/
	117	#define CONFIG_BOOTP_SUBNETMASK
	118	#define CONFIG_BOOTP_GATEWAY
	119	#define CONFIG_BOOTP_HOSTNAME
	120	#define CONFIG_BOOTP_BOOTPATH
	121
3d3befa7 WD	122
3d3befa7 WD	123	#define CONFIG_BOOTDELAY 2
0b8fa03b	124	#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=25,0,0xf1010000,0xf1010010,eth0"
42dfe7a1	125	/#define CONFIG_BOOTCOMMAND "bootp ; bootm" /
3d3befa7 WD	126
	127	/*
	128	* Static configuration when assigning fixed address
	129	*/
42dfe7a1 WD	130	/#define CONFIG_NETMASK 255.255.255.0 /-- talk on MY local net */
	131	/#define CONFIG_IPADDR xx.xx.xx.xx /-- static IP I currently own */
	132	/#define CONFIG_SERVERIP xx.xx.xx.xx /-- current IP of my dev pc */
3d3befa7 WD	133	#define CONFIG_BOOTFILE "/tftpboot/uImage" /* file to load */
	134
	135
	136	/*
	137	* Miscellaneous configurable options
	138	*/
	139	#define CFG_LONGHELP /* undef to save memory */
	140	#define CFG_PROMPT "Versatile # " /* Monitor Command Prompt */
	141	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	142	/* Print Buffer Size */
	143	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
	144	#define CFG_MAXARGS 16 /* max number of command args */
	145	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	146
	147	#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
	148	#define CFG_LOAD_ADDR 0x7fc0 /* default load address */
	149
	150	/*-----------------------------------------------------------------------
	151	* Stack sizes
	152	*
	153	* The stack sizes are set up in start.S using the settings below
	154	*/
	155	#define CONFIG_STACKSIZE (1281024) / regular stack */
	156	#ifdef CONFIG_USE_IRQ
	157	#define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
	158	#define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
	159	#endif
	160
	161	/*-----------------------------------------------------------------------
	162	* Physical Memory Map
	163	*/
	164	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
	165	#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
	166	#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
	167
	168	#define CFG_FLASH_BASE 0x34000000
	169
	170	/*-----------------------------------------------------------------------
	171	* FLASH and environment organization
	172	*/
d407bf52 WD	173
	174	#define VERSATILE_SYS_BASE 0x10000000
	175	#define VERSATILE_SYS_FLASH_OFFSET 0x4C
	176	#define VERSATILE_FLASHCTRL (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
	177	#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */
	178
3d3befa7 WD	179	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	180	#define PHYS_FLASH_SIZE 0x34000000 /* 64MB */
	181	/* timeout values are in ticks */
	182	#define CFG_FLASH_ERASE_TOUT (20CFG_HZ) / Timeout for Flash Erase */
	183	#define CFG_FLASH_WRITE_TOUT (20CFG_HZ) / Timeout for Flash Write */
d407bf52	184	#define CFG_MAX_FLASH_SECT (256)
3d3befa7 WD	185
	186	#define PHYS_FLASH_1 (CFG_FLASH_BASE)
	187
93f6d725	188	#define CFG_ENV_IS_IN_FLASH 1 /* env in flash instead of CONFIG_ENV_IS_NOWHERE */
d407bf52 WD	189	#define CFG_ENV_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
	190	#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
	191	#define CFG_ENV_OFFSET 0x01f00000 /* environment starts here */
	192	#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
	193
3d3befa7	194	#endif /* __CONFIG_H */