[u-boot.git] / include / configs / DU440.h

/*
 * (C) Copyright 2008
 * Matthias Fuchs, esd gmbh, [email protected]
 *
 * based on the Sequoia board configuration by
 * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 **********************************************************************
 * DU440.h - configuration for esd's DU440 board (Power PC440EPx)
 **********************************************************************
 */
#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_DU440		1		/* Board is esd DU440	*/
#define CONFIG_440EPX		1		/* Specific PPC440EPx	*/
#define CONFIG_4xx		1		/* ... PPC4xx family	*/
#define CONFIG_SYS_CLK_FREQ	33333400	/* external freq to pll	*/

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFFFA0000
#endif

#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
#define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
#define CONFIG_LAST_STAGE_INIT  1               /* last_stage_init      */

/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(8 << 20)	/* Reserve 8 MB for malloc()  */

#define CONFIG_SYS_BOOT_BASE_ADDR	0xf0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
#define CONFIG_SYS_FLASH_BASE		0xfc000000	/* start of FLASH	*/
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND0_ADDR		0xd0000000      /* NAND Flash		*/
#define CONFIG_SYS_NAND1_ADDR		0xd0100000      /* NAND Flash		*/
#define CONFIG_SYS_OCM_BASE		0xe0010000      /* ocm			*/
#define CONFIG_SYS_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
#define CONFIG_SYS_PCI_MEMBASE1	CONFIG_SYS_PCI_MEMBASE  + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE2	CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE3	CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
#define CONFIG_SYS_PCI_IOBASE		0xe8000000
#define CONFIG_SYS_PCI_SUBSYS_VENDORID	PCI_VENDOR_ID_ESDGMBH
#define CONFIG_SYS_PCI_SUBSYS_ID	0x0444		/* device ID for DU440 */

#define CONFIG_SYS_USB2D0_BASE		0xe0000100
#define CONFIG_SYS_USB_DEVICE		0xe0000000
#define CONFIG_SYS_USB_HOST		0xe0000400

/*
 * Initial RAM & stack pointer
 */
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
#define CONFIG_SYS_INIT_RAM_OCM	1		/* OCM as init ram	*/
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/

#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK
#define CONFIG_BAUDRATE		115200

#define CONFIG_SYS_BAUDRATE_TABLE						\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

/*
 * Video Port
 */
#define CONFIG_VIDEO
#define CONFIG_VIDEO_SMI_LYNXEM
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_VIDEO_BMP_GZIP              /* gzip compressed bmp images */
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4 << 20)  /* for decompressed img */
#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x31a       /* 1280x1024,16bpp */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SYS_ISA_IO CONFIG_SYS_PCI_IOBASE

/*
 * Environment
 */
#define CONFIG_ENV_IS_IN_EEPROM    1	/* use FLASH for environment vars */

/*
 * FLASH related
 */
#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver       */

#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	      */
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip  */

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)    */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)    */

#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)   */
/* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection      */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash      */

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x20000 /* size of one complete sector        */
#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector   */

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif

#ifdef CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_ENV_OFFSET		0	/* environment starts at */
					/* the beginning of the EEPROM */
#define CONFIG_ENV_SIZE		0x1000 /* 4096 bytes may be used for env vars */
#endif

/*
 * DDR SDRAM
 */
#define CONFIG_SYS_MBYTES_SDRAM        (1024)	/* 512 MiB      TODO: remove    */
#define CONFIG_DDR_DATA_EYE		/* use DDR2 optimization        */
#define CONFIG_SYS_MEM_TOP_HIDE        (4 << 10) /* don't use last 4kbytes     */
					/* 440EPx errata CHIP 11        */
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup     */
#define CONFIG_DDR_ECC			/* Use ECC when available       */
#define SPD_EEPROM_ADDRESS	{0x50}
#define CONFIG_PROG_SDRAM_TLB

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
#define CONFIG_SYS_I2C_PPC4XX_CH1
#define CONFIG_SYS_I2C_PPC4XX_SPEED_1		100000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1		0x7F

#define CONFIG_SYS_SPD_BUS_NUM         0
#define IIC1_MCP3021_ADDR	0x4d
#define IIC1_USB2507_ADDR	0x2c
#define CONFIG_SYS_I2C_NOPROBES		{ {1, IIC1_USB2507_ADDR} }

#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x54
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01

#define CONFIG_SYS_EEPROM_WREN         1
#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52

/*
 * standard dtt sensor configuration - bottom bit will determine local or
 * remote sensor of the TMP401
 */
#define CONFIG_DTT_SENSORS		{ 0, 1 }

/*
 * The PMC440 uses a TI TMP401 temperature sensor. This part
 * is basically compatible to the ADM1021 that is supported
 * by U-Boot.
 *
 * - i2c addr 0x4c
 * - conversion rate 0x02 = 0.25 conversions/second
 * - ALERT ouput disabled
 * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
 * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
 */
#define CONFIG_DTT_ADM1021
#define CONFIG_SYS_DTT_ADM1021		{ { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }

/*
 * RTC stuff
 */
#define CONFIG_RTC_DS1338
#define CONFIG_SYS_I2C_RTC_ADDR	0x68

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"ethrotate=no\0"						\
	"hostname=du440\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"flash_self=run ramargs addip addtty optargs;"			\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;"	\
		"bootm\0"						\
	"rootpath=/tftpboot/du440/target_root_du440\0"			\
	"img=/tftpboot/du440/uImage\0"					\
	"kernel_addr=FFC00000\0"					\
	"ramdisk_addr=FFE00000\0"					\
	"initrd_high=30000000\0"					\
	"load=tftp 100000 /tftpboot/du440/u-boot.bin\0"			\
	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"	\
		"cp.b 100000 FFFA0000 60000\0"				\
	""

#define CONFIG_PREBOOT                  /* enable preboot variable      */

#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#ifndef __ASSEMBLY__
int du440_phy_addr(int devnum);
#endif

#define CONFIG_PPC4xx_EMAC
#define	CONFIG_IBM_EMAC4_V4	1
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		du440_phy_addr(0) /* PHY address	*/

#define CONFIG_PHY_RESET        1	/* reset phy upon startup	*/
#undef CONFIG_PHY_GIGE			/* no GbE detection		*/

#define CONFIG_HAS_ETH0
#define CONFIG_SYS_RX_ETH_BUFFER	128

#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
#define CONFIG_PHY1_ADDR	du440_phy_addr(1)

/*
 * USB
 */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_OHCI_BE_CONTROLLER

#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
#define CONFIG_SYS_USB_OHCI_REGS_BASE	CONFIG_SYS_USB_HOST
#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"du440"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15

/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BMP
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SOURCE
#define CONFIG_CMD_USB

#define CONFIG_SUPPORT_VFAT

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	        "=> "	/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
#endif
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00400000 /* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END		0x3f000000 /* 4 ... < 1GB DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */

#define CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks	*/

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CONFIG_LOOPW            1       /* enable loopw command         */
#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

#define CONFIG_AUTOBOOT_KEYED	1
#define CONFIG_AUTOBOOT_PROMPT	\
	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
#define CONFIG_AUTOBOOT_DELAY_STR "d"
#define CONFIG_AUTOBOOT_STOP_STR " "

/*
 * PCI stuff
 */
#define CONFIG_PCI			/* include pci support	        */
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
#define CONFIG_SYS_PCI_TARGBASE       0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/

/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT
#define CONFIG_SYS_PCI_MASTER_INIT

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)     /* Initial Memory map for Linux */

/*
 * External Bus Controller (EBC) Setup
 */
#define CONFIG_SYS_FLASH		CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_CPLD_BASE		0xC0000000
#define CONFIG_SYS_CPLD_RANGE	        0x00000010
#define CONFIG_SYS_DUMEM_BASE		0xC0100000
#define CONFIG_SYS_DUMEM_RANGE		0x00100000
#define CONFIG_SYS_DUIO_BASE		0xC0200000
#define CONFIG_SYS_DUIO_RANGE	        0x00010000

#define CONFIG_SYS_NAND0_CS		2		/* NAND chip connected to CSx */
#define CONFIG_SYS_NAND1_CS		3		/* NAND chip connected to CSx */
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP		0x04017200
#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH_BASE | 0xda000)

/* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
#define CONFIG_SYS_EBC_PB1AP		0x018003c0
#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_CPLD_BASE | 0x18000)

/* Memory Bank 2 (NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB2AP		0x018003c0
#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_NAND0_ADDR | 0x1c000)

/* Memory Bank 3 (NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB3AP		0x018003c0
#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_NAND1_ADDR | 0x1c000)

/* Memory Bank 4 (DUMEM, 1MB) initialization */
#define CONFIG_SYS_EBC_PB4AP		0x018053c0
#define CONFIG_SYS_EBC_PB4CR		(CONFIG_SYS_DUMEM_BASE | 0x18000)

/* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
#define CONFIG_SYS_EBC_PB5AP		0x018053c0
#define CONFIG_SYS_EBC_PB5CR		(CONFIG_SYS_DUIO_BASE | 0x18000)

/*
 * NAND FLASH
 */
#define CONFIG_SYS_MAX_NAND_DEVICE	2
#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips */
#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \
				 CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS}

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

#define CONFIG_SOURCE		1

#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP

#endif	/* __CONFIG_H */
Commit	Line	Data
1a3ac86b MF	1	/*
	2	* (C) Copyright 2008
	3	* Matthias Fuchs, esd gmbh, [email protected]
	4	*
	5	* based on the Sequoia board configuration by
	6	* Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
1a3ac86b MF	9	*/
	10
	11	/*
	12	**********************************************************************
	13	* DU440.h - configuration for esd's DU440 board (Power PC440EPx)
	14	**********************************************************************
	15	*/
	16	#ifndef __CONFIG_H
	17	#define __CONFIG_H
	18
	19	/*
	20	* High Level Configuration Options
	21	*/
	22	#define CONFIG_DU440 1 /* Board is esd DU440 */
	23	#define CONFIG_440EPX 1 /* Specific PPC440EPx */
	24	#define CONFIG_4xx 1 /* ... PPC4xx family */
	25	#define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */
	26
2ae18241 WD	27	#ifndef CONFIG_SYS_TEXT_BASE
	28	#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
	29	#endif
	30
1a3ac86b MF	31	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	32	#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
	33	#define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */
	34
	35	/*
	36	* Base addresses -- Note these are effective addresses where the
	37	* actual resources get mapped (not physical addresses)
	38	*/
6d0f6bcf JCPV	39	#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
	40	#define CONFIG_SYS_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */
	41
	42	#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
	43	#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
	44	#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
14d0a02a	45	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	46	#define CONFIG_SYS_NAND0_ADDR 0xd0000000 /* NAND Flash */
	47	#define CONFIG_SYS_NAND1_ADDR 0xd0100000 /* NAND Flash */
	48	#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
	49	#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
	50	#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
	51	#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
	52	#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
	53	#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
1095493a SR	54	#define CONFIG_SYS_PCI_IOBASE 0xe8000000
	55	#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
	56	#define CONFIG_SYS_PCI_SUBSYS_ID 0x0444 /* device ID for DU440 */
1a3ac86b	57
6d0f6bcf JCPV	58	#define CONFIG_SYS_USB2D0_BASE 0xe0000100
	59	#define CONFIG_SYS_USB_DEVICE 0xe0000000
	60	#define CONFIG_SYS_USB_HOST 0xe0000400
1a3ac86b MF	61
	62	/*
	63	* Initial RAM & stack pointer
	64	*/
	65	/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
6d0f6bcf JCPV	66	#define CONFIG_SYS_INIT_RAM_OCM 1 /* OCM as init ram */
6d0f6bcf JCPV	67	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
1a3ac86b	68
553f0982	69	#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
25ddd1fb	70	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	71	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
1a3ac86b MF	72
	73	/*
	74	* Serial Port
	75	*/
550650dd SR	76	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	77	#define CONFIG_SYS_NS16550
	78	#define CONFIG_SYS_NS16550_SERIAL
	79	#define CONFIG_SYS_NS16550_REG_SIZE 1
	80	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
6d0f6bcf	81	#undef CONFIG_SYS_EXT_SERIAL_CLOCK
1a3ac86b	82	#define CONFIG_BAUDRATE 115200
1a3ac86b	83
6d0f6bcf	84	#define CONFIG_SYS_BAUDRATE_TABLE \
1a3ac86b MF	85	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	86
	87	/*
	88	* Video Port
	89	*/
	90	#define CONFIG_VIDEO
	91	#define CONFIG_VIDEO_SMI_LYNXEM
	92	#define CONFIG_CFB_CONSOLE
	93	#define CONFIG_VIDEO_LOGO
	94	#define CONFIG_VGA_AS_SINGLE_DEVICE
	95	#define CONFIG_SPLASH_SCREEN
	96	#define CONFIG_SPLASH_SCREEN_ALIGN
	97	#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
6d0f6bcf JCPV	98	#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4 << 20) /* for decompressed img */
	99	#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x31a /* 1280x1024,16bpp */
	100	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	101	#define CONFIG_SYS_ISA_IO CONFIG_SYS_PCI_IOBASE
1a3ac86b MF	102
	103	/*
	104	* Environment
	105	*/
bb1f8b4f	106	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
1a3ac86b MF	107
	108	/*
	109	* FLASH related
	110	*/
6d0f6bcf	111	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a	112	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
1a3ac86b	113
6d0f6bcf	114	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
1a3ac86b	115
6d0f6bcf JCPV	116	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	117	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
1a3ac86b	118
6d0f6bcf JCPV	119	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	120	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
1a3ac86b	121
6d0f6bcf	122	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
1a3ac86b	123	/* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
6d0f6bcf	124	#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
1a3ac86b	125
6d0f6bcf JCPV	126	#define CONFIG_SYS_FLASH_EMPTY_INFO
6d0f6bcf JCPV	127	#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
1a3ac86b	128
5a1aceb0	129	#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586	130	#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
6d0f6bcf	131	#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
0e8d1586	132	#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
1a3ac86b MF	133
1a3ac86b MF	134	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	135	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	136	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
1a3ac86b MF	137	#endif
1a3ac86b MF	138
bb1f8b4f	139	#ifdef CONFIG_ENV_IS_IN_EEPROM
0e8d1586	140	#define CONFIG_ENV_OFFSET 0 /* environment starts at */
1a3ac86b	141	/* the beginning of the EEPROM */
0e8d1586	142	#define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
1a3ac86b MF	143	#endif
	144
	145	/*
	146	* DDR SDRAM
	147	*/
6d0f6bcf	148	#define CONFIG_SYS_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */
1a3ac86b	149	#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
6d0f6bcf	150	#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
02e38920	151	/* 440EPx errata CHIP 11 */
1a3ac86b	152	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
1a3ac86b MF	153	#define CONFIG_DDR_ECC /* Use ECC when available */
	154	#define SPD_EEPROM_ADDRESS {0x50}
	155	#define CONFIG_PROG_SDRAM_TLB
	156
	157	/*
	158	* I2C
	159	*/
880540de DE	160	#define CONFIG_SYS_I2C
	161	#define CONFIG_SYS_I2C_PPC4XX
	162	#define CONFIG_SYS_I2C_PPC4XX_CH0
	163	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
	164	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
	165	#define CONFIG_SYS_I2C_PPC4XX_CH1
	166	#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 100000
	167	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
1a3ac86b	168
6d0f6bcf	169	#define CONFIG_SYS_SPD_BUS_NUM 0
1a3ac86b MF	170	#define IIC1_MCP3021_ADDR 0x4d
1a3ac86b MF	171	#define IIC1_USB2507_ADDR 0x2c
880540de DE	172	#define CONFIG_SYS_I2C_NOPROBES { {1, IIC1_USB2507_ADDR} }
880540de DE	173
6d0f6bcf JCPV	174	#define CONFIG_SYS_I2C_MULTI_EEPROMS
	175	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
	176	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	177	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
	178	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
	179	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
1a3ac86b	180
6d0f6bcf JCPV	181	#define CONFIG_SYS_EEPROM_WREN 1
6d0f6bcf JCPV	182	#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
1a3ac86b MF	183
	184	/*
	185	* standard dtt sensor configuration - bottom bit will determine local or
	186	* remote sensor of the TMP401
	187	*/
	188	#define CONFIG_DTT_SENSORS { 0, 1 }
	189
	190	/*
	191	* The PMC440 uses a TI TMP401 temperature sensor. This part
	192	* is basically compatible to the ADM1021 that is supported
	193	* by U-Boot.
	194	*
	195	* - i2c addr 0x4c
	196	* - conversion rate 0x02 = 0.25 conversions/second
	197	* - ALERT ouput disabled
	198	* - local temp sensor enabled, min set to 0 deg, max set to 70 deg
	199	* - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
	200	*/
	201	#define CONFIG_DTT_ADM1021
6d0f6bcf	202	#define CONFIG_SYS_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
1a3ac86b MF	203
	204	/*
	205	* RTC stuff
	206	*/
	207	#define CONFIG_RTC_DS1338
6d0f6bcf	208	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
1a3ac86b MF	209
	210	#undef CONFIG_BOOTARGS
	211
	212	#define CONFIG_EXTRA_ENV_SETTINGS \
	213	"netdev=eth0\0" \
	214	"ethrotate=no\0" \
	215	"hostname=du440\0" \
	216	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	217	"nfsroot=${serverip}:${rootpath}\0" \
	218	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	219	"addip=setenv bootargs ${bootargs} " \
	220	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	221	":${hostname}:${netdev}:off panic=1\0" \
	222	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	223	"flash_self=run ramargs addip addtty optargs;" \
	224	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	225	"net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;" \
93e14596	226	"bootm\0" \
1a3ac86b MF	227	"rootpath=/tftpboot/du440/target_root_du440\0" \
	228	"img=/tftpboot/du440/uImage\0" \
	229	"kernel_addr=FFC00000\0" \
	230	"ramdisk_addr=FFE00000\0" \
	231	"initrd_high=30000000\0" \
	232	"load=tftp 100000 /tftpboot/du440/u-boot.bin\0" \
	233	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
	234	"cp.b 100000 FFFA0000 60000\0" \
	235	""
1a3ac86b MF	236
	237	#define CONFIG_PREBOOT /* enable preboot variable */
	238
	239	#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
	240
	241	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	242	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
1a3ac86b MF	243
	244	#ifndef __ASSEMBLY__
	245	int du440_phy_addr(int devnum);
	246	#endif
	247
96e21f86	248	#define CONFIG_PPC4xx_EMAC
1a3ac86b MF	249	#define CONFIG_IBM_EMAC4_V4 1
	250	#define CONFIG_MII 1 /* MII PHY management */
	251	#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */
	252
	253	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
7c91f51a	254	#undef CONFIG_PHY_GIGE /* no GbE detection */
1a3ac86b MF	255
1a3ac86b MF	256	#define CONFIG_HAS_ETH0
6d0f6bcf	257	#define CONFIG_SYS_RX_ETH_BUFFER 128
1a3ac86b	258
1a3ac86b MF	259	#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
	260	#define CONFIG_PHY1_ADDR du440_phy_addr(1)
	261
	262	/*
	263	* USB
	264	*/
	265	#define CONFIG_USB_OHCI_NEW
	266	#define CONFIG_USB_STORAGE
6d0f6bcf	267	#define CONFIG_SYS_OHCI_BE_CONTROLLER
1a3ac86b	268
6d0f6bcf JCPV	269	#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
	270	#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
	271	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "du440"
	272	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
1a3ac86b MF	273
	274	/* Comment this out to enable USB 1.1 device */
	275	#define USB_2_0_DEVICE
	276
	277	/* Partitions */
	278	#define CONFIG_MAC_PARTITION
	279	#define CONFIG_DOS_PARTITION
	280	#define CONFIG_ISO_PARTITION
	281
	282	#include <config_cmd_default.h>
	283
74de7aef	284	#define CONFIG_CMD_ASKENV
7c91f51a	285	#define CONFIG_CMD_BMP
74de7aef	286	#define CONFIG_CMD_BSP
1a3ac86b	287	#define CONFIG_CMD_DATE
1a3ac86b	288	#define CONFIG_CMD_DHCP
1a3ac86b	289	#define CONFIG_CMD_DIAG
74de7aef	290	#define CONFIG_CMD_DTT
1a3ac86b MF	291	#define CONFIG_CMD_EEPROM
	292	#define CONFIG_CMD_ELF
	293	#define CONFIG_CMD_FAT
	294	#define CONFIG_CMD_I2C
	295	#define CONFIG_CMD_IRQ
	296	#define CONFIG_CMD_MII
	297	#define CONFIG_CMD_NAND
	298	#define CONFIG_CMD_NET
	299	#define CONFIG_CMD_NFS
	300	#define CONFIG_CMD_PCI
	301	#define CONFIG_CMD_PING
1a3ac86b MF	302	#define CONFIG_CMD_REGINFO
1a3ac86b MF	303	#define CONFIG_CMD_SDRAM
74de7aef WD	304	#define CONFIG_CMD_SOURCE
74de7aef WD	305	#define CONFIG_CMD_USB
1a3ac86b MF	306
	307	#define CONFIG_SUPPORT_VFAT
	308
	309	/*
	310	* Miscellaneous configurable options
	311	*/
6d0f6bcf JCPV	312	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	313	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
1a3ac86b	314	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	315	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
1a3ac86b	316	#else
6d0f6bcf	317	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
1a3ac86b MF	318	#endif
1a3ac86b MF	319	/* Print Buffer Size */
6d0f6bcf JCPV	320	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	321	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	322	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
1a3ac86b	323
6d0f6bcf JCPV	324	#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
6d0f6bcf JCPV	325	#define CONFIG_SYS_MEMTEST_END 0x3f000000 /* 4 ... < 1GB DRAM */
1a3ac86b	326
6d0f6bcf JCPV	327	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	328	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
1a3ac86b	329
6d0f6bcf	330	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
1a3ac86b MF	331
	332	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
	333	#define CONFIG_LOOPW 1 /* enable loopw command */
	334	#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
	335	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	336	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
	337
c37207d7 WD	338	#define CONFIG_AUTOBOOT_KEYED 1
	339	#define CONFIG_AUTOBOOT_PROMPT \
	340	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
1a3ac86b MF	341	#define CONFIG_AUTOBOOT_DELAY_STR "d"
	342	#define CONFIG_AUTOBOOT_STOP_STR " "
	343
	344	/*
	345	* PCI stuff
	346	*/
	347	#define CONFIG_PCI /* include pci support */
842033e6	348	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
1a3ac86b MF	349	#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
1a3ac86b MF	350	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	351	#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
1a3ac86b MF	352
1a3ac86b MF	353	/* Board-specific PCI */
6d0f6bcf JCPV	354	#define CONFIG_SYS_PCI_TARGET_INIT
6d0f6bcf JCPV	355	#define CONFIG_SYS_PCI_MASTER_INIT
1a3ac86b MF	356
	357	/*
	358	* For booting Linux, the board info and command line data
	359	* have to be in the first 8 MB of memory, since this is
	360	* the maximum mapped by the Linux kernel during initialization.
	361	*/
6d0f6bcf	362	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
1a3ac86b MF	363
	364	/*
	365	* External Bus Controller (EBC) Setup
	366	*/
6d0f6bcf	367	#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
1a3ac86b	368
6d0f6bcf JCPV	369	#define CONFIG_SYS_CPLD_BASE 0xC0000000
	370	#define CONFIG_SYS_CPLD_RANGE 0x00000010
	371	#define CONFIG_SYS_DUMEM_BASE 0xC0100000
	372	#define CONFIG_SYS_DUMEM_RANGE 0x00100000
	373	#define CONFIG_SYS_DUIO_BASE 0xC0200000
	374	#define CONFIG_SYS_DUIO_RANGE 0x00010000
1a3ac86b	375
6d0f6bcf JCPV	376	#define CONFIG_SYS_NAND0_CS 2 /* NAND chip connected to CSx */
6d0f6bcf JCPV	377	#define CONFIG_SYS_NAND1_CS 3 /* NAND chip connected to CSx */
1a3ac86b	378	/* Memory Bank 0 (NOR-FLASH) initialization */
6d0f6bcf JCPV	379	#define CONFIG_SYS_EBC_PB0AP 0x04017200
6d0f6bcf JCPV	380	#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE \| 0xda000)
1a3ac86b MF	381
1a3ac86b MF	382	/* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
6d0f6bcf JCPV	383	#define CONFIG_SYS_EBC_PB1AP 0x018003c0
6d0f6bcf JCPV	384	#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE \| 0x18000)
1a3ac86b MF	385
1a3ac86b MF	386	/* Memory Bank 2 (NAND-FLASH) initialization */
6d0f6bcf JCPV	387	#define CONFIG_SYS_EBC_PB2AP 0x018003c0
6d0f6bcf JCPV	388	#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND0_ADDR \| 0x1c000)
1a3ac86b MF	389
1a3ac86b MF	390	/* Memory Bank 3 (NAND-FLASH) initialization */
6d0f6bcf JCPV	391	#define CONFIG_SYS_EBC_PB3AP 0x018003c0
6d0f6bcf JCPV	392	#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND1_ADDR \| 0x1c000)
1a3ac86b MF	393
1a3ac86b MF	394	/* Memory Bank 4 (DUMEM, 1MB) initialization */
6d0f6bcf JCPV	395	#define CONFIG_SYS_EBC_PB4AP 0x018053c0
6d0f6bcf JCPV	396	#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_DUMEM_BASE \| 0x18000)
1a3ac86b MF	397
1a3ac86b MF	398	/* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
6d0f6bcf JCPV	399	#define CONFIG_SYS_EBC_PB5AP 0x018053c0
6d0f6bcf JCPV	400	#define CONFIG_SYS_EBC_PB5CR (CONFIG_SYS_DUIO_BASE \| 0x18000)
1a3ac86b MF	401
	402	/*
	403	* NAND FLASH
	404	*/
6d0f6bcf	405	#define CONFIG_SYS_MAX_NAND_DEVICE 2
6d0f6bcf JCPV	406	#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
	407	#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \
	408	CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS}
1a3ac86b	409
1a3ac86b MF	410	#if defined(CONFIG_CMD_KGDB)
	411	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	412	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	413	#endif
	414
74de7aef	415	#define CONFIG_SOURCE 1
1a3ac86b	416
35dd025c MF	417	#define CONFIG_OF_LIBFDT
	418	#define CONFIG_OF_BOARD_SETUP
	419
1a3ac86b	420	#endif /* __CONFIG_H */