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e53b507c SR |
1 | /* |
2 | * (C) Copyright 2009 Wolfgang Denk <wd@denx.de> | |
3 | * (C) Copyright 2009, DAVE Srl <www.dave.eu> | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | * | |
23 | * modifications for the MECP5123 by reinhard.arlt@esd-electronics.com | |
24 | * | |
25 | */ | |
26 | ||
27 | /* | |
28 | * MECP5123 board configuration file | |
29 | */ | |
30 | ||
31 | #ifndef __CONFIG_H | |
32 | #define __CONFIG_H | |
33 | ||
34 | #define CONFIG_MECP5123 1 | |
35 | /* | |
36 | * Memory map for the MECP5123 board: | |
37 | * | |
38 | * 0x0000_0000 - 0x1FFF_FFFF DDR RAM (512 MB) | |
39 | * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) | |
40 | * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) | |
41 | * 0x8200_0000 - 0x8200_FFFF VPC-3 (64 KB) | |
42 | * 0xFFC0_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) | |
43 | */ | |
44 | ||
45 | /* | |
46 | * High Level Configuration Options | |
47 | */ | |
48 | #define CONFIG_E300 1 /* E300 Family */ | |
49 | #define CONFIG_MPC512X 1 /* MPC512X family */ | |
50 | ||
51 | #define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ | |
52 | ||
53 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ | |
54 | #define CONFIG_MISC_INIT_R | |
55 | ||
56 | #define CONFIG_SYS_IMMR 0x80000000 | |
57 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100) | |
58 | ||
59 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ | |
60 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
61 | ||
62 | /* | |
63 | * DDR Setup - manually set all parameters as there's no SPD etc. | |
64 | */ | |
65 | #define CONFIG_SYS_DDR_SIZE 512 /* MB */ | |
66 | ||
67 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ | |
68 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
69 | ||
70 | /* DDR Controller Configuration | |
71 | * | |
72 | * SYS_CFG: | |
73 | * [31:31] MDDRC Soft Reset: Diabled | |
74 | * [30:30] DRAM CKE pin: Enabled | |
75 | * [29:29] DRAM CLK: Enabled | |
76 | * [28:28] Command Mode: Enabled (For initialization only) | |
77 | * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] | |
78 | * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] | |
79 | * [20:19] Read Test: DON'T USE | |
80 | * [18:18] Self Refresh: Enabled | |
81 | * [17:17] 16bit Mode: Disabled | |
82 | * [16:13] Ready Delay: 2 | |
83 | * [12:12] Half DQS Delay: Disabled | |
84 | * [11:11] Quarter DQS Delay: Disabled | |
85 | * [10:08] Write Delay: 2 | |
86 | * [07:07] Early ODT: Disabled | |
87 | * [06:06] On DIE Termination: Disabled | |
88 | * [05:05] FIFO Overflow Clear: DON'T USE here | |
89 | * [04:04] FIFO Underflow Clear: DON'T USE here | |
90 | * [03:03] FIFO Overflow Pending: DON'T USE here | |
91 | * [02:02] FIFO Underlfow Pending: DON'T USE here | |
92 | * [01:01] FIFO Overlfow Enabled: Enabled | |
93 | * [00:00] FIFO Underflow Enabled: Enabled | |
94 | * TIME_CFG0 | |
95 | * [31:16] DRAM Refresh Time: 0 CSB clocks | |
96 | * [15:8] DRAM Command Time: 0 CSB clocks | |
97 | * [07:00] DRAM Precharge Time: 0 CSB clocks | |
98 | * TIME_CFG1 | |
99 | * [31:26] DRAM tRFC: | |
100 | * [25:21] DRAM tWR1: | |
101 | * [20:17] DRAM tWRT1: | |
102 | * [16:11] DRAM tDRR: | |
103 | * [10:05] DRAM tRC: | |
104 | * [04:00] DRAM tRAS: | |
105 | * TIME_CFG2 | |
106 | * [31:28] DRAM tRCD: | |
107 | * [27:23] DRAM tFAW: | |
108 | * [22:19] DRAM tRTW1: | |
109 | * [18:15] DRAM tCCD: | |
110 | * [14:10] DRAM tRTP: | |
111 | * [09:05] DRAM tRP: | |
112 | * [04:00] DRAM tRPA | |
113 | */ | |
114 | #ifdef CONFIG_ADS5121_REV2 | |
115 | #define CONFIG_SYS_MDDRC_SYS_CFG 0xF8604A00 | |
116 | #define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00 | |
117 | #define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 | |
118 | #define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 | |
119 | #else | |
120 | #define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00 | |
121 | #define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00 | |
122 | #define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 | |
123 | #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 | |
124 | #endif | |
125 | #define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 | |
126 | #define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E | |
127 | #define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E | |
128 | ||
129 | #define CONFIG_SYS_MICRON_NOP 0x01380000 | |
130 | #define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 | |
131 | #define CONFIG_SYS_MICRON_EM2 0x01020000 | |
132 | #define CONFIG_SYS_MICRON_EM3 0x01030000 | |
133 | #define CONFIG_SYS_MICRON_EN_DLL 0x01010000 | |
134 | #define CONFIG_SYS_MICRON_RFSH 0x01080000 | |
135 | #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 | |
136 | #define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780 | |
137 | ||
138 | /* DDR Priority Manager Configuration */ | |
139 | #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 | |
140 | #define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 | |
141 | #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 | |
142 | #define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC | |
143 | #define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA | |
144 | #define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 | |
145 | #define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 | |
146 | #define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 | |
147 | #define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 | |
148 | #define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 | |
149 | #define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 | |
150 | #define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 | |
151 | #define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 | |
152 | #define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa | |
153 | #define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa | |
154 | #define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 | |
155 | #define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 | |
156 | #define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 | |
157 | #define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 | |
158 | #define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 | |
159 | #define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 | |
160 | #define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 | |
161 | #define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 | |
162 | ||
163 | /* | |
164 | * NOR FLASH on the Local Bus | |
165 | */ | |
166 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ | |
167 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
168 | ||
169 | #define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of FLASH */ | |
170 | #define CONFIG_SYS_FLASH_SIZE 0x00400000 /* max flash size */ | |
171 | ||
172 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
173 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
174 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} | |
175 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
176 | ||
177 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
178 | ||
179 | /* | |
180 | * NAND FLASH | |
181 | * drivers/mtd/nand/mpc5121_mpc.c (rev 2 silicon only) | |
182 | */ | |
183 | #define CONFIG_CMD_NAND | |
184 | #define CONFIG_NAND_MPC5121_NFC | |
185 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
186 | ||
187 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
188 | #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE | |
189 | ||
190 | /* | |
191 | * Configuration parameters for MPC5121 NAND driver | |
192 | */ | |
193 | #define CONFIG_FSL_NFC_WIDTH 1 | |
194 | #define CONFIG_FSL_NFC_WRITE_SIZE 2048 | |
195 | #define CONFIG_FSL_NFC_SPARE_SIZE 64 | |
196 | #define CONFIG_FSL_NFC_CHIPS 1 | |
197 | ||
198 | #define CONFIG_SYS_SRAM_BASE 0x30000000 | |
199 | #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ | |
200 | ||
201 | /* ALE active low, data size 4bytes */ | |
202 | #define CONFIG_SYS_CS0_CFG 0x05051150 | |
203 | ||
204 | /* Use not alternative CS timing */ | |
205 | #define CONFIG_SYS_CS_ALETIMING 0x00000000 | |
206 | ||
207 | /* ALE active low, data size 4bytes */ | |
208 | #define CONFIG_SYS_CS1_CFG 0x1f1f3090 | |
209 | #define CONFIG_SYS_VPC3_BASE 0x82000000 /* start of VPC3 space */ | |
210 | #define CONFIG_SYS_VPC3_SIZE 0x00010000 /* max VPC3 size */ | |
211 | ||
212 | /* Use SRAM for initial stack */ | |
213 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Init RAM addr */ | |
214 | #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE | |
215 | ||
216 | #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ | |
217 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
218 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
219 | ||
220 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */ | |
221 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Monitor length */ | |
222 | #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Malloc size */ | |
223 | ||
224 | /* | |
225 | * Serial Port | |
226 | */ | |
227 | #define CONFIG_CONS_INDEX 1 | |
228 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
229 | ||
230 | /* | |
231 | * Serial console configuration | |
232 | */ | |
233 | #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ | |
234 | #if CONFIG_PSC_CONSOLE != 3 | |
235 | #error CONFIG_PSC_CONSOLE must be 3 | |
236 | #endif | |
237 | #define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */ | |
238 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
239 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
240 | ||
241 | #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE | |
242 | #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR | |
243 | #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE | |
244 | #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR | |
245 | ||
246 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
247 | /* Use the HUSH parser */ | |
248 | #define CONFIG_SYS_HUSH_PARSER | |
249 | #ifdef CONFIG_SYS_HUSH_PARSER | |
250 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
251 | #endif | |
252 | ||
253 | /* I2C */ | |
254 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
255 | #undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */ | |
256 | #define CONFIG_I2C_MULTI_BUS | |
257 | #define CONFIG_I2C_CMD_TREE | |
258 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */ | |
259 | #define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */ | |
260 | ||
261 | /* | |
262 | * IIM - IC Identification Module | |
263 | */ | |
264 | #undef CONFIG_IIM | |
265 | ||
266 | /* | |
267 | * EEPROM configuration | |
268 | */ | |
269 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ | |
270 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */ | |
271 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */ | |
272 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */ | |
273 | #define CONFIG_SYS_EEPROM_WREN /* Use EEPROM write protect */ | |
274 | ||
275 | /* | |
276 | * Ethernet configuration | |
277 | */ | |
278 | #define CONFIG_MPC512x_FEC 1 | |
279 | #define CONFIG_NET_MULTI | |
280 | #define CONFIG_PHY_ADDR 0x1 | |
281 | #define CONFIG_MII 1 /* MII PHY management */ | |
282 | #define CONFIG_FEC_AN_TIMEOUT 1 | |
283 | #define CONFIG_HAS_ETH0 | |
284 | ||
285 | /* | |
286 | * Configure on-board RTC | |
287 | */ | |
288 | #define CONFIG_SYS_RTC_BUS_NUM 0x01 | |
289 | #define CONFIG_SYS_I2C_RTC_ADDR 0x32 | |
290 | #define CONFIG_RTC_RX8025 | |
291 | ||
292 | /* | |
293 | * Environment | |
294 | */ | |
295 | #define CONFIG_ENV_IS_IN_EEPROM /* Store env in I2C EEPROM */ | |
296 | #define CONFIG_ENV_SIZE 0x1000 | |
297 | #define CONFIG_ENV_OFFSET 0x0000 /* environment starts here */ | |
298 | ||
299 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
300 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
301 | ||
302 | #include <config_cmd_default.h> | |
303 | ||
304 | #define CONFIG_CMD_ASKENV | |
305 | #define CONFIG_CMD_DHCP | |
306 | #define CONFIG_CMD_I2C | |
307 | #define CONFIG_CMD_MII | |
308 | #define CONFIG_CMD_NFS | |
309 | #define CONFIG_CMD_PING | |
310 | #define CONFIG_CMD_REGINFO | |
311 | #define CONFIG_CMD_EEPROM | |
312 | #define CONFIG_CMD_DATE | |
313 | #undef CONFIG_CMD_FUSE | |
314 | #undef CONFIG_CMD_IDE | |
315 | #undef CONFIG_CMD_EXT2 | |
316 | #define CONFIG_CMD_FAT | |
317 | #define CONFIG_CMD_JFFS2 | |
318 | #define CONFIG_CMD_ELF | |
319 | #define CONFIG_DOS_PARTITION | |
320 | ||
321 | /* | |
322 | * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. | |
323 | * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set | |
324 | * to 0xFFFF, watchdog timeouts after about 64s. For details refer | |
325 | * to chapter 36 of the MPC5121e Reference Manual. | |
326 | */ | |
327 | /* #define CONFIG_WATCHDOG */ /* enable watchdog */ | |
328 | #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF | |
329 | ||
330 | /* | |
331 | * Miscellaneous configurable options | |
332 | */ | |
333 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
334 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
335 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
336 | ||
337 | #ifdef CONFIG_CMD_KGDB | |
338 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
339 | #else | |
340 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
341 | #endif | |
342 | ||
343 | /* Print Buffer Size */ | |
344 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
345 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
346 | /* max number of command args */ | |
347 | #define CONFIG_SYS_MAXARGS 32 | |
348 | /* Boot Argument Buffer Size */ | |
349 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
350 | ||
351 | #define CONFIG_SYS_HZ 1000 | |
352 | ||
353 | /* | |
354 | * For booting Linux, the board info and command line data | |
355 | * have to be in the first 8 MB of memory, since this is | |
356 | * the maximum mapped by the Linux kernel during initialization. | |
357 | */ | |
358 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Linux initial memory map */ | |
359 | ||
360 | /* Cache Configuration */ | |
361 | #define CONFIG_SYS_DCACHE_SIZE 32768 | |
362 | #define CONFIG_SYS_CACHELINE_SIZE 32 | |
363 | #ifdef CONFIG_CMD_KGDB | |
364 | #define CONFIG_SYS_CACHELINE_SHIFT 5 | |
365 | #endif | |
366 | ||
367 | #define CONFIG_SYS_HID0_INIT 0x000000000 | |
368 | #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK | |
369 | #define CONFIG_SYS_HID2 HID2_HBE | |
370 | ||
371 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ | |
372 | ||
373 | /* | |
374 | * Internal Definitions | |
375 | * | |
376 | * Boot Flags | |
377 | */ | |
378 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
379 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
380 | ||
381 | #ifdef CONFIG_CMD_KGDB | |
382 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
383 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
384 | #endif | |
385 | ||
386 | /* | |
387 | * Environment Configuration | |
388 | */ | |
389 | #define CONFIG_TIMESTAMP | |
390 | ||
391 | #define CONFIG_HOSTNAME mecp512x | |
392 | #define CONFIG_BOOTFILE /tftpboot/mecp512x/uImage | |
393 | #define CONFIG_ROOTPATH /tftpboot/mecp512x/target_root | |
394 | ||
395 | #define CONFIG_LOADADDR 400000 /* def. location for tftp and bootm */ | |
396 | ||
397 | #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ | |
398 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ | |
399 | ||
400 | #define CONFIG_PREBOOT "echo;" \ | |
401 | "echo Welcome to MECP5123" \ | |
402 | "echo" | |
403 | ||
404 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
405 | "u-boot_addr_r=200000\0" \ | |
406 | "kernel_addr_r=600000\0" \ | |
407 | "fdt_addr_r=880000\0" \ | |
408 | "ramdisk_addr_r=900000\0" \ | |
409 | "u-boot_addr=FFF00000\0" \ | |
410 | "kernel_addr=FFC40000\0" \ | |
411 | "fdt_addr=FFEC0000\0" \ | |
412 | "ramdisk_addr=FC040000\0" \ | |
413 | "ramdiskfile=/tftpboot/mecp512x/uRamdisk\0" \ | |
414 | "u-boot=/tftpboot/mecp512x/u-boot.bin\0" \ | |
415 | "bootfile=/tftpboot/mecp512x/uImage\0" \ | |
416 | "fdtfile=/tftpboot/mecp512x/mecp512x.dtb\0" \ | |
417 | "rootpath=/tftpboot/mecp512x/target_root\n" \ | |
418 | "netdev=eth0\0" \ | |
419 | "consdev=ttyPSC0\0" \ | |
420 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
421 | "nfsroot=${serverip}:${rootpath}\0" \ | |
422 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
423 | "addip=setenv bootargs ${bootargs} " \ | |
424 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
425 | ":${hostname}:${netdev}:off panic=1\0" \ | |
426 | "addtty=setenv bootargs ${bootargs} " \ | |
427 | "console=${consdev},${baudrate}\0" \ | |
428 | "flash_nfs=run nfsargs addip addtty;" \ | |
429 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ | |
430 | "flash_self=run ramargs addip addtty;" \ | |
431 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ | |
432 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ | |
433 | "tftp ${fdt_addr_r} ${fdtfile};" \ | |
434 | "run nfsargs addip addtty;" \ | |
435 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
436 | "net_self=tftp ${kernel_addr_r} ${bootfile};" \ | |
437 | "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ | |
438 | "tftp ${fdt_addr_r} ${fdtfile};" \ | |
439 | "run ramargs addip addtty;" \ | |
440 | "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ | |
441 | "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ | |
442 | "update=protect off ${u-boot_addr} +${filesize};" \ | |
443 | "era ${u-boot_addr} +${filesize};" \ | |
444 | "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ | |
445 | "upd=run load update\0" \ | |
446 | "" | |
447 | ||
448 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
449 | ||
450 | #define CONFIG_OF_LIBFDT | |
451 | #define CONFIG_OF_BOARD_SETUP | |
452 | ||
453 | #define OF_CPU "PowerPC,5121@0" | |
454 | #define OF_SOC_COMPAT "fsl,mpc5121-immr" | |
455 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
456 | #define OF_STDOUT_PATH "/soc@80000000/serial@11300" | |
457 | ||
458 | #endif /* __CONFIG_H */ |