[u-boot.git] / drivers / mmc / gen_atmel_mci.c

/*
 * Copyright (C) 2010
 * Rob Emanuele <[email protected]>
 * Reinhard Meyer, EMK Elektronik <[email protected]>
 *
 * Original Driver:
 * Copyright (C) 2004-2006 Atmel Corporation
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mmc.h>
#include <part.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/byteorder.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include "atmel_mci.h"

#ifndef CONFIG_SYS_MMC_CLK_OD
# define CONFIG_SYS_MMC_CLK_OD	150000
#endif

#define MMC_DEFAULT_BLKLEN	512

#if defined(CONFIG_ATMEL_MCI_PORTB)
# define MCI_BUS 1
#else
# define MCI_BUS 0
#endif

struct atmel_mci_priv {
	struct mmc_config	cfg;
	struct atmel_mci	*mci;
	unsigned int		initialized:1;
	unsigned int		curr_clk;
};

/* Read Atmel MCI IP version */
static unsigned int atmel_mci_get_version(struct atmel_mci *mci)
{
	return readl(&mci->version) & 0x00000fff;
}

/*
 * Print command and status:
 *
 * - always when DEBUG is defined
 * - on command errors
 */
static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg)
{
	debug("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n",
	      cmdr, cmdr & 0x3F, arg, status, msg);
}

/* Setup for MCI Clock and Block Size */
static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
{
	struct atmel_mci_priv *priv = mmc->priv;
	atmel_mci_t *mci = priv->mci;
	u32 bus_hz = get_mci_clk_rate();
	u32 clkdiv = 255;
	unsigned int version = atmel_mci_get_version(mci);
	u32 clkodd = 0;
	u32 mr;

	debug("mci: bus_hz is %u, setting clock %u Hz, block size %u\n",
		bus_hz, hz, blklen);
	if (hz > 0) {
		if (version >= 0x500) {
			clkdiv = DIV_ROUND_UP(bus_hz, hz) - 2;
			if (clkdiv > 511)
				clkdiv = 511;

			clkodd = clkdiv & 1;
			clkdiv >>= 1;

			debug("mci: setting clock %u Hz, block size %u\n",
			      bus_hz / (clkdiv * 2 + clkodd + 2), blklen);
		} else {
			/* find clkdiv yielding a rate <= than requested */
			for (clkdiv = 0; clkdiv < 255; clkdiv++) {
				if ((bus_hz / (clkdiv + 1) / 2) <= hz)
					break;
			}
			debug("mci: setting clock %u Hz, block size %u\n",
			      (bus_hz / (clkdiv + 1)) / 2, blklen);

		}
	}
	if (version >= 0x500)
		priv->curr_clk = bus_hz / (clkdiv * 2 + clkodd + 2);
	else
		priv->curr_clk = (bus_hz / (clkdiv + 1)) / 2;
	blklen &= 0xfffc;

	mr = MMCI_BF(CLKDIV, clkdiv);

	/* MCI IP version >= 0x200 has R/WPROOF */
	if (version >= 0x200)
		mr |= MMCI_BIT(RDPROOF) | MMCI_BIT(WRPROOF);

	/*
	 * MCI IP version >= 0x500 use bit 16 as clkodd.
	 * MCI IP version < 0x500 use upper 16 bits for blklen.
	 */
	if (version >= 0x500)
		mr |= MMCI_BF(CLKODD, clkodd);
	else
		mr |= MMCI_BF(BLKLEN, blklen);

	writel(mr, &mci->mr);

	/* MCI IP version >= 0x200 has blkr */
	if (version >= 0x200)
		writel(MMCI_BF(BLKLEN, blklen), &mci->blkr);

	if (mmc->card_caps & mmc->cfg->host_caps & MMC_MODE_HS)
		writel(MMCI_BIT(HSMODE), &mci->cfg);

	priv->initialized = 1;
}

/* Return the CMDR with flags for a given command and data packet */
static u32 mci_encode_cmd(
	struct mmc_cmd *cmd, struct mmc_data *data, u32* error_flags)
{
	u32 cmdr = 0;

	/* Default Flags for Errors */
	*error_flags |= (MMCI_BIT(DTOE) | MMCI_BIT(RDIRE) | MMCI_BIT(RENDE) |
		MMCI_BIT(RINDE) | MMCI_BIT(RTOE));

	/* Default Flags for the Command */
	cmdr |= MMCI_BIT(MAXLAT);

	if (data) {
		cmdr |= MMCI_BF(TRCMD, 1);
		if (data->blocks > 1)
			cmdr |= MMCI_BF(TRTYP, 1);
		if (data->flags & MMC_DATA_READ)
			cmdr |= MMCI_BIT(TRDIR);
	}

	if (cmd->resp_type & MMC_RSP_CRC)
		*error_flags |= MMCI_BIT(RCRCE);
	if (cmd->resp_type & MMC_RSP_136)
		cmdr |= MMCI_BF(RSPTYP, 2);
	else if (cmd->resp_type & MMC_RSP_BUSY)
		cmdr |= MMCI_BF(RSPTYP, 3);
	else if (cmd->resp_type & MMC_RSP_PRESENT)
		cmdr |= MMCI_BF(RSPTYP, 1);

	return cmdr | MMCI_BF(CMDNB, cmd->cmdidx);
}

/* Entered into function pointer in mci_send_cmd */
static u32 mci_data_read(atmel_mci_t *mci, u32* data, u32 error_flags)
{
	u32 status;

	do {
		status = readl(&mci->sr);
		if (status & (error_flags | MMCI_BIT(OVRE)))
			goto io_fail;
	} while (!(status & MMCI_BIT(RXRDY)));

	if (status & MMCI_BIT(RXRDY)) {
		*data = readl(&mci->rdr);
		status = 0;
	}
io_fail:
	return status;
}

/* Entered into function pointer in mci_send_cmd */
static u32 mci_data_write(atmel_mci_t *mci, u32* data, u32 error_flags)
{
	u32 status;

	do {
		status = readl(&mci->sr);
		if (status & (error_flags | MMCI_BIT(UNRE)))
			goto io_fail;
	} while (!(status & MMCI_BIT(TXRDY)));

	if (status & MMCI_BIT(TXRDY)) {
		writel(*data, &mci->tdr);
		status = 0;
	}
io_fail:
	return status;
}

/*
 * Entered into mmc structure during driver init
 *
 * Sends a command out on the bus and deals with the block data.
 * Takes the mmc pointer, a command pointer, and an optional data pointer.
 */
static int
mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
	struct atmel_mci_priv *priv = mmc->priv;
	atmel_mci_t *mci = priv->mci;
	u32 cmdr;
	u32 error_flags = 0;
	u32 status;

	if (!priv->initialized) {
		puts ("MCI not initialized!\n");
		return -ECOMM;
	}

	/* Figure out the transfer arguments */
	cmdr = mci_encode_cmd(cmd, data, &error_flags);

	/* For multi blocks read/write, set the block register */
	if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)
			|| (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK))
		writel(data->blocks | MMCI_BF(BLKLEN, mmc->read_bl_len),
			&mci->blkr);

	/* Send the command */
	writel(cmd->cmdarg, &mci->argr);
	writel(cmdr, &mci->cmdr);

#ifdef DEBUG
	dump_cmd(cmdr, cmd->cmdarg, 0, "DEBUG");
#endif

	/* Wait for the command to complete */
	while (!((status = readl(&mci->sr)) & MMCI_BIT(CMDRDY)));

	if ((status & error_flags) & MMCI_BIT(RTOE)) {
		dump_cmd(cmdr, cmd->cmdarg, status, "Command Time Out");
		return -ETIMEDOUT;
	} else if (status & error_flags) {
		dump_cmd(cmdr, cmd->cmdarg, status, "Command Failed");
		return -ECOMM;
	}

	/* Copy the response to the response buffer */
	if (cmd->resp_type & MMC_RSP_136) {
		cmd->response[0] = readl(&mci->rspr);
		cmd->response[1] = readl(&mci->rspr1);
		cmd->response[2] = readl(&mci->rspr2);
		cmd->response[3] = readl(&mci->rspr3);
	} else
		cmd->response[0] = readl(&mci->rspr);

	/* transfer all of the blocks */
	if (data) {
		u32 word_count, block_count;
		u32* ioptr;
		u32 sys_blocksize, dummy, i;
		u32 (*mci_data_op)
			(atmel_mci_t *mci, u32* data, u32 error_flags);

		if (data->flags & MMC_DATA_READ) {
			mci_data_op = mci_data_read;
			sys_blocksize = mmc->read_bl_len;
			ioptr = (u32*)data->dest;
		} else {
			mci_data_op = mci_data_write;
			sys_blocksize = mmc->write_bl_len;
			ioptr = (u32*)data->src;
		}

		status = 0;
		for (block_count = 0;
				block_count < data->blocks && !status;
				block_count++) {
			word_count = 0;
			do {
				status = mci_data_op(mci, ioptr, error_flags);
				word_count++;
				ioptr++;
			} while (!status && word_count < (data->blocksize/4));
#ifdef DEBUG
			if (data->flags & MMC_DATA_READ)
			{
				u32 cnt = word_count * 4;
				printf("Read Data:\n");
				print_buffer(0, data->dest + cnt * block_count,
					     1, cnt, 0);
			}
#endif
#ifdef DEBUG
			if (!status && word_count < (sys_blocksize / 4))
				printf("filling rest of block...\n");
#endif
			/* fill the rest of a full block */
			while (!status && word_count < (sys_blocksize / 4)) {
				status = mci_data_op(mci, &dummy,
					error_flags);
				word_count++;
			}
			if (status) {
				dump_cmd(cmdr, cmd->cmdarg, status,
					"Data Transfer Failed");
				return -ECOMM;
			}
		}

		/* Wait for Transfer End */
		i = 0;
		do {
			status = readl(&mci->sr);

			if (status & error_flags) {
				dump_cmd(cmdr, cmd->cmdarg, status,
					"DTIP Wait Failed");
				return -ECOMM;
			}
			i++;
		} while ((status & MMCI_BIT(DTIP)) && i < 10000);
		if (status & MMCI_BIT(DTIP)) {
			dump_cmd(cmdr, cmd->cmdarg, status,
				"XFER DTIP never unset, ignoring");
		}
	}

	/*
	 * After the switch command, wait for 8 clocks before the next
	 * command
	 */
	if (cmd->cmdidx == MMC_CMD_SWITCH)
		udelay(8*1000000 / priv->curr_clk); /* 8 clk in us */

	return 0;
}

/* Entered into mmc structure during driver init */
static void mci_set_ios(struct mmc *mmc)
{
	struct atmel_mci_priv *priv = mmc->priv;
	atmel_mci_t *mci = priv->mci;
	int bus_width = mmc->bus_width;
	unsigned int version = atmel_mci_get_version(mci);
	int busw;

	/* Set the clock speed */
	mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN);

	/*
	 * set the bus width and select slot for this interface
	 * there is no capability for multiple slots on the same interface yet
	 */
	if ((version & 0xf00) >= 0x300) {
		switch (bus_width) {
		case 8:
			busw = 3;
			break;
		case 4:
			busw = 2;
			break;
		default:
			busw = 0;
			break;
		}

		writel(busw << 6 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
	} else {
		busw = (bus_width == 4) ? 1 : 0;

		writel(busw << 7 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
	}
}

/* Entered into mmc structure during driver init */
static int mci_init(struct mmc *mmc)
{
	struct atmel_mci_priv *priv = mmc->priv;
	atmel_mci_t *mci = priv->mci;

	/* Initialize controller */
	writel(MMCI_BIT(SWRST), &mci->cr);	/* soft reset */
	writel(MMCI_BIT(PWSDIS), &mci->cr);	/* disable power save */
	writel(MMCI_BIT(MCIEN), &mci->cr);	/* enable mci */
	writel(MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);	/* select port */

	/* This delay can be optimized, but stick with max value */
	writel(0x7f, &mci->dtor);
	/* Disable Interrupts */
	writel(~0UL, &mci->idr);

	/* Set default clocks and blocklen */
	mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);

	return 0;
}

static const struct mmc_ops atmel_mci_ops = {
	.send_cmd	= mci_send_cmd,
	.set_ios	= mci_set_ios,
	.init		= mci_init,
};

/*
 * This is the only exported function
 *
 * Call it with the MCI register base address
 */
int atmel_mci_init(void *regs)
{
	struct mmc *mmc;
	struct mmc_config *cfg;
	struct atmel_mci_priv *priv;
	unsigned int version;

	priv = calloc(1, sizeof(*priv));
	if (!priv)
		return -ENOMEM;

	cfg = &priv->cfg;

	cfg->name = "mci";
	cfg->ops = &atmel_mci_ops;

	priv->mci = (struct atmel_mci *)regs;
	priv->initialized = 0;

	/* need to be able to pass these in on a board by board basis */
	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
	version = atmel_mci_get_version(priv->mci);
	if ((version & 0xf00) >= 0x300) {
		cfg->host_caps = MMC_MODE_8BIT;
		cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
	}

	cfg->host_caps |= MMC_MODE_4BIT;

	/*
	 * min and max frequencies determined by
	 * max and min of clock divider
	 */
	cfg->f_min = get_mci_clk_rate() / (2*256);
	cfg->f_max = get_mci_clk_rate() / (2*1);

	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;

	mmc = mmc_create(cfg, priv);

	if (mmc == NULL) {
		free(priv);
		return -ENODEV;
	}
	/* NOTE: possibly leaking the priv structure */

	return 0;
}
Commit	Line	Data
1592ef85 RM	1	/*
	2	* Copyright (C) 2010
	3	* Rob Emanuele <[email protected]>
	4	* Reinhard Meyer, EMK Elektronik <[email protected]>
	5	*
	6	* Original Driver:
	7	* Copyright (C) 2004-2006 Atmel Corporation
	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
1592ef85 RM	10	*/
	11
	12	#include <common.h>
	13	#include <mmc.h>
	14	#include <part.h>
	15	#include <malloc.h>
	16	#include <asm/io.h>
	17	#include <asm/errno.h>
	18	#include <asm/byteorder.h>
	19	#include <asm/arch/clk.h>
329f0f52	20	#include <asm/arch/hardware.h>
1592ef85 RM	21	#include "atmel_mci.h"
	22
	23	#ifndef CONFIG_SYS_MMC_CLK_OD
	24	# define CONFIG_SYS_MMC_CLK_OD 150000
	25	#endif
	26
	27	#define MMC_DEFAULT_BLKLEN 512
	28
	29	#if defined(CONFIG_ATMEL_MCI_PORTB)
	30	# define MCI_BUS 1
	31	#else
	32	# define MCI_BUS 0
	33	#endif
	34
6b75d359 MV	35	struct atmel_mci_priv {
	36	struct mmc_config cfg;
	37	struct atmel_mci *mci;
877807e1	38	unsigned int initialized:1;
b4670a0c	39	unsigned int curr_clk;
6b75d359 MV	40	};
6b75d359 MV	41
aac4b69b BS	42	/* Read Atmel MCI IP version */
	43	static unsigned int atmel_mci_get_version(struct atmel_mci *mci)
	44	{
	45	return readl(&mci->version) & 0x00000fff;
	46	}
	47
1592ef85 RM	48	/*
	49	* Print command and status:
	50	*
	51	* - always when DEBUG is defined
	52	* - on command errors
	53	*/
	54	static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg)
	55	{
b84c9c9a MV	56	debug("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n",
b84c9c9a MV	57	cmdr, cmdr & 0x3F, arg, status, msg);
1592ef85 RM	58	}
	59
	60	/* Setup for MCI Clock and Block Size */
	61	static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
	62	{
6b75d359 MV	63	struct atmel_mci_priv *priv = mmc->priv;
6b75d359 MV	64	atmel_mci_t *mci = priv->mci;
1592ef85 RM	65	u32 bus_hz = get_mci_clk_rate();
1592ef85 RM	66	u32 clkdiv = 255;
cd60ebd4 BS	67	unsigned int version = atmel_mci_get_version(mci);
	68	u32 clkodd = 0;
	69	u32 mr;
1592ef85 RM	70
	71	debug("mci: bus_hz is %u, setting clock %u Hz, block size %u\n",
	72	bus_hz, hz, blklen);
	73	if (hz > 0) {
cd60ebd4 BS	74	if (version >= 0x500) {
	75	clkdiv = DIV_ROUND_UP(bus_hz, hz) - 2;
	76	if (clkdiv > 511)
	77	clkdiv = 511;
	78
	79	clkodd = clkdiv & 1;
	80	clkdiv >>= 1;
	81
b84c9c9a MV	82	debug("mci: setting clock %u Hz, block size %u\n",
b84c9c9a MV	83	bus_hz / (clkdiv * 2 + clkodd + 2), blklen);
cd60ebd4 BS	84	} else {
	85	/* find clkdiv yielding a rate <= than requested */
	86	for (clkdiv = 0; clkdiv < 255; clkdiv++) {
	87	if ((bus_hz / (clkdiv + 1) / 2) <= hz)
	88	break;
	89	}
b84c9c9a MV	90	debug("mci: setting clock %u Hz, block size %u\n",
b84c9c9a MV	91	(bus_hz / (clkdiv + 1)) / 2, blklen);
cd60ebd4	92
1592ef85 RM	93	}
1592ef85 RM	94	}
b4670a0c GC	95	if (version >= 0x500)
	96	priv->curr_clk = bus_hz / (clkdiv * 2 + clkodd + 2);
	97	else
	98	priv->curr_clk = (bus_hz / (clkdiv + 1)) / 2;
1592ef85	99	blklen &= 0xfffc;
cd60ebd4 BS	100
	101	mr = MMCI_BF(CLKDIV, clkdiv);
	102
	103	/* MCI IP version >= 0x200 has R/WPROOF */
	104	if (version >= 0x200)
	105	mr \|= MMCI_BIT(RDPROOF) \| MMCI_BIT(WRPROOF);
	106
1db7377a	107	/*
cd60ebd4 BS	108	* MCI IP version >= 0x500 use bit 16 as clkodd.
cd60ebd4 BS	109	* MCI IP version < 0x500 use upper 16 bits for blklen.
1db7377a	110	*/
cd60ebd4 BS	111	if (version >= 0x500)
	112	mr \|= MMCI_BF(CLKODD, clkodd);
	113	else
	114	mr \|= MMCI_BF(BLKLEN, blklen);
	115
	116	writel(mr, &mci->mr);
	117
	118	/* MCI IP version >= 0x200 has blkr */
	119	if (version >= 0x200)
	120	writel(MMCI_BF(BLKLEN, blklen), &mci->blkr);
	121
da55c66e BS	122	if (mmc->card_caps & mmc->cfg->host_caps & MMC_MODE_HS)
	123	writel(MMCI_BIT(HSMODE), &mci->cfg);
	124
877807e1	125	priv->initialized = 1;
1592ef85 RM	126	}
	127
	128	/* Return the CMDR with flags for a given command and data packet */
	129	static u32 mci_encode_cmd(
	130	struct mmc_cmd cmd, struct mmc_data data, u32* error_flags)
	131	{
	132	u32 cmdr = 0;
	133
	134	/* Default Flags for Errors */
	135	*error_flags \|= (MMCI_BIT(DTOE) \| MMCI_BIT(RDIRE) \| MMCI_BIT(RENDE) \|
	136	MMCI_BIT(RINDE) \| MMCI_BIT(RTOE));
	137
	138	/* Default Flags for the Command */
	139	cmdr \|= MMCI_BIT(MAXLAT);
	140
	141	if (data) {
	142	cmdr \|= MMCI_BF(TRCMD, 1);
	143	if (data->blocks > 1)
	144	cmdr \|= MMCI_BF(TRTYP, 1);
	145	if (data->flags & MMC_DATA_READ)
	146	cmdr \|= MMCI_BIT(TRDIR);
	147	}
	148
	149	if (cmd->resp_type & MMC_RSP_CRC)
	150	*error_flags \|= MMCI_BIT(RCRCE);
	151	if (cmd->resp_type & MMC_RSP_136)
	152	cmdr \|= MMCI_BF(RSPTYP, 2);
	153	else if (cmd->resp_type & MMC_RSP_BUSY)
	154	cmdr \|= MMCI_BF(RSPTYP, 3);
	155	else if (cmd->resp_type & MMC_RSP_PRESENT)
	156	cmdr \|= MMCI_BF(RSPTYP, 1);
	157
	158	return cmdr \| MMCI_BF(CMDNB, cmd->cmdidx);
	159	}
	160
	161	/* Entered into function pointer in mci_send_cmd */
	162	static u32 mci_data_read(atmel_mci_t mci, u32 data, u32 error_flags)
	163	{
	164	u32 status;
	165
	166	do {
	167	status = readl(&mci->sr);
	168	if (status & (error_flags \| MMCI_BIT(OVRE)))
	169	goto io_fail;
	170	} while (!(status & MMCI_BIT(RXRDY)));
	171
	172	if (status & MMCI_BIT(RXRDY)) {
	173	*data = readl(&mci->rdr);
	174	status = 0;
	175	}
	176	io_fail:
	177	return status;
	178	}
	179
	180	/* Entered into function pointer in mci_send_cmd */
	181	static u32 mci_data_write(atmel_mci_t mci, u32 data, u32 error_flags)
	182	{
	183	u32 status;
	184
	185	do {
	186	status = readl(&mci->sr);
	187	if (status & (error_flags \| MMCI_BIT(UNRE)))
	188	goto io_fail;
	189	} while (!(status & MMCI_BIT(TXRDY)));
190
191	if (status & MMCI_BIT(TXRDY)) {
192	writel(*data, &mci->tdr);
193	status = 0;
194	}
195	io_fail:
196	return status;
197	}
198
199	/*
200	* Entered into mmc structure during driver init
201	*
202	* Sends a command out on the bus and deals with the block data.
203	* Takes the mmc pointer, a command pointer, and an optional data pointer.
204	*/
205	static int
206	mci_send_cmd(struct mmc mmc, struct mmc_cmd cmd, struct mmc_data *data)
207	{
6b75d359 MV	208	struct atmel_mci_priv *priv = mmc->priv;
6b75d359 MV	209	atmel_mci_t *mci = priv->mci;
1592ef85 RM	210	u32 cmdr;
	211	u32 error_flags = 0;
	212	u32 status;
	213
877807e1	214	if (!priv->initialized) {
1592ef85	215	puts ("MCI not initialized!\n");
915ffa52	216	return -ECOMM;
1592ef85 RM	217	}
	218
	219	/* Figure out the transfer arguments */
	220	cmdr = mci_encode_cmd(cmd, data, &error_flags);
	221
1db7377a WJ	222	/* For multi blocks read/write, set the block register */
	223	if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)
	224	\|\| (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK))
	225	writel(data->blocks \| MMCI_BF(BLKLEN, mmc->read_bl_len),
	226	&mci->blkr);
	227
1592ef85 RM	228	/* Send the command */
	229	writel(cmd->cmdarg, &mci->argr);
	230	writel(cmdr, &mci->cmdr);
	231
	232	#ifdef DEBUG
	233	dump_cmd(cmdr, cmd->cmdarg, 0, "DEBUG");
	234	#endif
	235
	236	/* Wait for the command to complete */
	237	while (!((status = readl(&mci->sr)) & MMCI_BIT(CMDRDY)));
	238
93e3236c BS	239	if ((status & error_flags) & MMCI_BIT(RTOE)) {
93e3236c BS	240	dump_cmd(cmdr, cmd->cmdarg, status, "Command Time Out");
915ffa52	241	return -ETIMEDOUT;
93e3236c	242	} else if (status & error_flags) {
1592ef85	243	dump_cmd(cmdr, cmd->cmdarg, status, "Command Failed");
915ffa52	244	return -ECOMM;
1592ef85 RM	245	}
	246
	247	/* Copy the response to the response buffer */
	248	if (cmd->resp_type & MMC_RSP_136) {
	249	cmd->response[0] = readl(&mci->rspr);
	250	cmd->response[1] = readl(&mci->rspr1);
	251	cmd->response[2] = readl(&mci->rspr2);
	252	cmd->response[3] = readl(&mci->rspr3);
	253	} else
	254	cmd->response[0] = readl(&mci->rspr);
	255
	256	/* transfer all of the blocks */
	257	if (data) {
	258	u32 word_count, block_count;
	259	u32* ioptr;
	260	u32 sys_blocksize, dummy, i;
	261	u32 (*mci_data_op)
	262	(atmel_mci_t mci, u32 data, u32 error_flags);
	263
	264	if (data->flags & MMC_DATA_READ) {
	265	mci_data_op = mci_data_read;
	266	sys_blocksize = mmc->read_bl_len;
	267	ioptr = (u32*)data->dest;
	268	} else {
	269	mci_data_op = mci_data_write;
	270	sys_blocksize = mmc->write_bl_len;
	271	ioptr = (u32*)data->src;
	272	}
	273
	274	status = 0;
	275	for (block_count = 0;
	276	block_count < data->blocks && !status;
	277	block_count++) {
	278	word_count = 0;
	279	do {
	280	status = mci_data_op(mci, ioptr, error_flags);
	281	word_count++;
	282	ioptr++;
	283	} while (!status && word_count < (data->blocksize/4));
	284	#ifdef DEBUG
	285	if (data->flags & MMC_DATA_READ)
	286	{
9902c7b6	287	u32 cnt = word_count * 4;
1592ef85	288	printf("Read Data:\n");
9902c7b6 WJ	289	print_buffer(0, data->dest + cnt * block_count,
9902c7b6 WJ	290	1, cnt, 0);
1592ef85 RM	291	}
	292	#endif
	293	#ifdef DEBUG
	294	if (!status && word_count < (sys_blocksize / 4))
	295	printf("filling rest of block...\n");
	296	#endif
	297	/* fill the rest of a full block */
	298	while (!status && word_count < (sys_blocksize / 4)) {
	299	status = mci_data_op(mci, &dummy,
	300	error_flags);
	301	word_count++;
	302	}
	303	if (status) {
	304	dump_cmd(cmdr, cmd->cmdarg, status,
	305	"Data Transfer Failed");
915ffa52	306	return -ECOMM;
1592ef85 RM	307	}
	308	}
	309
	310	/* Wait for Transfer End */
	311	i = 0;
	312	do {
	313	status = readl(&mci->sr);
	314
	315	if (status & error_flags) {
	316	dump_cmd(cmdr, cmd->cmdarg, status,
	317	"DTIP Wait Failed");
915ffa52	318	return -ECOMM;
1592ef85 RM	319	}
	320	i++;
	321	} while ((status & MMCI_BIT(DTIP)) && i < 10000);
	322	if (status & MMCI_BIT(DTIP)) {
	323	dump_cmd(cmdr, cmd->cmdarg, status,
	324	"XFER DTIP never unset, ignoring");
	325	}
	326	}
	327
b4670a0c GC	328	/*
	329	* After the switch command, wait for 8 clocks before the next
	330	* command
	331	*/
	332	if (cmd->cmdidx == MMC_CMD_SWITCH)
	333	udelay(81000000 / priv->curr_clk); / 8 clk in us */
	334
1592ef85 RM	335	return 0;
	336	}
	337
	338	/* Entered into mmc structure during driver init */
	339	static void mci_set_ios(struct mmc *mmc)
	340	{
6b75d359 MV	341	struct atmel_mci_priv *priv = mmc->priv;
6b75d359 MV	342	atmel_mci_t *mci = priv->mci;
aac4b69b BS	343	int bus_width = mmc->bus_width;
	344	unsigned int version = atmel_mci_get_version(mci);
	345	int busw;
1592ef85 RM	346
	347	/* Set the clock speed */
	348	mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN);
	349
	350	/*
	351	* set the bus width and select slot for this interface
	352	* there is no capability for multiple slots on the same interface yet
1592ef85	353	*/
aac4b69b BS	354	if ((version & 0xf00) >= 0x300) {
	355	switch (bus_width) {
	356	case 8:
	357	busw = 3;
	358	break;
	359	case 4:
	360	busw = 2;
	361	break;
	362	default:
	363	busw = 0;
	364	break;
	365	}
	366
	367	writel(busw << 6 \| MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
	368	} else {
	369	busw = (bus_width == 4) ? 1 : 0;
	370
	371	writel(busw << 7 \| MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
	372	}
1592ef85 RM	373	}
	374
	375	/* Entered into mmc structure during driver init */
	376	static int mci_init(struct mmc *mmc)
	377	{
6b75d359 MV	378	struct atmel_mci_priv *priv = mmc->priv;
6b75d359 MV	379	atmel_mci_t *mci = priv->mci;
1592ef85 RM	380
	381	/* Initialize controller */
	382	writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */
	383	writel(MMCI_BIT(PWSDIS), &mci->cr); /* disable power save */
	384	writel(MMCI_BIT(MCIEN), &mci->cr); /* enable mci */
2aed9d14	385	writel(MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); /* select port */
1592ef85	386
9924ca6e WJ	387	/* This delay can be optimized, but stick with max value */
9924ca6e WJ	388	writel(0x7f, &mci->dtor);
1592ef85 RM	389	/* Disable Interrupts */
	390	writel(~0UL, &mci->idr);
	391
	392	/* Set default clocks and blocklen */
	393	mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
	394
	395	return 0;
	396	}
	397
ab769f22 PA	398	static const struct mmc_ops atmel_mci_ops = {
	399	.send_cmd = mci_send_cmd,
	400	.set_ios = mci_set_ios,
	401	.init = mci_init,
	402	};
	403
1592ef85 RM	404	/*
	405	* This is the only exported function
	406	*
	407	* Call it with the MCI register base address
	408	*/
	409	int atmel_mci_init(void *regs)
	410	{
93bfd616 PA	411	struct mmc *mmc;
93bfd616 PA	412	struct mmc_config *cfg;
6b75d359	413	struct atmel_mci_priv *priv;
aac4b69b	414	unsigned int version;
1592ef85	415
6b75d359 MV	416	priv = calloc(1, sizeof(*priv));
	417	if (!priv)
	418	return -ENOMEM;
aac4b69b	419
6b75d359	420	cfg = &priv->cfg;
93bfd616 PA	421
	422	cfg->name = "mci";
	423	cfg->ops = &atmel_mci_ops;
1592ef85	424
6b75d359	425	priv->mci = (struct atmel_mci *)regs;
877807e1	426	priv->initialized = 0;
6b75d359	427
1592ef85	428	/* need to be able to pass these in on a board by board basis */
93bfd616	429	cfg->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34;
6b75d359	430	version = atmel_mci_get_version(priv->mci);
da55c66e	431	if ((version & 0xf00) >= 0x300) {
93bfd616	432	cfg->host_caps = MMC_MODE_8BIT;
da55c66e BS	433	cfg->host_caps \|= MMC_MODE_HS \| MMC_MODE_HS_52MHz;
da55c66e BS	434	}
aac4b69b	435
93bfd616	436	cfg->host_caps \|= MMC_MODE_4BIT;
aac4b69b	437
1592ef85 RM	438	/*
	439	* min and max frequencies determined by
	440	* max and min of clock divider
	441	*/
93bfd616 PA	442	cfg->f_min = get_mci_clk_rate() / (2*256);
	443	cfg->f_max = get_mci_clk_rate() / (2*1);
	444
	445	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1592ef85	446
6b75d359	447	mmc = mmc_create(cfg, priv);
8feafcc4	448
93bfd616	449	if (mmc == NULL) {
6b75d359 MV	450	free(priv);
6b75d359 MV	451	return -ENODEV;
93bfd616	452	}
6b75d359	453	/* NOTE: possibly leaking the priv structure */
1592ef85 RM	454
	455	return 0;
	456	}