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common: Drop net.h from common header
[u-boot.git] / board / phytec / pfla02 / pfla02.c
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83d290c5 1// SPDX-License-Identifier: GPL-2.0+
83605d37
SB		 2/*
3 * Copyright (C) 2017 Stefano Babic <[email protected]>
83605d37
SB		 4 */
5
6#include <common.h>
1eb69ae4 7#include <cpu_func.h>
5255932f 8#include <init.h>
90526e9f 9#include <net.h>
83605d37
SB		 10#include <asm/io.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/imx-regs.h>
13#include <asm/arch/iomux.h>
14#include <asm/arch/crm_regs.h>
15#include <asm/arch/iomux.h>
16#include <asm/arch/mx6-pins.h>
17#include <asm/mach-imx/iomux-v3.h>
18#include <asm/mach-imx/boot_mode.h>
19#include <asm/mach-imx/mxc_i2c.h>
20#include <asm/mach-imx/spi.h>
9fb625ce 21#include <env.h>
83605d37
SB		 22#include <linux/errno.h>
23#include <asm/gpio.h>
24#include <mmc.h>
25#include <i2c.h>
e37ac717 26#include <fsl_esdhc_imx.h>
83605d37
SB		 27#include <nand.h>
28#include <miiphy.h>
29#include <netdev.h>
30#include <asm/arch/sys_proto.h>
31#include <asm/sections.h>
32
33DECLARE_GLOBAL_DATA_PTR;
34
35#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
36 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
37 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38
39#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
40 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
41 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42
43#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
44 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
45
46#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
47 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
48
49#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
50 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
51 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
52
53#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
54
55#define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
56 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
57
58#define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
59 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
60
61#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14)
62#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
63#define GREEN_LED IMX_GPIO_NR(2, 31)
64#define RED_LED IMX_GPIO_NR(1, 30)
65#define IMX6Q_DRIVE_STRENGTH 0x30
66
67int dram_init(void)
68{
69 gd->ram_size = imx_ddr_size();
70 return 0;
71}
72
73static iomux_v3_cfg_t const uart4_pads[] = {
74 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
75 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
76};
77
78static iomux_v3_cfg_t const enet_pads[] = {
79 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
80 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
81 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
82 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
83 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
84 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
85 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
86 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
87 MUX_PAD_CTRL(ENET_PAD_CTRL)),
88 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
89 MUX_PAD_CTRL(ENET_PAD_CTRL)),
90 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
91 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
92 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
93 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
94 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
95 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
96 MUX_PAD_CTRL(ENET_PAD_CTRL)),
97 IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
98};
99
100static iomux_v3_cfg_t const ecspi3_pads[] = {
101 IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
102 IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
103 IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
104 IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
105};
106
107static iomux_v3_cfg_t const gpios_pads[] = {
108 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
109 IOMUX_PADS(PAD_SD4_DAT4__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
110 IOMUX_PADS(PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
111 IOMUX_PADS(PAD_SD4_DAT6__GPIO2_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
112 IOMUX_PADS(PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
113 IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
114 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
115 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
116};
117
118#ifdef CONFIG_CMD_NAND
119/* NAND */
120static iomux_v3_cfg_t const nfc_pads[] = {
121 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL)),
122 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL)),
123 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
124 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
125 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
126 IOMUX_PADS(PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
127 IOMUX_PADS(PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
128 IOMUX_PADS(PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
129 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
130 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
131 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
132 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
133 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
134 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
135 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
136 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
137 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
138 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
139 IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL)),
140};
141#endif
142
143static struct i2c_pads_info i2c_pad_info = {
144 .scl = {
145 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | I2C_PAD,
146 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | I2C_PAD,
147 .gp = IMX_GPIO_NR(3, 21)
148 },
149 .sda = {
150 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | I2C_PAD,
151 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | I2C_PAD,
152 .gp = IMX_GPIO_NR(3, 28)
153 }
154};
155
156static struct fsl_esdhc_cfg usdhc_cfg[] = {
157 {USDHC3_BASE_ADDR,
158 .max_bus_width = 4},
159 {.esdhc_base = USDHC2_BASE_ADDR,
160 .max_bus_width = 4},
161};
162
163#if !defined(CONFIG_SPL_BUILD)
164static iomux_v3_cfg_t const usdhc2_pads[] = {
165 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
166 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
167 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
168 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
169 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
170 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
171 IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
172 IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
173};
174#endif
175
176static iomux_v3_cfg_t const usdhc3_pads[] = {
177 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
178 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
179 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
180 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
181 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
182 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
183 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
184 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
185 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
186 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
187};
188
189int board_mmc_get_env_dev(int devno)
190{
191 return devno - 1;
192}
193
194int board_mmc_getcd(struct mmc *mmc)
195{
196 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
197 int ret = 0;
198
199 switch (cfg->esdhc_base) {
200 case USDHC2_BASE_ADDR:
201 ret = !gpio_get_value(USDHC2_CD_GPIO);
202 ret = 1;
203 break;
204 case USDHC3_BASE_ADDR:
205 ret = 1;
206 break;
207 }
208
209 return ret;
210}
211
212#ifndef CONFIG_SPL_BUILD
213int board_mmc_init(bd_t *bis)
214{
215 int ret;
216 int i;
217
218 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
219 switch (i) {
220 case 0:
221 SETUP_IOMUX_PADS(usdhc3_pads);
222 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
223 break;
224 case 1:
225 SETUP_IOMUX_PADS(usdhc2_pads);
226 gpio_direction_input(USDHC2_CD_GPIO);
227 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
228 break;
229 default:
230 printf("Warning: you configured more USDHC controllers"
231 "(%d) then supported by the board (%d)\n",
232 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
233 return -EINVAL;
234 }
235
236 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
237 if (ret)
238 return ret;
239 }
240
241 return 0;
242}
243#endif
244
245static void setup_iomux_uart(void)
246{
247 SETUP_IOMUX_PADS(uart4_pads);
248}
249
250static void setup_iomux_enet(void)
251{
252 SETUP_IOMUX_PADS(enet_pads);
253
254 gpio_direction_output(ENET_PHY_RESET_GPIO, 0);
255 mdelay(10);
256 gpio_set_value(ENET_PHY_RESET_GPIO, 1);
257 mdelay(30);
258}
259
260static void setup_spi(void)
261{
262 gpio_request(IMX_GPIO_NR(4, 24), "spi_cs0");
263 gpio_direction_output(IMX_GPIO_NR(4, 24), 1);
264
265 SETUP_IOMUX_PADS(ecspi3_pads);
266
267 enable_spi_clk(true, 2);
268}
269
270static void setup_gpios(void)
271{
272 SETUP_IOMUX_PADS(gpios_pads);
273}
274
275#ifdef CONFIG_CMD_NAND
276static void setup_gpmi_nand(void)
277{
278 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
279
280 /* config gpmi nand iomux */
281 SETUP_IOMUX_PADS(nfc_pads);
282
283 /* gate ENFC_CLK_ROOT clock first,before clk source switch */
284 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
285
286 /* config gpmi and bch clock to 100 MHz */
287 clrsetbits_le32(&mxc_ccm->cs2cdr,
288 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
289 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
290 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
291 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
292 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
293 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
294
295 /* enable ENFC_CLK_ROOT clock */
296 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
297
298 /* enable gpmi and bch clock gating */
299 setbits_le32(&mxc_ccm->CCGR4,
300 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
301 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
302 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
303 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
304 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
305
306 /* enable apbh clock gating */
307 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
308}
309#endif
310
311/*
312 * Board revision is coded in 4 GPIOs
313 */
314u32 get_board_rev(void)
315{
316 u32 rev;
317 int i;
318
319 for (i = 0, rev = 0; i < 4; i++)
320 rev |= (gpio_get_value(IMX_GPIO_NR(2, 12 + i)) << i);
321
322 return 16 - rev;
323}
324
325int board_spi_cs_gpio(unsigned bus, unsigned cs)
326{
327 if (bus != 2 || (cs != 0))
328 return -EINVAL;
329
330 return IMX_GPIO_NR(4, 24);
331}
332
333int board_eth_init(bd_t *bis)
334{
335 setup_iomux_enet();
336
337 return cpu_eth_init(bis);
338}
339
340int board_early_init_f(void)
341{
342 setup_iomux_uart();
343
344 return 0;
345}
346
347int board_init(void)
348{
349 /* address of boot parameters */
350 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
351
352#ifdef CONFIG_SYS_I2C_MXC
353 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info);
354#endif
355
356#ifdef CONFIG_MXC_SPI
357 setup_spi();
358#endif
359
360 setup_gpios();
361
362#ifdef CONFIG_CMD_NAND
363 setup_gpmi_nand();
364#endif
365 return 0;
366}
367
368
369#ifdef CONFIG_CMD_BMODE
370/*
371 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
372 * see Table 8-11 and Table 5-9
373 * BOOT_CFG1[7] = 1 (boot from NAND)
374 * BOOT_CFG1[5] = 0 - raw NAND
375 * BOOT_CFG1[4] = 0 - default pad settings
376 * BOOT_CFG1[3:2] = 00 - devices = 1
377 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
378 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
379 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
380 * BOOT_CFG2[0] = 0 - Reset time 12ms
381 */
382static const struct boot_mode board_boot_modes[] = {
383 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
384 {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
385 {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
386 {NULL, 0},
387};
388#endif
389
390int board_late_init(void)
391{
392 char buf[10];
393#ifdef CONFIG_CMD_BMODE
394 add_board_boot_modes(board_boot_modes);
395#endif
396
397 snprintf(buf, sizeof(buf), "%d", get_board_rev());
470135be 398 env_set("board_rev", buf);
83605d37
SB		 399
400 return 0;
401}
402
403#ifdef CONFIG_SPL_BUILD
404#include <asm/arch/mx6-ddr.h>
405#include <spl.h>
b08c8c48 406#include <linux/libfdt.h>
83605d37
SB		 407
408#define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11)
409static void phyflex_err006282_workaround(void)
410{
411 /*
412 * Boards beginning with 1362.2 have the SD4_DAT3 pin connected
413 * to the CMIC. If this pin isn't toggled within 10s the boards
414 * reset. The pin is unconnected on older boards, so we do not
415 * need a check for older boards before applying this fixup.
416 */
417
418 gpio_direction_output(MX6_PHYFLEX_ERR006282, 0);
419 mdelay(2);
420 gpio_direction_output(MX6_PHYFLEX_ERR006282, 1);
421 mdelay(2);
422 gpio_set_value(MX6_PHYFLEX_ERR006282, 0);
423
424 gpio_direction_input(MX6_PHYFLEX_ERR006282);
425}
426
427static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
428 .dram_sdclk_0 = 0x00000030,
429 .dram_sdclk_1 = 0x00000030,
430 .dram_cas = 0x00000030,
431 .dram_ras = 0x00000030,
432 .dram_reset = 0x00000030,
433 .dram_sdcke0 = 0x00003000,
434 .dram_sdcke1 = 0x00003000,
435 .dram_sdba2 = 0x00000030,
436 .dram_sdodt0 = 0x00000030,
437 .dram_sdodt1 = 0x00000030,
438
439 .dram_sdqs0 = 0x00000028,
440 .dram_sdqs1 = 0x00000028,
441 .dram_sdqs2 = 0x00000028,
442 .dram_sdqs3 = 0x00000028,
443 .dram_sdqs4 = 0x00000028,
444 .dram_sdqs5 = 0x00000028,
445 .dram_sdqs6 = 0x00000028,
446 .dram_sdqs7 = 0x00000028,
447 .dram_dqm0 = 0x00000028,
448 .dram_dqm1 = 0x00000028,
449 .dram_dqm2 = 0x00000028,
450 .dram_dqm3 = 0x00000028,
451 .dram_dqm4 = 0x00000028,
452 .dram_dqm5 = 0x00000028,
453 .dram_dqm6 = 0x00000028,
454 .dram_dqm7 = 0x00000028,
455};
456
457static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
458 .grp_ddr_type = 0x000C0000,
459 .grp_ddrmode_ctl = 0x00020000,
460 .grp_ddrpke = 0x00000000,
461 .grp_addds = IMX6Q_DRIVE_STRENGTH,
462 .grp_ctlds = IMX6Q_DRIVE_STRENGTH,
463 .grp_ddrmode = 0x00020000,
464 .grp_b0ds = 0x00000028,
465 .grp_b1ds = 0x00000028,
466 .grp_b2ds = 0x00000028,
467 .grp_b3ds = 0x00000028,
468 .grp_b4ds = 0x00000028,
469 .grp_b5ds = 0x00000028,
470 .grp_b6ds = 0x00000028,
471 .grp_b7ds = 0x00000028,
472};
473
474static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
475 .p0_mpwldectrl0 = 0x00110011,
476 .p0_mpwldectrl1 = 0x00240024,
477 .p1_mpwldectrl0 = 0x00260038,
478 .p1_mpwldectrl1 = 0x002C0038,
479 .p0_mpdgctrl0 = 0x03400350,
480 .p0_mpdgctrl1 = 0x03440340,
481 .p1_mpdgctrl0 = 0x034C0354,
482 .p1_mpdgctrl1 = 0x035C033C,
483 .p0_mprddlctl = 0x322A2A2A,
484 .p1_mprddlctl = 0x302C2834,
485 .p0_mpwrdlctl = 0x34303834,
486 .p1_mpwrdlctl = 0x422A3E36,
487};
488
489/* Index in RAM Chip array */
490enum {
cb40adff
SB		 491 RAM_MT64K,
492 RAM_MT128K,
493 RAM_MT256K
83605d37
SB		 494};
495
496static struct mx6_ddr3_cfg mt41k_xx[] = {
497/* MT41K64M16JT-125 (1Gb density) */
498 {
499 .mem_speed = 1600,
500 .density = 1,
501 .width = 16,
502 .banks = 8,
503 .rowaddr = 13,
504 .coladdr = 10,
505 .pagesz = 2,
506 .trcd = 1375,
507 .trcmin = 4875,
508 .trasmin = 3500,
509 .SRT = 1,
510 },
511
512/* MT41K256M16JT-125 (2Gb density) */
513 {
514 .mem_speed = 1600,
515 .density = 2,
516 .width = 16,
517 .banks = 8,
518 .rowaddr = 14,
519 .coladdr = 10,
520 .pagesz = 2,
521 .trcd = 1375,
522 .trcmin = 4875,
523 .trasmin = 3500,
524 .SRT = 1,
525 },
526
527/* MT41K256M16JT-125 (4Gb density) */
528 {
529 .mem_speed = 1600,
530 .density = 4,
531 .width = 16,
532 .banks = 8,
533 .rowaddr = 15,
534 .coladdr = 10,
535 .pagesz = 2,
536 .trcd = 1375,
537 .trcmin = 4875,
538 .trasmin = 3500,
539 .SRT = 1,
540 }
541};
542
543static void ccgr_init(void)
544{
545 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
546
547 writel(0x00C03F3F, &ccm->CCGR0);
548 writel(0x0030FC03, &ccm->CCGR1);
549 writel(0x0FFFC000, &ccm->CCGR2);
550 writel(0x3FF00000, &ccm->CCGR3);
551 writel(0x00FFF300, &ccm->CCGR4);
552 writel(0x0F0000C3, &ccm->CCGR5);
553 writel(0x000003FF, &ccm->CCGR6);
554}
555
cb40adff
SB		 556static void spl_dram_init(struct mx6_ddr_sysinfo *sysinfo,
557 struct mx6_ddr3_cfg *mem_ddr)
83605d37 558{
83605d37 559 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
cb40adff 560 mx6_dram_cfg(sysinfo, &mx6_mmcd_calib, mem_ddr);
83605d37
SB		 561}
562
563int board_mmc_init(bd_t *bis)
564{
565 if (spl_boot_device() == BOOT_DEVICE_SPI)
566 printf("MMC SEtup, Boot SPI");
567
568 SETUP_IOMUX_PADS(usdhc3_pads);
569 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
570 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
571 usdhc_cfg[0].max_bus_width = 4;
572 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
573
574 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
575}
576
577
578void board_boot_order(u32 *spl_boot_list)
579{
580 spl_boot_list[0] = spl_boot_device();
581 printf("Boot device %x\n", spl_boot_list[0]);
582 switch (spl_boot_list[0]) {
583 case BOOT_DEVICE_SPI:
584 spl_boot_list[1] = BOOT_DEVICE_UART;
585 break;
586 case BOOT_DEVICE_MMC1:
587 spl_boot_list[1] = BOOT_DEVICE_SPI;
588 spl_boot_list[2] = BOOT_DEVICE_UART;
589 break;
590 default:
591 printf("Boot device %x\n", spl_boot_list[0]);
592 }
593}
594
595/*
596 * This is used because get_ram_size() does not
597 * take care of cache, resulting a wrong size
598 * pfla02 has just 1, 2 or 4 GB option
599 * Function checks for mirrors in the first CS
600 */
601#define RAM_TEST_PATTERN 0xaa5555aa
cb40adff
SB		 602#define MIN_BANK_SIZE (512 * 1024 * 1024)
603
604static unsigned int pfla02_detect_chiptype(void)
83605d37
SB		 605{
606 u32 *p, *p1;
cb40adff 607 unsigned int offset = MIN_BANK_SIZE;
83605d37
SB		 608 int i;
609
610 for (i = 0; i < 2; i++) {
611 p = (u32 *)PHYS_SDRAM;
612 p1 = (u32 *)(PHYS_SDRAM + (i + 1) * offset);
613
614 *p1 = 0;
615 *p = RAM_TEST_PATTERN;
616
617 /*
618 * This is required to detect mirroring
619 * else we read back values from cache
620 */
621 flush_dcache_all();
622
623 if (*p == *p1)
624 return i;
625 }
cb40adff 626 return RAM_MT256K;
83605d37
SB		 627}
628
629void board_init_f(ulong dummy)
630{
631 unsigned int ramchip;
cb40adff
SB		 632
633 struct mx6_ddr_sysinfo sysinfo = {
634 /* width of data bus:0=16,1=32,2=64 */
635 .dsize = 2,
636 /* config for full 4GB range so that get_mem_size() works */
637 .cs_density = 32, /* 512 MB */
638 /* single chip select */
639#if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
640 .ncs = 1,
641#else
642 .ncs = 2,
643#endif
644 .cs1_mirror = 1,
645 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
646 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
647 .walat = 1, /* Write additional latency */
648 .ralat = 5, /* Read additional latency */
649 .mif3_mode = 3, /* Command prediction working mode */
650 .bi_on = 1, /* Bank interleaving enabled */
651 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
652 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
653 .ddr_type = DDR_TYPE_DDR3,
654 .refsel = 1, /* Refresh cycles at 32KHz */
655 .refr = 7, /* 8 refresh commands per refresh cycle */
656 };
657
83605d37
SB		 658#ifdef CONFIG_CMD_NAND
659 /* Enable NAND */
660 setup_gpmi_nand();
661#endif
662
663 /* setup clock gating */
664 ccgr_init();
665
666 /* setup AIPS and disable watchdog */
667 arch_cpu_init();
668
669 /* setup AXI */
670 gpr_init();
671
672 board_early_init_f();
673
674 /* setup GP timer */
675 timer_init();
676
677 /* UART clocks enabled and gd valid - init serial console */
678 preloader_console_init();
679
680 setup_spi();
681
682 setup_gpios();
683
684 /* DDR initialization */
cb40adff
SB		 685 spl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]);
686 ramchip = pfla02_detect_chiptype();
687 debug("Detected chip %d\n", ramchip);
688#if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
689 switch (ramchip) {
690 case RAM_MT64K:
691 sysinfo.cs_density = 6;
692 break;
693 case RAM_MT128K:
694 sysinfo.cs_density = 10;
695 break;
696 case RAM_MT256K:
697 sysinfo.cs_density = 18;
698 break;
699 }
700#endif
701 spl_dram_init(&sysinfo, &mt41k_xx[ramchip]);
83605d37
SB		 702
703 /* Clear the BSS. */
704 memset(__bss_start, 0, __bss_end - __bss_start);
705
706 phyflex_err006282_workaround();
707
708 /* load/boot image from boot device */
709 board_init_r(NULL, 0);
710}
711#endif
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