[u-boot.git] / board / isee / igep003x / board.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Board functions for IGEP COM AQUILA and SMARC AM335x based boards
 *
 * Copyright (C) 2013-2017, ISEE 2007 SL - http://www.isee.biz/
 */

#include <common.h>
#include <env.h>
#include <errno.h>
#include <init.h>
#include <malloc.h>
#include <net.h>
#include <serial.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include <fdt_support.h>
#include <mtd_node.h>
#include <jffs2/load_kernel.h>
#include "board.h"

DECLARE_GLOBAL_DATA_PTR;

/* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards
 * and control IGEP0034 green and red LEDs.
 * U-boot configures these pins as input pullup to detect board revision:
 * IGEP0034-LITE = 0b00
 * IGEP0034 (FULL) = 0b01
 * IGEP0033 = 0b1X
 */
#define GPIO_GREEN_REVISION	27
#define GPIO_RED_REVISION	26

static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;

/*
 * Routine: get_board_revision
 * Description: Returns the board revision
 */
static int get_board_revision(void)
{
	int revision;

	gpio_request(GPIO_GREEN_REVISION, "green_revision");
	gpio_direction_input(GPIO_GREEN_REVISION);
	revision = 2 * gpio_get_value(GPIO_GREEN_REVISION);
	gpio_free(GPIO_GREEN_REVISION);

	gpio_request(GPIO_RED_REVISION, "red_revision");
	gpio_direction_input(GPIO_RED_REVISION);
	revision = revision + gpio_get_value(GPIO_RED_REVISION);
	gpio_free(GPIO_RED_REVISION);

	return revision;
}

#ifdef CONFIG_SPL_BUILD
/* PN H5TQ4G63AFR is equivalent to MT41K256M16HA125*/
static const struct ddr_data ddr3_igep0034_data = {
	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
};

static const struct ddr_data ddr3_igep0034_lite_data = {
	.datardsratio0 = K4B2G1646EBIH9_RD_DQS,
	.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
	.datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
	.datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
};

static const struct cmd_control ddr3_igep0034_cmd_ctrl_data = {
	.cmd0csratio = MT41K256M16HA125E_RATIO,
	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,

	.cmd1csratio = MT41K256M16HA125E_RATIO,
	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,

	.cmd2csratio = MT41K256M16HA125E_RATIO,
	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};

static const struct cmd_control ddr3_igep0034_lite_cmd_ctrl_data = {
	.cmd0csratio = K4B2G1646EBIH9_RATIO,
	.cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,

	.cmd1csratio = K4B2G1646EBIH9_RATIO,
	.cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,

	.cmd2csratio = K4B2G1646EBIH9_RATIO,
	.cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
};

static struct emif_regs ddr3_igep0034_emif_reg_data = {
	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
	.zq_config = MT41K256M16HA125E_ZQ_CFG,
	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};

static struct emif_regs ddr3_igep0034_lite_emif_reg_data = {
	.sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
	.ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
	.sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
	.sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
	.sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
	.zq_config = K4B2G1646EBIH9_ZQ_CFG,
	.emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
};

const struct ctrl_ioregs ioregs_igep0034 = {
	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
};

const struct ctrl_ioregs ioregs_igep0034_lite = {
	.cm0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
	.cm1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
	.cm2ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
	.dt0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
	.dt1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
};

#define OSC    (V_OSCK/1000000)
const struct dpll_params dpll_ddr = {
		400, OSC-1, 1, -1, -1, -1, -1};

const struct dpll_params *get_dpll_ddr_params(void)
{
	return &dpll_ddr;
}

void set_uart_mux_conf(void)
{
	enable_uart0_pin_mux();
}

void set_mux_conf_regs(void)
{
	enable_board_pin_mux();
}

void sdram_init(void)
{
	if (get_board_revision() == 1)
		config_ddr(400, &ioregs_igep0034, &ddr3_igep0034_data,
			&ddr3_igep0034_cmd_ctrl_data, &ddr3_igep0034_emif_reg_data, 0);
	else
		config_ddr(400, &ioregs_igep0034_lite, &ddr3_igep0034_lite_data,
			&ddr3_igep0034_lite_cmd_ctrl_data, &ddr3_igep0034_lite_emif_reg_data, 0);
}

#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
	/* break into full u-boot on 'c' */
	return serial_tstc() && serial_getc() == 'c';
}
#endif
#endif

/*
 * Basic board specific setup.  Pinmux has been handled already.
 */
int board_init(void)
{
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

	gpmc_init();

	return 0;
}

#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	switch (get_board_revision()) {
		case 0:
			env_set("board_name", "igep0034-lite");
			break;
		case 1:
			env_set("board_name", "igep0034");
			break;
		default:
			env_set("board_name", "igep0033");
			break;
	}
#endif
	return 0;
}
#endif

#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
	static const struct node_info nodes[] = {
		{ "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
	};

	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
#endif
	return 0;
}
#endif

#if defined(CONFIG_DRIVER_TI_CPSW)
static void cpsw_control(int enabled)
{
	/* VTP can be added here */

	return;
}

static struct cpsw_slave_data cpsw_slaves[] = {
	{
		.slave_reg_ofs	= 0x208,
		.sliver_reg_ofs	= 0xd80,
		.phy_addr	= 0,
		.phy_if		= PHY_INTERFACE_MODE_RMII,
	},
};

static struct cpsw_platform_data cpsw_data = {
	.mdio_base		= CPSW_MDIO_BASE,
	.cpsw_base		= CPSW_BASE,
	.mdio_div		= 0xff,
	.channels		= 8,
	.cpdma_reg_ofs		= 0x800,
	.slaves			= 1,
	.slave_data		= cpsw_slaves,
	.ale_reg_ofs		= 0xd00,
	.ale_entries		= 1024,
	.host_port_reg_ofs	= 0x108,
	.hw_stats_reg_ofs	= 0x900,
	.bd_ram_ofs		= 0x2000,
	.mac_control		= (1 << 5),
	.control		= cpsw_control,
	.host_port_num		= 0,
	.version		= CPSW_CTRL_VERSION_2,
};

int board_eth_init(bd_t *bis)
{
	int rv, ret = 0;
	uint8_t mac_addr[6];
	uint32_t mac_hi, mac_lo;

	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
		/* try reading mac address from efuse */
		mac_lo = readl(&cdev->macid0l);
		mac_hi = readl(&cdev->macid0h);
		mac_addr[0] = mac_hi & 0xFF;
		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
		mac_addr[4] = mac_lo & 0xFF;
		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
		if (is_valid_ethaddr(mac_addr))
			eth_env_set_enetaddr("ethaddr", mac_addr);
	}

	writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
	       &cdev->miisel);

	if (get_board_revision() == 1)
		cpsw_slaves[0].phy_addr = 1;

	rv = cpsw_register(&cpsw_data);
	if (rv < 0)
		printf("Error %d registering CPSW switch\n", rv);
	else
		ret += rv;

	return ret;
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
5f5c1d13	2	/*
09533e5d	3	* Board functions for IGEP COM AQUILA and SMARC AM335x based boards
5f5c1d13	4	*
09533e5d	5	* Copyright (C) 2013-2017, ISEE 2007 SL - http://www.isee.biz/
5f5c1d13 EBS	6	*/
	7
	8	#include <common.h>
9fb625ce	9	#include <env.h>
5f5c1d13	10	#include <errno.h>
5255932f	11	#include <init.h>
336d4615	12	#include <malloc.h>
90526e9f	13	#include <net.h>
b03e0510	14	#include <serial.h>
5f5c1d13 EBS	15	#include <spl.h>
	16	#include <asm/arch/cpu.h>
	17	#include <asm/arch/hardware.h>
	18	#include <asm/arch/omap.h>
	19	#include <asm/arch/ddr_defs.h>
	20	#include <asm/arch/clock.h>
	21	#include <asm/arch/gpio.h>
	22	#include <asm/arch/mmc_host_def.h>
	23	#include <asm/arch/sys_proto.h>
	24	#include <asm/io.h>
	25	#include <asm/emif.h>
	26	#include <asm/gpio.h>
	27	#include <i2c.h>
	28	#include <miiphy.h>
	29	#include <cpsw.h>
3607e0f8 LM	30	#include <fdt_support.h>
	31	#include <mtd_node.h>
	32	#include <jffs2/load_kernel.h>
5f5c1d13 EBS	33	#include "board.h"
	34
	35	DECLARE_GLOBAL_DATA_PTR;
	36
09533e5d PP	37	/* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards
	38	* and control IGEP0034 green and red LEDs.
	39	* U-boot configures these pins as input pullup to detect board revision:
	40	* IGEP0034-LITE = 0b00
	41	* IGEP0034 (FULL) = 0b01
	42	* IGEP0033 = 0b1X
	43	*/
	44	#define GPIO_GREEN_REVISION 27
	45	#define GPIO_RED_REVISION 26
	46
5f5c1d13 EBS	47	static struct ctrl_dev cdev = (struct ctrl_dev )CTRL_DEVICE_BASE;
5f5c1d13 EBS	48
09533e5d PP	49	/*
	50	* Routine: get_board_revision
	51	* Description: Returns the board revision
	52	*/
	53	static int get_board_revision(void)
	54	{
	55	int revision;
	56
	57	gpio_request(GPIO_GREEN_REVISION, "green_revision");
	58	gpio_direction_input(GPIO_GREEN_REVISION);
	59	revision = 2 * gpio_get_value(GPIO_GREEN_REVISION);
	60	gpio_free(GPIO_GREEN_REVISION);
	61
	62	gpio_request(GPIO_RED_REVISION, "red_revision");
	63	gpio_direction_input(GPIO_RED_REVISION);
	64	revision = revision + gpio_get_value(GPIO_RED_REVISION);
	65	gpio_free(GPIO_RED_REVISION);
	66
	67	return revision;
	68	}
	69
5f5c1d13	70	#ifdef CONFIG_SPL_BUILD
09533e5d PP	71	/* PN H5TQ4G63AFR is equivalent to MT41K256M16HA125*/
	72	static const struct ddr_data ddr3_igep0034_data = {
	73	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
	74	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
	75	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
	76	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
	77	};
	78
	79	static const struct ddr_data ddr3_igep0034_lite_data = {
5f5c1d13 EBS	80	.datardsratio0 = K4B2G1646EBIH9_RD_DQS,
	81	.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
	82	.datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
	83	.datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
5f5c1d13 EBS	84	};
5f5c1d13 EBS	85
09533e5d PP	86	static const struct cmd_control ddr3_igep0034_cmd_ctrl_data = {
	87	.cmd0csratio = MT41K256M16HA125E_RATIO,
	88	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
	89
	90	.cmd1csratio = MT41K256M16HA125E_RATIO,
	91	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
	92
	93	.cmd2csratio = MT41K256M16HA125E_RATIO,
	94	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
	95	};
	96
	97	static const struct cmd_control ddr3_igep0034_lite_cmd_ctrl_data = {
5f5c1d13	98	.cmd0csratio = K4B2G1646EBIH9_RATIO,
5f5c1d13 EBS	99	.cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
	100
	101	.cmd1csratio = K4B2G1646EBIH9_RATIO,
5f5c1d13 EBS	102	.cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
	103
	104	.cmd2csratio = K4B2G1646EBIH9_RATIO,
5f5c1d13 EBS	105	.cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
	106	};
	107
09533e5d PP	108	static struct emif_regs ddr3_igep0034_emif_reg_data = {
	109	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
	110	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
	111	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
	112	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
	113	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
	114	.zq_config = MT41K256M16HA125E_ZQ_CFG,
	115	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
	116	};
	117
	118	static struct emif_regs ddr3_igep0034_lite_emif_reg_data = {
5f5c1d13 EBS	119	.sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
	120	.ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
	121	.sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
	122	.sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
	123	.sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
	124	.zq_config = K4B2G1646EBIH9_ZQ_CFG,
	125	.emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
	126	};
94d77fb6	127
09533e5d PP	128	const struct ctrl_ioregs ioregs_igep0034 = {
	129	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	130	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	131	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	132	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	133	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	134	};
	135
	136	const struct ctrl_ioregs ioregs_igep0034_lite = {
	137	.cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
	138	.cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
	139	.cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
	140	.dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
	141	.dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
	142	};
	143
94d77fb6 LV	144	#define OSC (V_OSCK/1000000)
94d77fb6 LV	145	const struct dpll_params dpll_ddr = {
94b32f60	146	400, OSC-1, 1, -1, -1, -1, -1};
94d77fb6 LV	147
	148	const struct dpll_params *get_dpll_ddr_params(void)
	149	{
	150	return &dpll_ddr;
	151	}
	152
0660481a	153	void set_uart_mux_conf(void)
5f5c1d13	154	{
5f5c1d13	155	enable_uart0_pin_mux();
0660481a	156	}
5f5c1d13	157
0660481a HS	158	void set_mux_conf_regs(void)
0660481a HS	159	{
5f5c1d13	160	enable_board_pin_mux();
0660481a	161	}
5f5c1d13	162
0660481a HS	163	void sdram_init(void)
0660481a HS	164	{
09533e5d PP	165	if (get_board_revision() == 1)
	166	config_ddr(400, &ioregs_igep0034, &ddr3_igep0034_data,
	167	&ddr3_igep0034_cmd_ctrl_data, &ddr3_igep0034_emif_reg_data, 0);
	168	else
	169	config_ddr(400, &ioregs_igep0034_lite, &ddr3_igep0034_lite_data,
	170	&ddr3_igep0034_lite_cmd_ctrl_data, &ddr3_igep0034_lite_emif_reg_data, 0);
5f5c1d13	171	}
ab3b7770 LM	172
	173	#ifdef CONFIG_SPL_OS_BOOT
	174	int spl_start_uboot(void)
	175	{
	176	/* break into full u-boot on 'c' */
	177	return serial_tstc() && serial_getc() == 'c';
	178	}
	179	#endif
0660481a	180	#endif
5f5c1d13 EBS	181
	182	/*
	183	* Basic board specific setup. Pinmux has been handled already.
	184	*/
	185	int board_init(void)
	186	{
73feefdc	187	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
5f5c1d13 EBS	188
	189	gpmc_init();
	190
	191	return 0;
	192	}
	193
09533e5d PP	194	#ifdef CONFIG_BOARD_LATE_INIT
	195	int board_late_init(void)
	196	{
	197	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	198	switch (get_board_revision()) {
	199	case 0:
382bee57	200	env_set("board_name", "igep0034-lite");
09533e5d PP	201	break;
09533e5d PP	202	case 1:
382bee57	203	env_set("board_name", "igep0034");
09533e5d PP	204	break;
09533e5d PP	205	default:
382bee57	206	env_set("board_name", "igep0033");
09533e5d PP	207	break;
	208	}
	209	#endif
	210	return 0;
	211	}
	212	#endif
	213
3607e0f8 LM	214	#ifdef CONFIG_OF_BOARD_SETUP
	215	int ft_board_setup(void blob, bd_t bd)
	216	{
	217	#ifdef CONFIG_FDT_FIXUP_PARTITIONS
b35fb6ac	218	static const struct node_info nodes[] = {
3607e0f8 LM	219	{ "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
	220	};
	221
	222	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
	223	#endif
	224	return 0;
	225	}
	226	#endif
	227
5f5c1d13 EBS	228	#if defined(CONFIG_DRIVER_TI_CPSW)
	229	static void cpsw_control(int enabled)
	230	{
	231	/* VTP can be added here */
	232
	233	return;
	234	}
	235
	236	static struct cpsw_slave_data cpsw_slaves[] = {
	237	{
	238	.slave_reg_ofs = 0x208,
	239	.sliver_reg_ofs = 0xd80,
9c653aad	240	.phy_addr = 0,
5f5c1d13 EBS	241	.phy_if = PHY_INTERFACE_MODE_RMII,
	242	},
	243	};
	244
	245	static struct cpsw_platform_data cpsw_data = {
	246	.mdio_base = CPSW_MDIO_BASE,
	247	.cpsw_base = CPSW_BASE,
	248	.mdio_div = 0xff,
	249	.channels = 8,
	250	.cpdma_reg_ofs = 0x800,
	251	.slaves = 1,
	252	.slave_data = cpsw_slaves,
	253	.ale_reg_ofs = 0xd00,
	254	.ale_entries = 1024,
	255	.host_port_reg_ofs = 0x108,
	256	.hw_stats_reg_ofs = 0x900,
6478cde6	257	.bd_ram_ofs = 0x2000,
5f5c1d13 EBS	258	.mac_control = (1 << 5),
	259	.control = cpsw_control,
	260	.host_port_num = 0,
	261	.version = CPSW_CTRL_VERSION_2,
	262	};
	263
	264	int board_eth_init(bd_t *bis)
	265	{
	266	int rv, ret = 0;
	267	uint8_t mac_addr[6];
	268	uint32_t mac_hi, mac_lo;
	269
35affd7a	270	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
5f5c1d13 EBS	271	/* try reading mac address from efuse */
	272	mac_lo = readl(&cdev->macid0l);
	273	mac_hi = readl(&cdev->macid0h);
	274	mac_addr[0] = mac_hi & 0xFF;
	275	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	276	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
	277	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
	278	mac_addr[4] = mac_lo & 0xFF;
	279	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
0adb5b76	280	if (is_valid_ethaddr(mac_addr))
fd1e959e	281	eth_env_set_enetaddr("ethaddr", mac_addr);
5f5c1d13 EBS	282	}
5f5c1d13 EBS	283
dafd4db3 HS	284	writel((GMII1_SEL_RMII \| RMII1_IO_CLK_EN),
dafd4db3 HS	285	&cdev->miisel);
5f5c1d13	286
09533e5d PP	287	if (get_board_revision() == 1)
	288	cpsw_slaves[0].phy_addr = 1;
	289
5f5c1d13 EBS	290	rv = cpsw_register(&cpsw_data);
	291	if (rv < 0)
	292	printf("Error %d registering CPSW switch\n", rv);
	293	else
	294	ret += rv;
	295
	296	return ret;
	297	}
	298	#endif