[u-boot.git] / board / bosch / shc / board.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * board.c
 *
 * (C) Copyright 2016
 * Heiko Schocher, DENX Software Engineering, [email protected].
 *
 * Based on:
 * Board functions for TI AM335X based boards
 *
 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
 */

#include <common.h>
#include <cpu_func.h>
#include <env.h>
#include <errno.h>
#include <init.h>
#include <irq_func.h>
#include <net.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include <power/tps65217.h>
#include <env_internal.h>
#include <watchdog.h>
#include "mmc.h"
#include "board.h"

DECLARE_GLOBAL_DATA_PTR;

static struct shc_eeprom __attribute__((section(".data"))) header;
static int shc_eeprom_valid;

/*
 * Read header information from EEPROM into global structure.
 */
static int read_eeprom(void)
{
	/* Check if baseboard eeprom is available */
	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
		puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
		return -ENODEV;
	}

	/* read the eeprom using i2c */
	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
		     sizeof(header))) {
		puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
		return -EIO;
	}

	if (header.magic != HDR_MAGIC) {
		printf("Incorrect magic number (0x%x) in EEPROM\n",
		       header.magic);
		return -EIO;
	}

	shc_eeprom_valid = 1;

	return 0;
}

static void shc_request_gpio(void)
{
	gpio_request(LED_PWR_BL_GPIO, "LED PWR BL");
	gpio_request(LED_PWR_RD_GPIO, "LED PWR RD");
	gpio_request(RESET_GPIO, "reset");
	gpio_request(WIFI_REGEN_GPIO, "WIFI REGEN");
	gpio_request(WIFI_RST_GPIO, "WIFI rst");
	gpio_request(ZIGBEE_RST_GPIO, "ZigBee rst");
	gpio_request(BIDCOS_RST_GPIO, "BIDCOS rst");
	gpio_request(ENOC_RST_GPIO, "ENOC rst");
#if defined CONFIG_B_SAMPLE
	gpio_request(LED_PWR_GN_GPIO, "LED PWR GN");
	gpio_request(LED_CONN_BL_GPIO, "LED CONN BL");
	gpio_request(LED_CONN_RD_GPIO, "LED CONN RD");
	gpio_request(LED_CONN_GN_GPIO, "LED CONN GN");
#else
	gpio_request(LED_LAN_BL_GPIO, "LED LAN BL");
	gpio_request(LED_LAN_RD_GPIO, "LED LAN RD");
	gpio_request(LED_CLOUD_BL_GPIO, "LED CLOUD BL");
	gpio_request(LED_CLOUD_RD_GPIO, "LED CLOUD RD");
	gpio_request(LED_PWM_GPIO, "LED PWM");
	gpio_request(Z_WAVE_RST_GPIO, "Z WAVE rst");
#endif
	gpio_request(BACK_BUTTON_GPIO, "Back button");
	gpio_request(FRONT_BUTTON_GPIO, "Front button");
}

/*
 * Function which forces all installed modules into running state for ICT
 * testing. Called by SPL.
 */
static void __maybe_unused force_modules_running(void)
{
	/* Wi-Fi power regulator enable - high = enabled */
	gpio_direction_output(WIFI_REGEN_GPIO, 1);
	/*
	 * Wait for Wi-Fi power regulator to reach a stable voltage
	 * (soft-start time, max. 350 µs)
	 */
	__udelay(350);

	/* Wi-Fi module reset - high = running */
	gpio_direction_output(WIFI_RST_GPIO, 1);

	/* ZigBee reset - high = running */
	gpio_direction_output(ZIGBEE_RST_GPIO, 1);

	/* BidCos reset - high = running */
	gpio_direction_output(BIDCOS_RST_GPIO, 1);

#if !defined(CONFIG_B_SAMPLE)
	/* Z-Wave reset - high = running */
	gpio_direction_output(Z_WAVE_RST_GPIO, 1);
#endif

	/* EnOcean reset - low = running */
	gpio_direction_output(ENOC_RST_GPIO, 0);
}

/*
 * Function which forces all installed modules into reset - to be released by
 * the OS, called by SPL
 */
static void __maybe_unused force_modules_reset(void)
{
	/* Wi-Fi module reset - low = reset */
	gpio_direction_output(WIFI_RST_GPIO, 0);

	/* Wi-Fi power regulator enable - low = disabled */
	gpio_direction_output(WIFI_REGEN_GPIO, 0);

	/* ZigBee reset - low = reset */
	gpio_direction_output(ZIGBEE_RST_GPIO, 0);

	/* BidCos reset - low = reset */
	/*gpio_direction_output(BIDCOS_RST_GPIO, 0);*/

#if !defined(CONFIG_B_SAMPLE)
	/* Z-Wave reset - low = reset */
	gpio_direction_output(Z_WAVE_RST_GPIO, 0);
#endif

	/* EnOcean reset - high = reset*/
	gpio_direction_output(ENOC_RST_GPIO, 1);
}

/*
 * Function to set the LEDs in the state "Bootloader booting"
 */
static void __maybe_unused leds_set_booting(void)
{
#if defined(CONFIG_B_SAMPLE)

	/* Turn all red LEDs on */
	gpio_direction_output(LED_PWR_RD_GPIO, 1);
	gpio_direction_output(LED_CONN_RD_GPIO, 1);

#else /* All other SHCs starting with B2-Sample */
	/* Set the PWM GPIO */
	gpio_direction_output(LED_PWM_GPIO, 1);
	/* Turn all red LEDs on */
	gpio_direction_output(LED_PWR_RD_GPIO, 1);
	gpio_direction_output(LED_LAN_RD_GPIO, 1);
	gpio_direction_output(LED_CLOUD_RD_GPIO, 1);

#endif
}

/*
 * Function to set the LEDs in the state "Bootloader error"
 */
static void leds_set_failure(int state)
{
#if defined(CONFIG_B_SAMPLE)
	/* Turn all blue and green LEDs off */
	gpio_set_value(LED_PWR_BL_GPIO, 0);
	gpio_set_value(LED_PWR_GN_GPIO, 0);
	gpio_set_value(LED_CONN_BL_GPIO, 0);
	gpio_set_value(LED_CONN_GN_GPIO, 0);

	/* Turn all red LEDs to 'state' */
	gpio_set_value(LED_PWR_RD_GPIO, state);
	gpio_set_value(LED_CONN_RD_GPIO, state);

#else /* All other SHCs starting with B2-Sample */
	/* Set the PWM GPIO */
	gpio_direction_output(LED_PWM_GPIO, 1);

	/* Turn all blue LEDs off */
	gpio_set_value(LED_PWR_BL_GPIO, 0);
	gpio_set_value(LED_LAN_BL_GPIO, 0);
	gpio_set_value(LED_CLOUD_BL_GPIO, 0);

	/* Turn all red LEDs to 'state' */
	gpio_set_value(LED_PWR_RD_GPIO, state);
	gpio_set_value(LED_LAN_RD_GPIO, state);
	gpio_set_value(LED_CLOUD_RD_GPIO, state);
#endif
}

/*
 * Function to set the LEDs in the state "Bootloader finished"
 */
static void leds_set_finish(void)
{
#if defined(CONFIG_B_SAMPLE)
	/* Turn all LEDs off */
	gpio_set_value(LED_PWR_BL_GPIO, 0);
	gpio_set_value(LED_PWR_RD_GPIO, 0);
	gpio_set_value(LED_PWR_GN_GPIO, 0);
	gpio_set_value(LED_CONN_BL_GPIO, 0);
	gpio_set_value(LED_CONN_RD_GPIO, 0);
	gpio_set_value(LED_CONN_GN_GPIO, 0);
#else /* All other SHCs starting with B2-Sample */
	/* Turn all LEDs off */
	gpio_set_value(LED_PWR_BL_GPIO, 0);
	gpio_set_value(LED_PWR_RD_GPIO, 0);
	gpio_set_value(LED_LAN_BL_GPIO, 0);
	gpio_set_value(LED_LAN_RD_GPIO, 0);
	gpio_set_value(LED_CLOUD_BL_GPIO, 0);
	gpio_set_value(LED_CLOUD_RD_GPIO, 0);

	/* Turn off the PWM GPIO and mux it to EHRPWM */
	gpio_set_value(LED_PWM_GPIO, 0);
	enable_shc_board_pwm_pin_mux();
#endif
}

static void check_button_status(void)
{
	ulong value;
	gpio_direction_input(FRONT_BUTTON_GPIO);
	value = gpio_get_value(FRONT_BUTTON_GPIO);

	if (value == 0) {
		printf("front button activated !\n");
		env_set("harakiri", "1");
	}
}

#if defined(CONFIG_SPL_BUILD)
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
	return 1;
}
#endif

static void shc_board_early_init(void)
{
	shc_request_gpio();
# ifdef CONFIG_SHC_ICT
	/* Force all modules into enabled state for ICT testing */
	force_modules_running();
# else
	/* Force all modules to enter Reset state until released by the OS */
	force_modules_reset();
# endif
	leds_set_booting();
}

static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;

#define MPU_SPREADING_PERMILLE 18 /* Spread 1.8 percent */
#define OSC	(V_OSCK/1000000)
/* Bosch: Predivider must be fixed to 4, so N = 4-1 */
#define MPUPLL_N        (4-1)
/* Bosch: Fref = 24 MHz / (N+1) = 24 MHz / 4 = 6 MHz */
#define MPUPLL_FREF (OSC / (MPUPLL_N + 1))

const struct dpll_params dpll_ddr_shc = {
		400, OSC-1, 1, -1, -1, -1, -1};

const struct dpll_params *get_dpll_ddr_params(void)
{
	return &dpll_ddr_shc;
}

/*
 * As we enabled downspread SSC with 1.8%, the values needed to be corrected
 * such that the 20% overshoot will not lead to too high frequencies.
 * In all cases, this is achieved by subtracting one from M (6 MHz less).
 * Example: 600 MHz CPU
 *   Step size: 24 MHz OSC, N = 4 (fix) --> Fref = 6 MHz
 *   600 MHz - 6 MHz (1x Fref) = 594 MHz
 *   SSC: 594 MHz * 1.8% = 10.7 MHz SSC
 *   Overshoot: 10.7 MHz * 20 % = 2.2 MHz
 *   --> Fmax = 594 MHz + 2.2 MHz = 596.2 MHz, lower than 600 MHz --> OK!
 */
const struct dpll_params dpll_mpu_shc_opp100 = {
		99, MPUPLL_N, 1, -1, -1, -1, -1};

void am33xx_spl_board_init(void)
{
	int sil_rev;
	int mpu_vdd;

	puts(BOARD_ID_STR);

	/*
	 * Set CORE Frequency to OPP100
	 * Hint: DCDC3 (CORE) defaults to 1.100V (for OPP100)
	 */
	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);

	sil_rev = readl(&cdev->deviceid) >> 28;
	if (sil_rev < 2) {
		puts("We do not support Silicon Revisions below 2.0!\n");
		return;
	}

	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
	if (i2c_probe(TPS65217_CHIP_PM))
		return;

	/*
	 * Retrieve the CPU max frequency by reading the efuse
	 * SHC-Default: 600 MHz
	 */
	switch (dpll_mpu_opp100.m) {
	case MPUPLL_M_1000:
		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
		break;
	case MPUPLL_M_800:
		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
		break;
	case MPUPLL_M_720:
		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
		break;
	case MPUPLL_M_600:
		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
		break;
	case MPUPLL_M_300:
		mpu_vdd = TPS65217_DCDC_VOLT_SEL_950MV;
		break;
	default:
		puts("Cannot determine the frequency, failing!\n");
		return;
	}

	if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
		puts("tps65217_voltage_update failure\n");
		return;
	}

	/* Set MPU Frequency to what we detected */
	printf("MPU reference clock runs at %d MHz\n", MPUPLL_FREF);
	printf("Setting MPU clock to %d MHz\n", MPUPLL_FREF *
	       dpll_mpu_shc_opp100.m);
	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_shc_opp100);

	/* Enable Spread Spectrum for this freq to be clean on EMI side */
	set_mpu_spreadspectrum(MPU_SPREADING_PERMILLE);

	/*
	 * Using the default voltages for the PMIC (TPS65217D)
	 * LS1 = 1.8V (VDD_1V8)
	 * LS2 = 3.3V (VDD_3V3A)
	 * LDO1 = 1.8V (VIO and VRTC)
	 * LDO2 = 3.3V (VDD_3V3AUX)
	 */
	shc_board_early_init();
}

void set_uart_mux_conf(void)
{
	enable_uart0_pin_mux();
}

void set_mux_conf_regs(void)
{
	enable_shc_board_pin_mux();
}

const struct ctrl_ioregs ioregs_evmsk = {
	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
};

static const struct ddr_data ddr3_shc_data = {
	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
};

static const struct cmd_control ddr3_shc_cmd_ctrl_data = {
	.cmd0csratio = MT41K256M16HA125E_RATIO,
	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,

	.cmd1csratio = MT41K256M16HA125E_RATIO,
	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,

	.cmd2csratio = MT41K256M16HA125E_RATIO,
	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};

static struct emif_regs ddr3_shc_emif_reg_data = {
	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
	.zq_config = MT41K256M16HA125E_ZQ_CFG,
	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
				PHY_EN_DYN_PWRDN,
};

void sdram_init(void)
{
	/* Configure the DDR3 RAM */
	config_ddr(400, &ioregs_evmsk, &ddr3_shc_data,
		   &ddr3_shc_cmd_ctrl_data, &ddr3_shc_emif_reg_data, 0);
}
#endif

/*
 * Basic board specific setup.  Pinmux has been handled already.
 */
int board_init(void)
{
#if defined(CONFIG_HW_WATCHDOG)
	hw_watchdog_init();
#endif
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	if (read_eeprom() < 0)
		puts("EEPROM Content Invalid.\n");

	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
	gpmc_init();
#endif
	shc_request_gpio();

	return 0;
}

#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
	check_button_status();
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	if (shc_eeprom_valid)
		if (is_valid_ethaddr(header.mac_addr))
			eth_env_set_enetaddr("ethaddr", header.mac_addr);
#endif

	return 0;
}
#endif

#if defined(CONFIG_USB_ETHER) && \
	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
int board_eth_init(bd_t *bis)
{
	return usb_eth_initialize(bis);
}
#endif

#ifdef CONFIG_SHOW_BOOT_PROGRESS
static void bosch_check_reset_pin(void)
{
	if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) {
		printf("Resetting ...\n");
		writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
		disable_interrupts();
		reset_cpu(0);
		/*NOTREACHED*/
	}
}

static void hang_bosch(const char *cause, int code)
{
	int lv;

	gpio_direction_input(RESET_GPIO);

	/* Enable reset pin interrupt on falling edge */
	writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
	writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_FALLINGDETECT);
	enable_interrupts();

	puts(cause);
	for (;;) {
		for (lv = 0; lv < code; lv++) {
			bosch_check_reset_pin();
			leds_set_failure(1);
			__udelay(150 * 1000);
			leds_set_failure(0);
			__udelay(150 * 1000);
		}
#if defined(BLINK_CODE)
		__udelay(300 * 1000);
#endif
	}
}

void show_boot_progress(int val)
{
	switch (val) {
	case BOOTSTAGE_ID_NEED_RESET:
		hang_bosch("need reset", 4);
		break;
	}
}

void arch_preboot_os(void)
{
	leds_set_finish();
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
d8ccbe93 HS	2	/*
	3	* board.c
	4	*
	5	* (C) Copyright 2016
	6	* Heiko Schocher, DENX Software Engineering, [email protected].
	7	*
	8	* Based on:
	9	* Board functions for TI AM335X based boards
	10	*
	11	* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
d8ccbe93 HS	12	*/
	13
	14	#include <common.h>
9a3b4ceb	15	#include <cpu_func.h>
9fb625ce	16	#include <env.h>
d8ccbe93	17	#include <errno.h>
5255932f	18	#include <init.h>
36bf446b	19	#include <irq_func.h>
90526e9f	20	#include <net.h>
d8ccbe93 HS	21	#include <spl.h>
	22	#include <asm/arch/cpu.h>
	23	#include <asm/arch/hardware.h>
	24	#include <asm/arch/omap.h>
	25	#include <asm/arch/ddr_defs.h>
	26	#include <asm/arch/clock.h>
	27	#include <asm/arch/gpio.h>
	28	#include <asm/arch/mmc_host_def.h>
	29	#include <asm/arch/sys_proto.h>
	30	#include <asm/arch/mem.h>
	31	#include <asm/io.h>
	32	#include <asm/emif.h>
	33	#include <asm/gpio.h>
	34	#include <i2c.h>
	35	#include <miiphy.h>
	36	#include <cpsw.h>
	37	#include <power/tps65217.h>
f3998fdc	38	#include <env_internal.h>
d8ccbe93	39	#include <watchdog.h>
d8ccbe93 HS	40	#include "mmc.h"
	41	#include "board.h"
	42
	43	DECLARE_GLOBAL_DATA_PTR;
	44
d8ccbe93 HS	45	static struct shc_eeprom __attribute__((section(".data"))) header;
	46	static int shc_eeprom_valid;
	47
	48	/*
	49	* Read header information from EEPROM into global structure.
	50	*/
	51	static int read_eeprom(void)
	52	{
	53	/* Check if baseboard eeprom is available */
	54	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
	55	puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
	56	return -ENODEV;
	57	}
	58
	59	/* read the eeprom using i2c */
	60	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
	61	sizeof(header))) {
	62	puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
	63	return -EIO;
	64	}
	65
	66	if (header.magic != HDR_MAGIC) {
	67	printf("Incorrect magic number (0x%x) in EEPROM\n",
	68	header.magic);
	69	return -EIO;
	70	}
	71
	72	shc_eeprom_valid = 1;
	73
	74	return 0;
	75	}
	76
	77	static void shc_request_gpio(void)
	78	{
	79	gpio_request(LED_PWR_BL_GPIO, "LED PWR BL");
	80	gpio_request(LED_PWR_RD_GPIO, "LED PWR RD");
	81	gpio_request(RESET_GPIO, "reset");
	82	gpio_request(WIFI_REGEN_GPIO, "WIFI REGEN");
	83	gpio_request(WIFI_RST_GPIO, "WIFI rst");
	84	gpio_request(ZIGBEE_RST_GPIO, "ZigBee rst");
	85	gpio_request(BIDCOS_RST_GPIO, "BIDCOS rst");
	86	gpio_request(ENOC_RST_GPIO, "ENOC rst");
	87	#if defined CONFIG_B_SAMPLE
	88	gpio_request(LED_PWR_GN_GPIO, "LED PWR GN");
	89	gpio_request(LED_CONN_BL_GPIO, "LED CONN BL");
	90	gpio_request(LED_CONN_RD_GPIO, "LED CONN RD");
	91	gpio_request(LED_CONN_GN_GPIO, "LED CONN GN");
	92	#else
	93	gpio_request(LED_LAN_BL_GPIO, "LED LAN BL");
	94	gpio_request(LED_LAN_RD_GPIO, "LED LAN RD");
	95	gpio_request(LED_CLOUD_BL_GPIO, "LED CLOUD BL");
	96	gpio_request(LED_CLOUD_RD_GPIO, "LED CLOUD RD");
	97	gpio_request(LED_PWM_GPIO, "LED PWM");
	98	gpio_request(Z_WAVE_RST_GPIO, "Z WAVE rst");
	99	#endif
	100	gpio_request(BACK_BUTTON_GPIO, "Back button");
	101	gpio_request(FRONT_BUTTON_GPIO, "Front button");
	102	}
	103
	104	/*
	105	* Function which forces all installed modules into running state for ICT
	106	* testing. Called by SPL.
	107	*/
	108	static void __maybe_unused force_modules_running(void)
109	{
110	/* Wi-Fi power regulator enable - high = enabled */
111	gpio_direction_output(WIFI_REGEN_GPIO, 1);
112	/*
113	* Wait for Wi-Fi power regulator to reach a stable voltage
114	* (soft-start time, max. 350 µs)
115	*/
116	__udelay(350);
117
118	/* Wi-Fi module reset - high = running */
119	gpio_direction_output(WIFI_RST_GPIO, 1);
120
121	/* ZigBee reset - high = running */
122	gpio_direction_output(ZIGBEE_RST_GPIO, 1);
123
124	/* BidCos reset - high = running */
125	gpio_direction_output(BIDCOS_RST_GPIO, 1);
126
127	#if !defined(CONFIG_B_SAMPLE)
128	/* Z-Wave reset - high = running */
129	gpio_direction_output(Z_WAVE_RST_GPIO, 1);
130	#endif
131
132	/* EnOcean reset - low = running */
133	gpio_direction_output(ENOC_RST_GPIO, 0);
134	}
135
136	/*
137	* Function which forces all installed modules into reset - to be released by
138	* the OS, called by SPL
139	*/
140	static void __maybe_unused force_modules_reset(void)
141	{
142	/* Wi-Fi module reset - low = reset */
143	gpio_direction_output(WIFI_RST_GPIO, 0);
144
145	/* Wi-Fi power regulator enable - low = disabled */
146	gpio_direction_output(WIFI_REGEN_GPIO, 0);
147
148	/* ZigBee reset - low = reset */
149	gpio_direction_output(ZIGBEE_RST_GPIO, 0);
150
151	/* BidCos reset - low = reset */
152	/gpio_direction_output(BIDCOS_RST_GPIO, 0);/
153
154	#if !defined(CONFIG_B_SAMPLE)
155	/* Z-Wave reset - low = reset */
156	gpio_direction_output(Z_WAVE_RST_GPIO, 0);
157	#endif
158
159	/* EnOcean reset - high = reset*/
160	gpio_direction_output(ENOC_RST_GPIO, 1);
161	}
162
163	/*
164	* Function to set the LEDs in the state "Bootloader booting"
165	*/
166	static void __maybe_unused leds_set_booting(void)
167	{
168	#if defined(CONFIG_B_SAMPLE)
169
170	/* Turn all red LEDs on */
171	gpio_direction_output(LED_PWR_RD_GPIO, 1);
172	gpio_direction_output(LED_CONN_RD_GPIO, 1);
173
174	#else /* All other SHCs starting with B2-Sample */
175	/* Set the PWM GPIO */
176	gpio_direction_output(LED_PWM_GPIO, 1);
177	/* Turn all red LEDs on */
178	gpio_direction_output(LED_PWR_RD_GPIO, 1);
179	gpio_direction_output(LED_LAN_RD_GPIO, 1);
180	gpio_direction_output(LED_CLOUD_RD_GPIO, 1);
181
182	#endif
183	}
184
185	/*
186	* Function to set the LEDs in the state "Bootloader error"
187	*/
188	static void leds_set_failure(int state)
189	{
190	#if defined(CONFIG_B_SAMPLE)
191	/* Turn all blue and green LEDs off */
192	gpio_set_value(LED_PWR_BL_GPIO, 0);
193	gpio_set_value(LED_PWR_GN_GPIO, 0);
194	gpio_set_value(LED_CONN_BL_GPIO, 0);
195	gpio_set_value(LED_CONN_GN_GPIO, 0);
196
197	/* Turn all red LEDs to 'state' */
198	gpio_set_value(LED_PWR_RD_GPIO, state);
199	gpio_set_value(LED_CONN_RD_GPIO, state);
200
201	#else /* All other SHCs starting with B2-Sample */
202	/* Set the PWM GPIO */
203	gpio_direction_output(LED_PWM_GPIO, 1);
204
205	/* Turn all blue LEDs off */
206	gpio_set_value(LED_PWR_BL_GPIO, 0);
207	gpio_set_value(LED_LAN_BL_GPIO, 0);
208	gpio_set_value(LED_CLOUD_BL_GPIO, 0);
209
210	/* Turn all red LEDs to 'state' */
211	gpio_set_value(LED_PWR_RD_GPIO, state);
212	gpio_set_value(LED_LAN_RD_GPIO, state);
213	gpio_set_value(LED_CLOUD_RD_GPIO, state);
214	#endif
215	}
216
217	/*
218	* Function to set the LEDs in the state "Bootloader finished"
219	*/
220	static void leds_set_finish(void)
221	{
222	#if defined(CONFIG_B_SAMPLE)
223	/* Turn all LEDs off */
224	gpio_set_value(LED_PWR_BL_GPIO, 0);
225	gpio_set_value(LED_PWR_RD_GPIO, 0);
226	gpio_set_value(LED_PWR_GN_GPIO, 0);
227	gpio_set_value(LED_CONN_BL_GPIO, 0);
228	gpio_set_value(LED_CONN_RD_GPIO, 0);
229	gpio_set_value(LED_CONN_GN_GPIO, 0);
230	#else /* All other SHCs starting with B2-Sample */
231	/* Turn all LEDs off */
232	gpio_set_value(LED_PWR_BL_GPIO, 0);
233	gpio_set_value(LED_PWR_RD_GPIO, 0);
234	gpio_set_value(LED_LAN_BL_GPIO, 0);
235	gpio_set_value(LED_LAN_RD_GPIO, 0);
236	gpio_set_value(LED_CLOUD_BL_GPIO, 0);
237	gpio_set_value(LED_CLOUD_RD_GPIO, 0);
238
239	/* Turn off the PWM GPIO and mux it to EHRPWM */
240	gpio_set_value(LED_PWM_GPIO, 0);
241	enable_shc_board_pwm_pin_mux();
242	#endif
243	}
244
245	static void check_button_status(void)
246	{
247	ulong value;
248	gpio_direction_input(FRONT_BUTTON_GPIO);
249	value = gpio_get_value(FRONT_BUTTON_GPIO);
250
251	if (value == 0) {
252	printf("front button activated !\n");
382bee57	253	env_set("harakiri", "1");
d8ccbe93 HS	254	}
	255	}
	256
a36c70a3	257	#if defined(CONFIG_SPL_BUILD)
d8ccbe93 HS	258	#ifdef CONFIG_SPL_OS_BOOT
	259	int spl_start_uboot(void)
	260	{
	261	return 1;
	262	}
	263	#endif
	264
	265	static void shc_board_early_init(void)
	266	{
	267	shc_request_gpio();
	268	# ifdef CONFIG_SHC_ICT
	269	/* Force all modules into enabled state for ICT testing */
	270	force_modules_running();
	271	# else
	272	/* Force all modules to enter Reset state until released by the OS */
	273	force_modules_reset();
	274	# endif
	275	leds_set_booting();
	276	}
	277
a36c70a3 HS	278	static struct ctrl_dev cdev = (struct ctrl_dev )CTRL_DEVICE_BASE;
a36c70a3 HS	279
d8ccbe93 HS	280	#define MPU_SPREADING_PERMILLE 18 /* Spread 1.8 percent */
	281	#define OSC (V_OSCK/1000000)
	282	/* Bosch: Predivider must be fixed to 4, so N = 4-1 */
	283	#define MPUPLL_N (4-1)
	284	/* Bosch: Fref = 24 MHz / (N+1) = 24 MHz / 4 = 6 MHz */
	285	#define MPUPLL_FREF (OSC / (MPUPLL_N + 1))
	286
	287	const struct dpll_params dpll_ddr_shc = {
	288	400, OSC-1, 1, -1, -1, -1, -1};
	289
	290	const struct dpll_params *get_dpll_ddr_params(void)
	291	{
	292	return &dpll_ddr_shc;
	293	}
	294
	295	/*
	296	* As we enabled downspread SSC with 1.8%, the values needed to be corrected
	297	* such that the 20% overshoot will not lead to too high frequencies.
	298	* In all cases, this is achieved by subtracting one from M (6 MHz less).
	299	* Example: 600 MHz CPU
	300	* Step size: 24 MHz OSC, N = 4 (fix) --> Fref = 6 MHz
	301	* 600 MHz - 6 MHz (1x Fref) = 594 MHz
	302	* SSC: 594 MHz * 1.8% = 10.7 MHz SSC
	303	* Overshoot: 10.7 MHz * 20 % = 2.2 MHz
	304	* --> Fmax = 594 MHz + 2.2 MHz = 596.2 MHz, lower than 600 MHz --> OK!
	305	*/
	306	const struct dpll_params dpll_mpu_shc_opp100 = {
	307	99, MPUPLL_N, 1, -1, -1, -1, -1};
	308
	309	void am33xx_spl_board_init(void)
	310	{
	311	int sil_rev;
	312	int mpu_vdd;
	313
	314	puts(BOARD_ID_STR);
	315
	316	/*
	317	* Set CORE Frequency to OPP100
	318	* Hint: DCDC3 (CORE) defaults to 1.100V (for OPP100)
	319	*/
	320	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
	321
	322	sil_rev = readl(&cdev->deviceid) >> 28;
	323	if (sil_rev < 2) {
	324	puts("We do not support Silicon Revisions below 2.0!\n");
	325	return;
	326	}
	327
	328	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
	329	if (i2c_probe(TPS65217_CHIP_PM))
	330	return;
	331
	332	/*
	333	* Retrieve the CPU max frequency by reading the efuse
	334	* SHC-Default: 600 MHz
	335	*/
	336	switch (dpll_mpu_opp100.m) {
	337	case MPUPLL_M_1000:
	338	mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
	339	break;
	340	case MPUPLL_M_800:
	341	mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
	342	break;
	343	case MPUPLL_M_720:
344	mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
345	break;
346	case MPUPLL_M_600:
347	mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
348	break;
349	case MPUPLL_M_300:
350	mpu_vdd = TPS65217_DCDC_VOLT_SEL_950MV;
351	break;
352	default:
353	puts("Cannot determine the frequency, failing!\n");
354	return;
355	}
356
357	if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
358	puts("tps65217_voltage_update failure\n");
359	return;
360	}
361
362	/* Set MPU Frequency to what we detected */
363	printf("MPU reference clock runs at %d MHz\n", MPUPLL_FREF);
364	printf("Setting MPU clock to %d MHz\n", MPUPLL_FREF *
365	dpll_mpu_shc_opp100.m);
366	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_shc_opp100);
367
368	/* Enable Spread Spectrum for this freq to be clean on EMI side */
369	set_mpu_spreadspectrum(MPU_SPREADING_PERMILLE);
370
371	/*
372	* Using the default voltages for the PMIC (TPS65217D)
373	* LS1 = 1.8V (VDD_1V8)
374	* LS2 = 3.3V (VDD_3V3A)
375	* LDO1 = 1.8V (VIO and VRTC)
376	* LDO2 = 3.3V (VDD_3V3AUX)
377	*/
378	shc_board_early_init();
379	}
380
381	void set_uart_mux_conf(void)
382	{
383	enable_uart0_pin_mux();
384	}
385
386	void set_mux_conf_regs(void)
387	{
388	enable_shc_board_pin_mux();
389	}
390
391	const struct ctrl_ioregs ioregs_evmsk = {
392	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
393	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
394	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
395	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
396	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
397	};
398
399	static const struct ddr_data ddr3_shc_data = {
400	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
401	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
402	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
403	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
404	};
405
406	static const struct cmd_control ddr3_shc_cmd_ctrl_data = {
407	.cmd0csratio = MT41K256M16HA125E_RATIO,
408	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
409
410	.cmd1csratio = MT41K256M16HA125E_RATIO,
411	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
412
413	.cmd2csratio = MT41K256M16HA125E_RATIO,
414	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
415	};
416
417	static struct emif_regs ddr3_shc_emif_reg_data = {
418	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
419	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
420	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
421	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
422	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
423	.zq_config = MT41K256M16HA125E_ZQ_CFG,
424	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY \|
425	PHY_EN_DYN_PWRDN,
426	};
427
428	void sdram_init(void)
429	{
430	/* Configure the DDR3 RAM */
431	config_ddr(400, &ioregs_evmsk, &ddr3_shc_data,
432	&ddr3_shc_cmd_ctrl_data, &ddr3_shc_emif_reg_data, 0);
433	}
434	#endif
435
436	/*
437	* Basic board specific setup. Pinmux has been handled already.
438	*/
439	int board_init(void)
440	{
441	#if defined(CONFIG_HW_WATCHDOG)
442	hw_watchdog_init();
443	#endif
444	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
445	if (read_eeprom() < 0)
446	puts("EEPROM Content Invalid.\n");
447
448	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
88718be3	449	#if defined(CONFIG_NOR) \|\| defined(CONFIG_MTD_RAW_NAND)
d8ccbe93 HS	450	gpmc_init();
	451	#endif
	452	shc_request_gpio();
	453
	454	return 0;
	455	}
	456
	457	#ifdef CONFIG_BOARD_LATE_INIT
	458	int board_late_init(void)
	459	{
	460	check_button_status();
	461	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	462	if (shc_eeprom_valid)
	463	if (is_valid_ethaddr(header.mac_addr))
fd1e959e	464	eth_env_set_enetaddr("ethaddr", header.mac_addr);
d8ccbe93 HS	465	#endif
	466
	467	return 0;
	468	}
	469	#endif
	470
d8ccbe93	471	#if defined(CONFIG_USB_ETHER) && \
b432b1eb	472	(!defined(CONFIG_SPL_BUILD) \|\| defined(CONFIG_SPL_USB_ETHER))
a36c70a3 HS	473	int board_eth_init(bd_t *bis)
	474	{
	475	return usb_eth_initialize(bis);
d8ccbe93 HS	476	}
	477	#endif
	478
d8ccbe93 HS	479	#ifdef CONFIG_SHOW_BOOT_PROGRESS
	480	static void bosch_check_reset_pin(void)
	481	{
	482	if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) {
	483	printf("Resetting ...\n");
	484	writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
	485	disable_interrupts();
	486	reset_cpu(0);
	487	/NOTREACHED/
	488	}
	489	}
	490
	491	static void hang_bosch(const char *cause, int code)
	492	{
	493	int lv;
	494
	495	gpio_direction_input(RESET_GPIO);
	496
	497	/* Enable reset pin interrupt on falling edge */
	498	writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
	499	writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_FALLINGDETECT);
	500	enable_interrupts();
	501
	502	puts(cause);
	503	for (;;) {
	504	for (lv = 0; lv < code; lv++) {
	505	bosch_check_reset_pin();
	506	leds_set_failure(1);
	507	__udelay(150 * 1000);
	508	leds_set_failure(0);
	509	__udelay(150 * 1000);
	510	}
	511	#if defined(BLINK_CODE)
	512	__udelay(300 * 1000);
	513	#endif
	514	}
	515	}
	516
	517	void show_boot_progress(int val)
	518	{
	519	switch (val) {
	520	case BOOTSTAGE_ID_NEED_RESET:
	521	hang_bosch("need reset", 4);
	522	break;
	523	}
	524	}
d8ccbe93 HS	525
	526	void arch_preboot_os(void)
	527	{
	528	leds_set_finish();
	529	}
d8ccbe93	530	#endif