[u-boot.git] / arch / arm / mach-meson / board-axg.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2016 Beniamino Galvani <[email protected]>
 * (C) Copyright 2018 Neil Armstrong <[email protected]>
 */

#include <common.h>
#include <init.h>
#include <net.h>
#include <asm/arch/boot.h>
#include <asm/arch/eth.h>
#include <asm/arch/axg.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/armv8/mmu.h>
#include <linux/sizes.h>
#include <phy.h>

DECLARE_GLOBAL_DATA_PTR;

int meson_get_boot_device(void)
{
	return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE;
}

/* Configure the reserved memory zones exported by the secure registers
 * into EFI and DTB reserved memory entries.
 */
void meson_init_reserved_memory(void *fdt)
{
	u64 bl31_size, bl31_start;
	u64 bl32_size, bl32_start;
	u32 reg;

	/*
	 * Get ARM Trusted Firmware reserved memory zones in :
	 * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
	 * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
	 * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
	 */
	reg = readl(AXG_AO_SEC_GP_CFG3);

	bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK)
			>> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
	bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;

	bl31_start = readl(AXG_AO_SEC_GP_CFG5);
	bl32_start = readl(AXG_AO_SEC_GP_CFG4);

	/* Add BL31 reserved zone */
	if (bl31_start && bl31_size)
		meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);

	/* Add BL32 reserved zone */
	if (bl32_start && bl32_size)
		meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
}

phys_size_t get_effective_memsize(void)
{
	/* Size is reported in MiB, convert it in bytes */
	return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK)
			>> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M;
}

static struct mm_region axg_mem_map[] = {
	{
		.virt = 0x0UL,
		.phys = 0x0UL,
		.size = 0x80000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
			 PTE_BLOCK_INNER_SHARE
	}, {
		.virt = 0xf0000000UL,
		.phys = 0xf0000000UL,
		.size = 0x10000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
			 PTE_BLOCK_NON_SHARE |
			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
	}, {
		/* List terminator */
		0,
	}
};

struct mm_region *mem_map = axg_mem_map;

/* Configure the Ethernet MAC with the requested interface mode
 * with some optional flags.
 */
void meson_eth_init(phy_interface_t mode, unsigned int flags)
{
	switch (mode) {
	case PHY_INTERFACE_MODE_RGMII:
	case PHY_INTERFACE_MODE_RGMII_ID:
	case PHY_INTERFACE_MODE_RGMII_RXID:
	case PHY_INTERFACE_MODE_RGMII_TXID:
		/* Set RGMII mode */
		setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
			     AXG_ETH_REG_0_TX_PHASE(1) |
			     AXG_ETH_REG_0_TX_RATIO(4) |
			     AXG_ETH_REG_0_PHY_CLK_EN |
			     AXG_ETH_REG_0_CLK_EN);
		break;

	case PHY_INTERFACE_MODE_RMII:
		/* Set RMII mode */
		out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
					AXG_ETH_REG_0_INVERT_RMII_CLK |
					AXG_ETH_REG_0_CLK_EN);
		break;

	default:
		printf("Invalid Ethernet interface mode\n");
		return;
	}

	/* Enable power gate */
	clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK);
}
Commit	Line	Data
485bba39 NA	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* (C) Copyright 2016 Beniamino Galvani <[email protected]>
	4	* (C) Copyright 2018 Neil Armstrong <[email protected]>
	5	*/
	6
	7	#include <common.h>
9b4a205f	8	#include <init.h>
90526e9f	9	#include <net.h>
d96a782d	10	#include <asm/arch/boot.h>
485bba39 NA	11	#include <asm/arch/eth.h>
	12	#include <asm/arch/axg.h>
	13	#include <asm/arch/mem.h>
	14	#include <asm/io.h>
	15	#include <asm/armv8/mmu.h>
	16	#include <linux/sizes.h>
	17	#include <phy.h>
	18
	19	DECLARE_GLOBAL_DATA_PTR;
	20
d96a782d NA	21	int meson_get_boot_device(void)
	22	{
	23	return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE;
	24	}
	25
485bba39 NA	26	/* Configure the reserved memory zones exported by the secure registers
	27	* into EFI and DTB reserved memory entries.
	28	*/
	29	void meson_init_reserved_memory(void *fdt)
	30	{
	31	u64 bl31_size, bl31_start;
	32	u64 bl32_size, bl32_start;
	33	u32 reg;
	34
	35	/*
	36	* Get ARM Trusted Firmware reserved memory zones in :
	37	* - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
	38	* - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
	39	* - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
	40	*/
	41	reg = readl(AXG_AO_SEC_GP_CFG3);
	42
	43	bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK)
	44	>> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
	45	bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
	46
	47	bl31_start = readl(AXG_AO_SEC_GP_CFG5);
	48	bl32_start = readl(AXG_AO_SEC_GP_CFG4);
	49
	50	/* Add BL31 reserved zone */
	51	if (bl31_start && bl31_size)
	52	meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
	53
	54	/* Add BL32 reserved zone */
	55	if (bl32_start && bl32_size)
	56	meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
	57	}
	58
	59	phys_size_t get_effective_memsize(void)
	60	{
	61	/* Size is reported in MiB, convert it in bytes */
	62	return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK)
	63	>> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M;
	64	}
	65
	66	static struct mm_region axg_mem_map[] = {
	67	{
	68	.virt = 0x0UL,
	69	.phys = 0x0UL,
	70	.size = 0x80000000UL,
	71	.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) \|
	72	PTE_BLOCK_INNER_SHARE
	73	}, {
	74	.virt = 0xf0000000UL,
	75	.phys = 0xf0000000UL,
	76	.size = 0x10000000UL,
	77	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	78	PTE_BLOCK_NON_SHARE \|
	79	PTE_BLOCK_PXN \| PTE_BLOCK_UXN
	80	}, {
	81	/* List terminator */
	82	0,
	83	}
	84	};
	85
	86	struct mm_region *mem_map = axg_mem_map;
	87
	88	/* Configure the Ethernet MAC with the requested interface mode
	89	* with some optional flags.
90	*/
91	void meson_eth_init(phy_interface_t mode, unsigned int flags)
92	{
93	switch (mode) {
94	case PHY_INTERFACE_MODE_RGMII:
95	case PHY_INTERFACE_MODE_RGMII_ID:
96	case PHY_INTERFACE_MODE_RGMII_RXID:
97	case PHY_INTERFACE_MODE_RGMII_TXID:
98	/* Set RGMII mode */
99	setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII \|
100	AXG_ETH_REG_0_TX_PHASE(1) \|
101	AXG_ETH_REG_0_TX_RATIO(4) \|
102	AXG_ETH_REG_0_PHY_CLK_EN \|
103	AXG_ETH_REG_0_CLK_EN);
104	break;
105
106	case PHY_INTERFACE_MODE_RMII:
107	/* Set RMII mode */
108	out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII \|
109	AXG_ETH_REG_0_INVERT_RMII_CLK \|
110	AXG_ETH_REG_0_CLK_EN);
111	break;
112
113	default:
114	printf("Invalid Ethernet interface mode\n");
115	return;
116	}
117
118	/* Enable power gate */
119	clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK);
120	}