[u-boot.git] / board / ivm / ivm.c

/*
 * (C) Copyright 2000, 2001
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 * Ulrich Lutz, Speech Design GmbH, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc8xx.h>
#include <commproc.h>

#ifdef CONFIG_STATUS_LED
# include <status_led.h>
#endif

/* ------------------------------------------------------------------------- */

static long int dram_size (long int, long int *, long int);

/* ------------------------------------------------------------------------- */

#define	_NOT_USED_	0xFFFFFFFF

/*
 * 50 MHz SHARC access using UPM A
 */
const uint sharc_table[] =
{
	/*
	 * Single Read. (Offset 0 in UPM RAM)
	 */
	0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
	0xFFFFEC05, /* last */
		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Burst Read. (Offset 8 in UPM RAM)
	 */
	/* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Single Write. (Offset 18 in UPM RAM)
	 */
	0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
	0xFFFFEC05, /* last */
		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Burst Write. (Offset 20 in UPM RAM)
	 */
	/* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Refresh  (Offset 30 in UPM RAM)
	 */
	/* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Exception. (Offset 3c in UPM RAM)
	 */
	0x7FFFFC07, /* last */
		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
};


/*
 * 50 MHz SDRAM access using UPM B
 */
const uint sdram_table[] =
{
	/*
	 * Single Read. (Offset 0 in UPM RAM)
	 */
	0x0E26FC04, 0x11ADFC04, 0xEFBBBC00, 0x1FF77C45,	/* last */
	_NOT_USED_,
	/*
	 * SDRAM Initialization (offset 5 in UPM RAM)
	 *
	 * This is no UPM entry point. The following definition uses
	 * the remaining space to establish an initialization
	 * sequence, which is executed by a RUN command.
	 *
	 */
		    0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
	/*
	 * Burst Read. (Offset 8 in UPM RAM)
	 */
	0x0E26FC04, 0x10ADFC04, 0xF0AFFC00, 0xF0AFFC00,
	0xF1AFFC00, 0xEFBBBC00, 0x1FF77C45, /* last */
					    _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Single Write. (Offset 18 in UPM RAM)
	 */
	0x1F27FC04, 0xEEAEBC04, 0x01B93C00, 0x1FF77C45, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Burst Write. (Offset 20 in UPM RAM)
	 */
	0x0E26BC00, 0x10AD7C00, 0xF0AFFC00, 0xF0AFFC00,
	0xE1BBBC04, 0x1FF77C45, /* last */
				_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Refresh  (Offset 30 in UPM RAM)
	 */
	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC84,
	0xFFFFFC05, /* last */
		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Exception. (Offset 3c in UPM RAM)
	 */
	0x7FFFFC07, /* last */
		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
};

/* ------------------------------------------------------------------------- */


/*
 * Check Board Identity:
 *
 */

int checkboard (void)
{
#ifdef CONFIG_IVMS8
	puts ("Board: IVMS8\n");
#endif
#ifdef CONFIG_IVML24
	puts ("Board: IVM-L8/24\n");
#endif
	return (0);
}

/* ------------------------------------------------------------------------- */

long int
initdram (int board_type)
{
    volatile immap_t     *immr  = (immap_t *)CFG_IMMR;
    volatile memctl8xx_t *memctl = &immr->im_memctl;
    long int size_b0;

    /* enable SDRAM clock ("switch on" SDRAM) */
    immr->im_cpm.cp_pbpar &= ~(CFG_PB_SDRAM_CLKE);	/* GPIO */
    immr->im_cpm.cp_pbodr &= ~(CFG_PB_SDRAM_CLKE);	/* active output */
    immr->im_cpm.cp_pbdir |=   CFG_PB_SDRAM_CLKE ;	/* output */
    immr->im_cpm.cp_pbdat |=   CFG_PB_SDRAM_CLKE ;	/* assert SDRAM CLKE */
    udelay(1);

    /*
     * Map controller bank 1 for ELIC SACCO
     */
    memctl->memc_or1 = CFG_OR1;
    memctl->memc_br1 = CFG_BR1;

    /*
     * Map controller bank 2 for ELIC EPIC
     */
    memctl->memc_or2 = CFG_OR2;
    memctl->memc_br2 = CFG_BR2;

    /*
     * Configure UPMA for SHARC
     */
    upmconfig(UPMA, (uint *)sharc_table, sizeof(sharc_table)/sizeof(uint));

#if defined(CONFIG_IVML24)
    /*
     * Map controller bank 4 for HDLC Address space
     */
    memctl->memc_or4 = CFG_OR4;
    memctl->memc_br4 = CFG_BR4;
#endif

    /*
     * Map controller bank 5 for SHARC
     */
    memctl->memc_or5 = CFG_OR5;
    memctl->memc_br5 = CFG_BR5;

    memctl->memc_mamr = 0x00001000;

    /*
     * Configure UPMB for SDRAM
     */
    upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));

    memctl->memc_mptpr = CFG_MPTPR_1BK_8K;

    memctl->memc_mar = 0x00000088;

    /*
     * Map controller bank 3 to the SDRAM bank at preliminary address.
     */
    memctl->memc_or3 = CFG_OR3_PRELIM;
    memctl->memc_br3 = CFG_BR3_PRELIM;

    memctl->memc_mbmr = CFG_MBMR_8COL;	/* refresh not enabled yet */

    udelay(200);
    memctl->memc_mcr = 0x80806105;	/* precharge */
    udelay(1);
    memctl->memc_mcr = 0x80806106;	/* load mode register */
    udelay(1);
    memctl->memc_mcr = 0x80806130;	/* autorefresh */
    udelay(1);
    memctl->memc_mcr = 0x80806130;	/* autorefresh */
    udelay(1);
    memctl->memc_mcr = 0x80806130;	/* autorefresh */
    udelay(1);
    memctl->memc_mcr = 0x80806130;	/* autorefresh */
    udelay(1);
    memctl->memc_mcr = 0x80806130;	/* autorefresh */
    udelay(1);
    memctl->memc_mcr = 0x80806130;	/* autorefresh */
    udelay(1);
    memctl->memc_mcr = 0x80806130;	/* autorefresh */
    udelay(1);
    memctl->memc_mcr = 0x80806130;	/* autorefresh */

    memctl->memc_mbmr |= MAMR_PTBE;	/* refresh enabled */

    /*
     * Check Bank 0 Memory Size for re-configuration
     */
    size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);

    memctl->memc_mbmr = CFG_MBMR_8COL | MAMR_PTBE;

    return (size_b0);
}

/* ------------------------------------------------------------------------- */

/*
 * Check memory range for valid RAM. A simple memory test determines
 * the actually available RAM size between addresses `base' and
 * `base + maxsize'. Some (not all) hardware errors are detected:
 * - short between address lines
 * - short between data lines
 */

static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
    volatile immap_t     *immr  = (immap_t *)CFG_IMMR;
    volatile memctl8xx_t *memctl = &immr->im_memctl;
    volatile long int	 *addr;
    ulong		  cnt, val;
    ulong		  save[32];	/* to make test non-destructive */
    unsigned char	  i = 0;

    memctl->memc_mbmr = mamr_value;

    for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
	addr = base + cnt;	/* pointer arith! */

	save[i++] = *addr;
	*addr = ~cnt;
    }

    /* write 0 to base address */
    addr = base;
    save[i] = *addr;
    *addr = 0;

    /* check at base address */
    if ((val = *addr) != 0) {
	*addr = save[i];
	return (0);
    }

    for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
	addr = base + cnt;	/* pointer arith! */

	val = *addr;
	*addr = save[--i];

	if (val != (~cnt)) {
	    return (cnt * sizeof(long));
	}
    }
    return (maxsize);
}

/* ------------------------------------------------------------------------- */

void	reset_phy(void)
{
	immap_t *immr = (immap_t *)CFG_IMMR;

	/* De-assert Ethernet Powerdown */
	immr->im_cpm.cp_pbpar &= ~(CFG_PB_ETH_POWERDOWN); /* GPIO */
	immr->im_cpm.cp_pbodr &= ~(CFG_PB_ETH_POWERDOWN); /* active output */
	immr->im_cpm.cp_pbdir |=   CFG_PB_ETH_POWERDOWN ; /* output */
	immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
	udelay(1000);

	/*
	 * RESET is implemented by a positive pulse of at least 1 us
	 * at the reset pin.
	 *
	 * Configure RESET pins for NS DP83843 PHY, and RESET chip.
	 *
	 * Note: The RESET pin is high active, but there is an
	 *	 inverter on the SPD823TS board...
	 */
	immr->im_ioport.iop_pcpar &= ~(CFG_PC_ETH_RESET);
	immr->im_ioport.iop_pcdir |=   CFG_PC_ETH_RESET;
	/* assert RESET signal of PHY */
	immr->im_ioport.iop_pcdat &= ~(CFG_PC_ETH_RESET);
	udelay (10);
	/* de-assert RESET signal of PHY */
	immr->im_ioport.iop_pcdat |=   CFG_PC_ETH_RESET;
	udelay (10);
}

/* ------------------------------------------------------------------------- */

void show_boot_progress (int status)
{
#if defined(CONFIG_STATUS_LED)
# if defined(STATUS_LED_YELLOW)
	status_led_set (STATUS_LED_YELLOW,
			(status < 0) ? STATUS_LED_ON : STATUS_LED_OFF);
# endif /* STATUS_LED_YELLOW */
# if defined(STATUS_LED_BOOT)
	if (status == 6)
	  status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
# endif /* STATUS_LED_BOOT */
#endif /* CONFIG_STATUS_LED */
}

/* ------------------------------------------------------------------------- */

void ide_set_reset(int on)
{
	volatile immap_t *immr = (immap_t *)CFG_IMMR;

	/*
	 * Configure PC for IDE Reset Pin
	 */
	if (on) {		/* assert RESET */
		immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
	} else {		/* release RESET */
		immr->im_ioport.iop_pcdat |=   CFG_PC_IDE_RESET;
	}

	/* program port pin as GPIO output */
	immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
	immr->im_ioport.iop_pcso  &= ~(CFG_PC_IDE_RESET);
	immr->im_ioport.iop_pcdir |=   CFG_PC_IDE_RESET;
}

/* ------------------------------------------------------------------------- */
Commit	Line	Data
16f21704 WD	1	/*
	2	* (C) Copyright 2000, 2001
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	* Ulrich Lutz, Speech Design GmbH, [email protected].
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <common.h>
	26	#include <mpc8xx.h>
	27	#include <commproc.h>
	28
	29	#ifdef CONFIG_STATUS_LED
	30	# include <status_led.h>
	31	#endif
	32
	33	/* ------------------------------------------------------------------------- */
	34
	35	static long int dram_size (long int, long int *, long int);
	36
	37	/* ------------------------------------------------------------------------- */
	38
	39	#define _NOT_USED_ 0xFFFFFFFF
	40
	41	/*
	42	* 50 MHz SHARC access using UPM A
	43	*/
	44	const uint sharc_table[] =
	45	{
	46	/*
	47	* Single Read. (Offset 0 in UPM RAM)
	48	*/
	49	0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
	50	0xFFFFEC05, /* last */
8bde7f77	51	_NOT_USED_, _NOT_USED_, _NOT_USED_,
16f21704 WD	52	/*
	53	* Burst Read. (Offset 8 in UPM RAM)
	54	*/
	55	/* last */
	56	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	57	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	58	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	59	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	60	/*
	61	* Single Write. (Offset 18 in UPM RAM)
	62	*/
	63	0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
	64	0xFFFFEC05, /* last */
8bde7f77	65	_NOT_USED_, _NOT_USED_, _NOT_USED_,
16f21704 WD	66	/*
	67	* Burst Write. (Offset 20 in UPM RAM)
	68	*/
	69	/* last */
	70	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	71	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	72	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	73	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	74	/*
	75	* Refresh (Offset 30 in UPM RAM)
	76	*/
	77	/* last */
	78	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	79	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	80	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	81	/*
	82	* Exception. (Offset 3c in UPM RAM)
	83	*/
	84	0x7FFFFC07, /* last */
	85	_NOT_USED_, _NOT_USED_, _NOT_USED_,
	86	};
	87
	88
	89	/*
	90	* 50 MHz SDRAM access using UPM B
	91	*/
	92	const uint sdram_table[] =
	93	{
	94	/*
	95	* Single Read. (Offset 0 in UPM RAM)
	96	*/
	97	0x0E26FC04, 0x11ADFC04, 0xEFBBBC00, 0x1FF77C45, /* last */
	98	_NOT_USED_,
	99	/*
	100	* SDRAM Initialization (offset 5 in UPM RAM)
	101	*
8bde7f77 WD	102	* This is no UPM entry point. The following definition uses
	103	* the remaining space to establish an initialization
	104	* sequence, which is executed by a RUN command.
16f21704 WD	105	*
	106	*/
	107	0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
	108	/*
	109	* Burst Read. (Offset 8 in UPM RAM)
	110	*/
	111	0x0E26FC04, 0x10ADFC04, 0xF0AFFC00, 0xF0AFFC00,
	112	0xF1AFFC00, 0xEFBBBC00, 0x1FF77C45, /* last */
	113	_NOT_USED_,
	114	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	115	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	116	/*
	117	* Single Write. (Offset 18 in UPM RAM)
	118	*/
	119	0x1F27FC04, 0xEEAEBC04, 0x01B93C00, 0x1FF77C45, /* last */
	120	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	121	/*
	122	* Burst Write. (Offset 20 in UPM RAM)
	123	*/
	124	0x0E26BC00, 0x10AD7C00, 0xF0AFFC00, 0xF0AFFC00,
	125	0xE1BBBC04, 0x1FF77C45, /* last */
	126	_NOT_USED_, _NOT_USED_,
	127	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	128	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	129	/*
	130	* Refresh (Offset 30 in UPM RAM)
	131	*/
	132	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC84,
	133	0xFFFFFC05, /* last */
	134	_NOT_USED_, _NOT_USED_, _NOT_USED_,
	135	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	136	/*
	137	* Exception. (Offset 3c in UPM RAM)
	138	*/
	139	0x7FFFFC07, /* last */
	140	_NOT_USED_, _NOT_USED_, _NOT_USED_,
	141	};
	142
	143	/* ------------------------------------------------------------------------- */
	144
	145
	146	/*
	147	* Check Board Identity:
	148	*
	149	*/
	150
	151	int checkboard (void)
	152	{
	153	#ifdef CONFIG_IVMS8
	154	puts ("Board: IVMS8\n");
	155	#endif
	156	#ifdef CONFIG_IVML24
	157	puts ("Board: IVM-L8/24\n");
	158	#endif
	159	return (0);
	160	}
	161
	162	/* ------------------------------------------------------------------------- */
	163
	164	long int
	165	initdram (int board_type)
	166	{
	167	volatile immap_t immr = (immap_t )CFG_IMMR;
	168	volatile memctl8xx_t *memctl = &immr->im_memctl;
169	long int size_b0;
170
171	/* enable SDRAM clock ("switch on" SDRAM) */
172	immr->im_cpm.cp_pbpar &= ~(CFG_PB_SDRAM_CLKE); /* GPIO */
173	immr->im_cpm.cp_pbodr &= ~(CFG_PB_SDRAM_CLKE); /* active output */
174	immr->im_cpm.cp_pbdir \|= CFG_PB_SDRAM_CLKE ; /* output */
175	immr->im_cpm.cp_pbdat \|= CFG_PB_SDRAM_CLKE ; /* assert SDRAM CLKE */
176	udelay(1);
177
178	/*
179	* Map controller bank 1 for ELIC SACCO
180	*/
181	memctl->memc_or1 = CFG_OR1;
182	memctl->memc_br1 = CFG_BR1;
183
184	/*
185	* Map controller bank 2 for ELIC EPIC
186	*/
187	memctl->memc_or2 = CFG_OR2;
188	memctl->memc_br2 = CFG_BR2;
189
190	/*
191	* Configure UPMA for SHARC
192	*/
193	upmconfig(UPMA, (uint *)sharc_table, sizeof(sharc_table)/sizeof(uint));
194
195	#if defined(CONFIG_IVML24)
196	/*
197	* Map controller bank 4 for HDLC Address space
198	*/
199	memctl->memc_or4 = CFG_OR4;
200	memctl->memc_br4 = CFG_BR4;
201	#endif
202
203	/*
204	* Map controller bank 5 for SHARC
205	*/
206	memctl->memc_or5 = CFG_OR5;
207	memctl->memc_br5 = CFG_BR5;
208
209	memctl->memc_mamr = 0x00001000;
210
211	/*
212	* Configure UPMB for SDRAM
213	*/
214	upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
215
216	memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
217
218	memctl->memc_mar = 0x00000088;
219
220	/*
221	* Map controller bank 3 to the SDRAM bank at preliminary address.
222	*/
223	memctl->memc_or3 = CFG_OR3_PRELIM;
224	memctl->memc_br3 = CFG_BR3_PRELIM;
225
226	memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
227
228	udelay(200);
229	memctl->memc_mcr = 0x80806105; /* precharge */
230	udelay(1);
231	memctl->memc_mcr = 0x80806106; /* load mode register */
232	udelay(1);
233	memctl->memc_mcr = 0x80806130; /* autorefresh */
234	udelay(1);
235	memctl->memc_mcr = 0x80806130; /* autorefresh */
236	udelay(1);
237	memctl->memc_mcr = 0x80806130; /* autorefresh */
238	udelay(1);
239	memctl->memc_mcr = 0x80806130; /* autorefresh */
240	udelay(1);
241	memctl->memc_mcr = 0x80806130; /* autorefresh */
242	udelay(1);
243	memctl->memc_mcr = 0x80806130; /* autorefresh */
244	udelay(1);
245	memctl->memc_mcr = 0x80806130; /* autorefresh */
246	udelay(1);
247	memctl->memc_mcr = 0x80806130; /* autorefresh */
248
249	memctl->memc_mbmr \|= MAMR_PTBE; /* refresh enabled */
250
251	/*
252	* Check Bank 0 Memory Size for re-configuration
253	*/
254	size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
255
256	memctl->memc_mbmr = CFG_MBMR_8COL \| MAMR_PTBE;
257
258	return (size_b0);
259	}
260
261	/* ------------------------------------------------------------------------- */
262
263	/*
264	* Check memory range for valid RAM. A simple memory test determines
265	* the actually available RAM size between addresses `base' and
266	* `base + maxsize'. Some (not all) hardware errors are detected:
267	* - short between address lines
268	* - short between data lines
269	*/
270
271	static long int dram_size (long int mamr_value, long int *base, long int maxsize)
272	{
273	volatile immap_t immr = (immap_t )CFG_IMMR;
274	volatile memctl8xx_t *memctl = &immr->im_memctl;
275	volatile long int *addr;
276	ulong cnt, val;
277	ulong save[32]; /* to make test non-destructive */
278	unsigned char i = 0;
279
280	memctl->memc_mbmr = mamr_value;
281
282	for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
283	addr = base + cnt; /* pointer arith! */
284
285	save[i++] = *addr;
286	*addr = ~cnt;
287	}
288
289	/* write 0 to base address */
290	addr = base;
291	save[i] = *addr;
292	*addr = 0;
293
294	/* check at base address */
295	if ((val = *addr) != 0) {
296	*addr = save[i];
297	return (0);
298	}
299
300	for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
301	addr = base + cnt; /* pointer arith! */
302
303	val = *addr;
304	*addr = save[--i];
305
306	if (val != (~cnt)) {
307	return (cnt * sizeof(long));
308	}
309	}
310	return (maxsize);
311	}
312
313	/* ------------------------------------------------------------------------- */
314
315	void reset_phy(void)
316	{
317	immap_t immr = (immap_t )CFG_IMMR;
318
319	/* De-assert Ethernet Powerdown */
320	immr->im_cpm.cp_pbpar &= ~(CFG_PB_ETH_POWERDOWN); /* GPIO */
321	immr->im_cpm.cp_pbodr &= ~(CFG_PB_ETH_POWERDOWN); /* active output */
322	immr->im_cpm.cp_pbdir \|= CFG_PB_ETH_POWERDOWN ; /* output */
323	immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
324	udelay(1000);
325
326	/*
8bde7f77 WD	327	* RESET is implemented by a positive pulse of at least 1 us
8bde7f77 WD	328	* at the reset pin.
16f21704 WD	329	*
	330	* Configure RESET pins for NS DP83843 PHY, and RESET chip.
	331	*
	332	* Note: The RESET pin is high active, but there is an
	333	* inverter on the SPD823TS board...
	334	*/
	335	immr->im_ioport.iop_pcpar &= ~(CFG_PC_ETH_RESET);
	336	immr->im_ioport.iop_pcdir \|= CFG_PC_ETH_RESET;
	337	/* assert RESET signal of PHY */
	338	immr->im_ioport.iop_pcdat &= ~(CFG_PC_ETH_RESET);
	339	udelay (10);
	340	/* de-assert RESET signal of PHY */
	341	immr->im_ioport.iop_pcdat \|= CFG_PC_ETH_RESET;
	342	udelay (10);
	343	}
	344
	345	/* ------------------------------------------------------------------------- */
	346
	347	void show_boot_progress (int status)
	348	{
	349	#if defined(CONFIG_STATUS_LED)
	350	# if defined(STATUS_LED_YELLOW)
	351	status_led_set (STATUS_LED_YELLOW,
	352	(status < 0) ? STATUS_LED_ON : STATUS_LED_OFF);
	353	# endif /* STATUS_LED_YELLOW */
	354	# if defined(STATUS_LED_BOOT)
	355	if (status == 6)
	356	status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
	357	# endif /* STATUS_LED_BOOT */
	358	#endif /* CONFIG_STATUS_LED */
	359	}
	360
	361	/* ------------------------------------------------------------------------- */
	362
	363	void ide_set_reset(int on)
	364	{
	365	volatile immap_t immr = (immap_t )CFG_IMMR;
	366
	367	/*
	368	* Configure PC for IDE Reset Pin
	369	*/
	370	if (on) { /* assert RESET */
	371	immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
	372	} else { /* release RESET */
	373	immr->im_ioport.iop_pcdat \|= CFG_PC_IDE_RESET;
	374	}
	375
	376	/* program port pin as GPIO output */
	377	immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
	378	immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET);
	379	immr->im_ioport.iop_pcdir \|= CFG_PC_IDE_RESET;
	380	}
	381
	382	/* ------------------------------------------------------------------------- */