[u-boot.git] / drivers / spi / cf_spi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 *
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
 * TsiChung Liew ([email protected])
 *
 * Support for DM and DT, non-DM code removed.
 * Copyright (C) 2018 Angelo Dureghello <[email protected]>
 *
 * TODO: fsl_dspi.c should work as a driver for the DSPI module.
 */

#include <common.h>
#include <dm.h>
#include <log.h>
#include <dm/platform_data/spi_coldfire.h>
#include <spi.h>
#include <malloc.h>
#include <asm/coldfire/dspi.h>
#include <asm/io.h>

struct coldfire_spi_priv {
	struct dspi *regs;
	uint baudrate;
	int mode;
	int charbit;
};

DECLARE_GLOBAL_DATA_PTR;

#ifndef CONFIG_SPI_IDLE_VAL
#if defined(CONFIG_SPI_MMC)
#define CONFIG_SPI_IDLE_VAL	0xFFFF
#else
#define CONFIG_SPI_IDLE_VAL	0x0
#endif
#endif

/*
 * DSPI specific mode
 *
 * bit 31 - 28: Transfer size 3 to 16 bits
 *     27 - 26: PCS to SCK delay prescaler
 *     25 - 24: After SCK delay prescaler
 *     23 - 22: Delay after transfer prescaler
 *     21     : Allow overwrite for bit 31-22 and bit 20-8
 *     20     : Double baud rate
 *     19 - 16: PCS to SCK delay scaler
 *     15 - 12: After SCK delay scaler
 *     11 -  8: Delay after transfer scaler
 *      7 -  0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
 */
#define SPI_MODE_MOD			0x00200000
#define SPI_MODE_DBLRATE		0x00100000

#define SPI_MODE_XFER_SZ_MASK		0xf0000000
#define SPI_MODE_DLY_PRE_MASK		0x0fc00000
#define SPI_MODE_DLY_SCA_MASK		0x000fff00

#define MCF_FRM_SZ_16BIT		DSPI_CTAR_TRSZ(0xf)
#define MCF_DSPI_SPEED_BESTMATCH	0x7FFFFFFF
#define MCF_DSPI_MAX_CTAR_REGS		8

/* Default values */
#define MCF_DSPI_DEFAULT_SCK_FREQ	10000000
#define MCF_DSPI_DEFAULT_MAX_CS		4
#define MCF_DSPI_DEFAULT_MODE		0

#define MCF_DSPI_DEFAULT_CTAR		(DSPI_CTAR_TRSZ(7) | \
					DSPI_CTAR_PCSSCK_1CLK | \
					DSPI_CTAR_PASC(0) | \
					DSPI_CTAR_PDT(0) | \
					DSPI_CTAR_CSSCK(0) | \
					DSPI_CTAR_ASC(0) | \
					DSPI_CTAR_DT(1) | \
					DSPI_CTAR_BR(6))

#define MCF_CTAR_MODE_MASK		(MCF_FRM_SZ_16BIT | \
					DSPI_CTAR_PCSSCK(3) | \
					DSPI_CTAR_PASC_7CLK | \
					DSPI_CTAR_PDT(3) | \
					DSPI_CTAR_CSSCK(0x0f) | \
					DSPI_CTAR_ASC(0x0f) | \
					DSPI_CTAR_DT(0x0f))

#define setup_ctrl(ctrl, cs)	((ctrl & 0xFF000000) | ((1 << cs) << 16))

static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
			    u32 ctrl, u16 data)
{
	/*
	 * Need to check fifo level here
	 */
	while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000)
		;

	writel(ctrl | data, &cfspi->regs->tfr);
}

static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
{

	while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
		;

	return readw(&cfspi->regs->rfr);
}

static int coldfire_spi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	struct dspi *dspi = cfspi->regs;
	struct dm_spi_slave_plat *slave_plat =
		dev_get_parent_plat(dev);

	if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
		return -1;

	/* Clear FIFO and resume transfer */
	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);

	dspi_chip_select(slave_plat->cs);

	return 0;
}

static int coldfire_spi_release_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	struct dspi *dspi = cfspi->regs;
	struct dm_spi_slave_plat *slave_plat =
		dev_get_parent_plat(dev);

	/* Clear FIFO */
	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);

	dspi_chip_unselect(slave_plat->cs);

	return 0;
}

static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
			     const void *dout, void *din,
			     unsigned long flags)
{
	struct udevice *bus = dev_get_parent(dev);
	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
	u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
	u8 *spi_rd = NULL, *spi_wr = NULL;
	static u32 ctrl;
	uint len = bitlen >> 3;

	if (cfspi->charbit == 16) {
		bitlen >>= 1;
		spi_wr16 = (u16 *)dout;
		spi_rd16 = (u16 *)din;
	} else {
		spi_wr = (u8 *)dout;
		spi_rd = (u8 *)din;
	}

	if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
		ctrl |= DSPI_TFR_CONT;

	ctrl = setup_ctrl(ctrl, slave_plat->cs);

	if (len > 1) {
		int tmp_len = len - 1;

		while (tmp_len--) {
			if (dout) {
				if (cfspi->charbit == 16)
					cfspi_tx(cfspi, ctrl, *spi_wr16++);
				else
					cfspi_tx(cfspi, ctrl, *spi_wr++);
				cfspi_rx(cfspi);
			}

			if (din) {
				cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
				if (cfspi->charbit == 16)
					*spi_rd16++ = cfspi_rx(cfspi);
				else
					*spi_rd++ = cfspi_rx(cfspi);
			}
		}

		len = 1;	/* remaining byte */
	}

	if (flags & SPI_XFER_END)
		ctrl &= ~DSPI_TFR_CONT;

	if (len) {
		if (dout) {
			if (cfspi->charbit == 16)
				cfspi_tx(cfspi, ctrl, *spi_wr16);
			else
				cfspi_tx(cfspi, ctrl, *spi_wr);
			cfspi_rx(cfspi);
		}

		if (din) {
			cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
			if (cfspi->charbit == 16)
				*spi_rd16 = cfspi_rx(cfspi);
			else
				*spi_rd = cfspi_rx(cfspi);
		}
	} else {
		/* dummy read */
		cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
		cfspi_rx(cfspi);
	}

	return 0;
}

static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
{
	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	struct dspi *dspi = cfspi->regs;
	int prescaler[] = { 2, 3, 5, 7 };
	int scaler[] = {
		2, 4, 6, 8,
		16, 32, 64, 128,
		256, 512, 1024, 2048,
		4096, 8192, 16384, 32768
	};
	int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
	int best_i, best_j, bestmatch = MCF_DSPI_SPEED_BESTMATCH, baud_speed;
	u32 bus_setup;

	cfspi->baudrate = max_hz;

	/* Read current setup */
	bus_setup = readl(&dspi->ctar[dev_seq(bus)]);

	tmp = (prescaler[3] * scaler[15]);
	/* Maximum and minimum baudrate it can handle */
	if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||
	    (cfspi->baudrate < (gd->bus_clk / tmp))) {
		printf("Exceed baudrate limitation: Max %d - Min %d\n",
		       (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
		return -1;
	}

	/* Activate Double Baud when it exceed 1/4 the bus clk */
	if ((bus_setup & DSPI_CTAR_DBR) ||
	    (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
		bus_setup |= DSPI_CTAR_DBR;
		dbr = 1;
	}

	/* Overwrite default value set in platform configuration file */
	if (cfspi->mode & SPI_MODE_MOD) {
		/*
		 * Check to see if it is enabled by default in platform
		 * config, or manual setting passed by mode parameter
		 */
		if (cfspi->mode & SPI_MODE_DBLRATE) {
			bus_setup |= DSPI_CTAR_DBR;
			dbr = 1;
		}
	}

	pbrcnt = sizeof(prescaler) / sizeof(int);
	brcnt = sizeof(scaler) / sizeof(int);

	/* baudrate calculation - to closer value, may not be exact match */
	for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) {
		baud_speed = gd->bus_clk / prescaler[i];
		for (j = 0; j < brcnt; j++) {
			tmp = (baud_speed / scaler[j]) * (1 + dbr);

			if (tmp > cfspi->baudrate)
				diff = tmp - cfspi->baudrate;
			else
				diff = cfspi->baudrate - tmp;

			if (diff < bestmatch) {
				bestmatch = diff;
				best_i = i;
				best_j = j;
			}
		}
	}

	bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f));
	bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
	writel(bus_setup, &dspi->ctar[dev_seq(bus)]);

	return 0;
}

static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
{
	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	struct dspi *dspi = cfspi->regs;
	u32 bus_setup = 0;

	cfspi->mode = mode;

	if (cfspi->mode & SPI_CPOL)
		bus_setup |= DSPI_CTAR_CPOL;
	if (cfspi->mode & SPI_CPHA)
		bus_setup |= DSPI_CTAR_CPHA;
	if (cfspi->mode & SPI_LSB_FIRST)
		bus_setup |= DSPI_CTAR_LSBFE;

	/* Overwrite default value set in platform configuration file */
	if (cfspi->mode & SPI_MODE_MOD) {
		if ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) == 0)
			bus_setup |=
			    readl(&dspi->ctar[dev_seq(bus)]) & MCF_FRM_SZ_16BIT;
		else
			bus_setup |=
			    ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) >> 1);

		/* PSCSCK, PASC, PDT */
		bus_setup |= (cfspi->mode & SPI_MODE_DLY_PRE_MASK) >> 4;
		/* CSSCK, ASC, DT */
		bus_setup |= (cfspi->mode & SPI_MODE_DLY_SCA_MASK) >> 4;
	} else {
		bus_setup |=
			(readl(&dspi->ctar[dev_seq(bus)]) & MCF_CTAR_MODE_MASK);
	}

	cfspi->charbit =
		((readl(&dspi->ctar[dev_seq(bus)]) & MCF_FRM_SZ_16BIT) ==
			MCF_FRM_SZ_16BIT) ? 16 : 8;

	setbits_be32(&dspi->ctar[dev_seq(bus)], bus_setup);

	return 0;
}

static int coldfire_spi_probe(struct udevice *bus)
{
	struct coldfire_spi_plat *plat = dev_get_plat(bus);
	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	struct dspi *dspi = cfspi->regs;
	int i;

	cfspi->regs = (struct dspi *)plat->regs_addr;

	cfspi->baudrate = plat->speed_hz;
	cfspi->mode = plat->mode;

	for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {
		unsigned int ctar = 0;

		if (plat->ctar[i][0] == 0)
			break;

		ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |
			DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |
			DSPI_CTAR_PASC(plat->ctar[i][2]) |
			DSPI_CTAR_PDT(plat->ctar[i][3]) |
			DSPI_CTAR_CSSCK(plat->ctar[i][4]) |
			DSPI_CTAR_ASC(plat->ctar[i][5]) |
			DSPI_CTAR_DT(plat->ctar[i][6]) |
			DSPI_CTAR_BR(plat->ctar[i][7]);

		writel(ctar, &cfspi->regs->ctar[i]);
	}

	/* Default CTARs */
	for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
		writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);

	dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
	    DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
	    DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
	    DSPI_MCR_CRXF | DSPI_MCR_CTXF;

	return 0;
}

#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static int coldfire_dspi_of_to_plat(struct udevice *bus)
{
	fdt_addr_t addr;
	struct coldfire_spi_plat *plat = bus->plat;
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(bus);
	int *ctar, len;

	addr = dev_read_addr(bus);
	if (addr == FDT_ADDR_T_NONE)
		return -ENOMEM;

	plat->regs_addr = addr;

	plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
				      MCF_DSPI_DEFAULT_MAX_CS);

	plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
					MCF_DSPI_DEFAULT_SCK_FREQ);

	plat->mode = fdtdec_get_int(blob, node, "spi-mode",
				    MCF_DSPI_DEFAULT_MODE);

	memset(plat->ctar, 0, sizeof(plat->ctar));

	ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);

	if (ctar && len) {
		int i, q, ctar_regs;

		ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;

		if (ctar_regs > MAX_CTAR_REGS)
			ctar_regs = MAX_CTAR_REGS;

		for (i = 0; i < ctar_regs; i++) {
			for (q = 0; q < MAX_CTAR_FIELDS; q++)
				plat->ctar[i][q] = *ctar++;
		}
	}

	debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
	      (void *)plat->regs_addr,
	       plat->speed_hz, plat->num_cs, plat->mode);

	return 0;
}

static const struct udevice_id coldfire_spi_ids[] = {
	{ .compatible = "fsl,mcf-dspi" },
	{ }
};
#endif

static const struct dm_spi_ops coldfire_spi_ops = {
	.claim_bus	= coldfire_spi_claim_bus,
	.release_bus	= coldfire_spi_release_bus,
	.xfer		= coldfire_spi_xfer,
	.set_speed	= coldfire_spi_set_speed,
	.set_mode	= coldfire_spi_set_mode,
};

U_BOOT_DRIVER(coldfire_spi) = {
	.name = "spi_coldfire",
	.id = UCLASS_SPI,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
	.of_match = coldfire_spi_ids,
	.of_to_plat = coldfire_dspi_of_to_plat,
	.plat_auto	= sizeof(struct coldfire_spi_plat),
#endif
	.probe = coldfire_spi_probe,
	.ops = &coldfire_spi_ops,
	.priv_auto	= sizeof(struct coldfire_spi_priv),
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
dec61c78 TL	2	/*
	3	*
	4	* (C) Copyright 2000-2003
	5	* Wolfgang Denk, DENX Software Engineering, [email protected].
	6	*
	7	* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
	8	* TsiChung Liew ([email protected])
5ea37664 AD	9	*
	10	* Support for DM and DT, non-DM code removed.
	11	* Copyright (C) 2018 Angelo Dureghello <[email protected]>
	12	*
	13	* TODO: fsl_dspi.c should work as a driver for the DSPI module.
dec61c78 TL	14	*/
	15
	16	#include <common.h>
5ea37664	17	#include <dm.h>
f7ae49fc	18	#include <log.h>
5ea37664	19	#include <dm/platform_data/spi_coldfire.h>
dec61c78 TL	20	#include <spi.h>
dec61c78 TL	21	#include <malloc.h>
5ea37664 AD	22	#include <asm/coldfire/dspi.h>
5ea37664 AD	23	#include <asm/io.h>
dec61c78	24
5ea37664 AD	25	struct coldfire_spi_priv {
5ea37664 AD	26	struct dspi *regs;
dec61c78	27	uint baudrate;
5ea37664	28	int mode;
dec61c78 TL	29	int charbit;
	30	};
	31
dec61c78 TL	32	DECLARE_GLOBAL_DATA_PTR;
dec61c78 TL	33
b97e0cd7 WW	34	#ifndef CONFIG_SPI_IDLE_VAL
	35	#if defined(CONFIG_SPI_MMC)
	36	#define CONFIG_SPI_IDLE_VAL 0xFFFF
	37	#else
	38	#define CONFIG_SPI_IDLE_VAL 0x0
	39	#endif
	40	#endif
	41
5ea37664 AD	42	/*
	43	* DSPI specific mode
	44	*
	45	* bit 31 - 28: Transfer size 3 to 16 bits
	46	* 27 - 26: PCS to SCK delay prescaler
	47	* 25 - 24: After SCK delay prescaler
	48	* 23 - 22: Delay after transfer prescaler
	49	* 21 : Allow overwrite for bit 31-22 and bit 20-8
	50	* 20 : Double baud rate
	51	* 19 - 16: PCS to SCK delay scaler
	52	* 15 - 12: After SCK delay scaler
	53	* 11 - 8: Delay after transfer scaler
	54	* 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
	55	*/
	56	#define SPI_MODE_MOD 0x00200000
	57	#define SPI_MODE_DBLRATE 0x00100000
	58
	59	#define SPI_MODE_XFER_SZ_MASK 0xf0000000
	60	#define SPI_MODE_DLY_PRE_MASK 0x0fc00000
	61	#define SPI_MODE_DLY_SCA_MASK 0x000fff00
	62
	63	#define MCF_FRM_SZ_16BIT DSPI_CTAR_TRSZ(0xf)
	64	#define MCF_DSPI_SPEED_BESTMATCH 0x7FFFFFFF
	65	#define MCF_DSPI_MAX_CTAR_REGS 8
	66
	67	/* Default values */
	68	#define MCF_DSPI_DEFAULT_SCK_FREQ 10000000
	69	#define MCF_DSPI_DEFAULT_MAX_CS 4
	70	#define MCF_DSPI_DEFAULT_MODE 0
	71
	72	#define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) \| \
	73	DSPI_CTAR_PCSSCK_1CLK \| \
	74	DSPI_CTAR_PASC(0) \| \
	75	DSPI_CTAR_PDT(0) \| \
	76	DSPI_CTAR_CSSCK(0) \| \
	77	DSPI_CTAR_ASC(0) \| \
	78	DSPI_CTAR_DT(1) \| \
	79	DSPI_CTAR_BR(6))
	80
	81	#define MCF_CTAR_MODE_MASK (MCF_FRM_SZ_16BIT \| \
	82	DSPI_CTAR_PCSSCK(3) \| \
	83	DSPI_CTAR_PASC_7CLK \| \
	84	DSPI_CTAR_PDT(3) \| \
	85	DSPI_CTAR_CSSCK(0x0f) \| \
	86	DSPI_CTAR_ASC(0x0f) \| \
	87	DSPI_CTAR_DT(0x0f))
	88
	89	#define setup_ctrl(ctrl, cs) ((ctrl & 0xFF000000) \| ((1 << cs) << 16))
	90
	91	static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
	92	u32 ctrl, u16 data)
bb166276	93	{
5ea37664 AD	94	/*
	95	* Need to check fifo level here
	96	*/
	97	while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000)
	98	;
	99
	100	writel(ctrl \| data, &cfspi->regs->tfr);
bb166276 AL	101	}
bb166276 AL	102
5ea37664	103	static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
dec61c78	104	{
dec61c78	105
5ea37664 AD	106	while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
5ea37664 AD	107	;
dec61c78	108
5ea37664	109	return readw(&cfspi->regs->rfr);
dec61c78 TL	110	}
dec61c78 TL	111
5ea37664	112	static int coldfire_spi_claim_bus(struct udevice *dev)
dec61c78	113	{
5ea37664 AD	114	struct udevice *bus = dev->parent;
	115	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	116	struct dspi *dspi = cfspi->regs;
8a8d24bd	117	struct dm_spi_slave_plat *slave_plat =
caa4daa2	118	dev_get_parent_plat(dev);
dec61c78	119
5ea37664 AD	120	if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
5ea37664 AD	121	return -1;
dec61c78	122
5ea37664 AD	123	/* Clear FIFO and resume transfer */
	124	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF \| DSPI_MCR_CRXF);
	125
	126	dspi_chip_select(slave_plat->cs);
	127
	128	return 0;
dec61c78 TL	129	}
dec61c78 TL	130
5ea37664	131	static int coldfire_spi_release_bus(struct udevice *dev)
dec61c78	132	{
5ea37664 AD	133	struct udevice *bus = dev->parent;
	134	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	135	struct dspi *dspi = cfspi->regs;
8a8d24bd	136	struct dm_spi_slave_plat *slave_plat =
caa4daa2	137	dev_get_parent_plat(dev);
dec61c78	138
5ea37664 AD	139	/* Clear FIFO */
5ea37664 AD	140	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF \| DSPI_MCR_CRXF);
dec61c78	141
5ea37664 AD	142	dspi_chip_unselect(slave_plat->cs);
	143
	144	return 0;
dec61c78 TL	145	}
dec61c78 TL	146
5ea37664 AD	147	static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
	148	const void dout, void din,
	149	unsigned long flags)
dec61c78	150	{
5ea37664 AD	151	struct udevice *bus = dev_get_parent(dev);
5ea37664 AD	152	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
8a8d24bd	153	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
dec61c78 TL	154	u16 spi_rd16 = NULL, spi_wr16 = NULL;
dec61c78 TL	155	u8 spi_rd = NULL, spi_wr = NULL;
5ea37664	156	static u32 ctrl;
dec61c78 TL	157	uint len = bitlen >> 3;
dec61c78 TL	158
5ea37664	159	if (cfspi->charbit == 16) {
dec61c78	160	bitlen >>= 1;
5ea37664 AD	161	spi_wr16 = (u16 *)dout;
5ea37664 AD	162	spi_rd16 = (u16 *)din;
dec61c78	163	} else {
5ea37664 AD	164	spi_wr = (u8 *)dout;
5ea37664 AD	165	spi_rd = (u8 *)din;
dec61c78 TL	166	}
	167
	168	if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
	169	ctrl \|= DSPI_TFR_CONT;
	170
5ea37664	171	ctrl = setup_ctrl(ctrl, slave_plat->cs);
dec61c78 TL	172
	173	if (len > 1) {
	174	int tmp_len = len - 1;
5ea37664	175
dec61c78	176	while (tmp_len--) {
5ea37664 AD	177	if (dout) {
	178	if (cfspi->charbit == 16)
	179	cfspi_tx(cfspi, ctrl, *spi_wr16++);
dec61c78	180	else
5ea37664 AD	181	cfspi_tx(cfspi, ctrl, *spi_wr++);
5ea37664 AD	182	cfspi_rx(cfspi);
dec61c78 TL	183	}
dec61c78 TL	184
5ea37664 AD	185	if (din) {
	186	cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
	187	if (cfspi->charbit == 16)
	188	*spi_rd16++ = cfspi_rx(cfspi);
dec61c78	189	else
5ea37664	190	*spi_rd++ = cfspi_rx(cfspi);
dec61c78 TL	191	}
	192	}
	193
	194	len = 1; /* remaining byte */
	195	}
	196
5ea37664	197	if (flags & SPI_XFER_END)
dec61c78 TL	198	ctrl &= ~DSPI_TFR_CONT;
	199
	200	if (len) {
5ea37664 AD	201	if (dout) {
	202	if (cfspi->charbit == 16)
	203	cfspi_tx(cfspi, ctrl, *spi_wr16);
dec61c78	204	else
5ea37664 AD	205	cfspi_tx(cfspi, ctrl, *spi_wr);
5ea37664 AD	206	cfspi_rx(cfspi);
dec61c78 TL	207	}
dec61c78 TL	208
5ea37664 AD	209	if (din) {
	210	cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
	211	if (cfspi->charbit == 16)
	212	*spi_rd16 = cfspi_rx(cfspi);
dec61c78	213	else
5ea37664	214	*spi_rd = cfspi_rx(cfspi);
dec61c78 TL	215	}
	216	} else {
	217	/* dummy read */
5ea37664 AD	218	cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
5ea37664 AD	219	cfspi_rx(cfspi);
dec61c78 TL	220	}
	221
	222	return 0;
	223	}
	224
5ea37664	225	static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
dec61c78	226	{
5ea37664 AD	227	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
5ea37664 AD	228	struct dspi *dspi = cfspi->regs;
dec61c78 TL	229	int prescaler[] = { 2, 3, 5, 7 };
	230	int scaler[] = {
	231	2, 4, 6, 8,
	232	16, 32, 64, 128,
	233	256, 512, 1024, 2048,
	234	4096, 8192, 16384, 32768
	235	};
	236	int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
5ea37664 AD	237	int best_i, best_j, bestmatch = MCF_DSPI_SPEED_BESTMATCH, baud_speed;
	238	u32 bus_setup;
	239
	240	cfspi->baudrate = max_hz;
	241
	242	/* Read current setup */
8b85dfc6	243	bus_setup = readl(&dspi->ctar[dev_seq(bus)]);
dec61c78 TL	244
	245	tmp = (prescaler[3] * scaler[15]);
	246	/* Maximum and minimum baudrate it can handle */
5ea37664 AD	247	if ((cfspi->baudrate > (gd->bus_clk >> 1)) \|\|
5ea37664 AD	248	(cfspi->baudrate < (gd->bus_clk / tmp))) {
dec61c78 TL	249	printf("Exceed baudrate limitation: Max %d - Min %d\n",
dec61c78 TL	250	(int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
5ea37664	251	return -1;
dec61c78 TL	252	}
	253
	254	/* Activate Double Baud when it exceed 1/4 the bus clk */
5ea37664 AD	255	if ((bus_setup & DSPI_CTAR_DBR) \|\|
5ea37664 AD	256	(cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
dec61c78 TL	257	bus_setup \|= DSPI_CTAR_DBR;
	258	dbr = 1;
	259	}
	260
dec61c78	261	/* Overwrite default value set in platform configuration file */
5ea37664	262	if (cfspi->mode & SPI_MODE_MOD) {
dec61c78 TL	263	/*
	264	* Check to see if it is enabled by default in platform
	265	* config, or manual setting passed by mode parameter
	266	*/
5ea37664	267	if (cfspi->mode & SPI_MODE_DBLRATE) {
dec61c78 TL	268	bus_setup \|= DSPI_CTAR_DBR;
	269	dbr = 1;
	270	}
5ea37664	271	}
dec61c78 TL	272
	273	pbrcnt = sizeof(prescaler) / sizeof(int);
	274	brcnt = sizeof(scaler) / sizeof(int);
	275
	276	/* baudrate calculation - to closer value, may not be exact match */
	277	for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) {
	278	baud_speed = gd->bus_clk / prescaler[i];
	279	for (j = 0; j < brcnt; j++) {
	280	tmp = (baud_speed / scaler[j]) * (1 + dbr);
	281
5ea37664 AD	282	if (tmp > cfspi->baudrate)
5ea37664 AD	283	diff = tmp - cfspi->baudrate;
dec61c78	284	else
5ea37664	285	diff = cfspi->baudrate - tmp;
dec61c78 TL	286
	287	if (diff < bestmatch) {
	288	bestmatch = diff;
	289	best_i = i;
	290	best_j = j;
	291	}
	292	}
	293	}
5ea37664 AD	294
5ea37664 AD	295	bus_setup &= ~(DSPI_CTAR_PBR(0x03) \| DSPI_CTAR_BR(0x0f));
dec61c78	296	bus_setup \|= (DSPI_CTAR_PBR(best_i) \| DSPI_CTAR_BR(best_j));
8b85dfc6	297	writel(bus_setup, &dspi->ctar[dev_seq(bus)]);
dec61c78	298
5ea37664	299	return 0;
dec61c78	300	}
dec61c78	301
5ea37664	302	static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
dec61c78	303	{
5ea37664 AD	304	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	305	struct dspi *dspi = cfspi->regs;
	306	u32 bus_setup = 0;
dec61c78	307
5ea37664	308	cfspi->mode = mode;
dec61c78	309
5ea37664 AD	310	if (cfspi->mode & SPI_CPOL)
	311	bus_setup \|= DSPI_CTAR_CPOL;
	312	if (cfspi->mode & SPI_CPHA)
	313	bus_setup \|= DSPI_CTAR_CPHA;
	314	if (cfspi->mode & SPI_LSB_FIRST)
	315	bus_setup \|= DSPI_CTAR_LSBFE;
dec61c78	316
5ea37664 AD	317	/* Overwrite default value set in platform configuration file */
	318	if (cfspi->mode & SPI_MODE_MOD) {
	319	if ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) == 0)
	320	bus_setup \|=
8b85dfc6	321	readl(&dspi->ctar[dev_seq(bus)]) & MCF_FRM_SZ_16BIT;
5ea37664 AD	322	else
	323	bus_setup \|=
	324	((cfspi->mode & SPI_MODE_XFER_SZ_MASK) >> 1);
dec61c78	325
5ea37664 AD	326	/* PSCSCK, PASC, PDT */
	327	bus_setup \|= (cfspi->mode & SPI_MODE_DLY_PRE_MASK) >> 4;
	328	/* CSSCK, ASC, DT */
	329	bus_setup \|= (cfspi->mode & SPI_MODE_DLY_SCA_MASK) >> 4;
	330	} else {
	331	bus_setup \|=
8b85dfc6	332	(readl(&dspi->ctar[dev_seq(bus)]) & MCF_CTAR_MODE_MASK);
5ea37664 AD	333	}
	334
	335	cfspi->charbit =
8b85dfc6	336	((readl(&dspi->ctar[dev_seq(bus)]) & MCF_FRM_SZ_16BIT) ==
5ea37664	337	MCF_FRM_SZ_16BIT) ? 16 : 8;
dec61c78	338
8b85dfc6	339	setbits_be32(&dspi->ctar[dev_seq(bus)], bus_setup);
dec61c78	340
5ea37664	341	return 0;
dec61c78 TL	342	}
dec61c78 TL	343
5ea37664	344	static int coldfire_spi_probe(struct udevice *bus)
dec61c78	345	{
8a8d24bd	346	struct coldfire_spi_plat *plat = dev_get_plat(bus);
5ea37664 AD	347	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	348	struct dspi *dspi = cfspi->regs;
	349	int i;
bb166276	350
5ea37664	351	cfspi->regs = (struct dspi *)plat->regs_addr;
dec61c78	352
5ea37664 AD	353	cfspi->baudrate = plat->speed_hz;
	354	cfspi->mode = plat->mode;
	355
	356	for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {
	357	unsigned int ctar = 0;
	358
	359	if (plat->ctar[i][0] == 0)
	360	break;
	361
	362	ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) \|
	363	DSPI_CTAR_PCSSCK(plat->ctar[i][1]) \|
	364	DSPI_CTAR_PASC(plat->ctar[i][2]) \|
	365	DSPI_CTAR_PDT(plat->ctar[i][3]) \|
	366	DSPI_CTAR_CSSCK(plat->ctar[i][4]) \|
	367	DSPI_CTAR_ASC(plat->ctar[i][5]) \|
	368	DSPI_CTAR_DT(plat->ctar[i][6]) \|
	369	DSPI_CTAR_BR(plat->ctar[i][7]);
	370
	371	writel(ctar, &cfspi->regs->ctar[i]);
	372	}
	373
	374	/* Default CTARs */
	375	for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
	376	writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);
	377
	378	dspi->mcr = DSPI_MCR_MSTR \| DSPI_MCR_CSIS7 \| DSPI_MCR_CSIS6 \|
	379	DSPI_MCR_CSIS5 \| DSPI_MCR_CSIS4 \| DSPI_MCR_CSIS3 \|
	380	DSPI_MCR_CSIS2 \| DSPI_MCR_CSIS1 \| DSPI_MCR_CSIS0 \|
	381	DSPI_MCR_CRXF \| DSPI_MCR_CTXF;
	382
	383	return 0;
dec61c78 TL	384	}
dec61c78 TL	385
5ea37664	386	#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
d1998a9f	387	static int coldfire_dspi_of_to_plat(struct udevice *bus)
dec61c78	388	{
5ea37664	389	fdt_addr_t addr;
8a8d24bd	390	struct coldfire_spi_plat *plat = bus->plat;
5ea37664 AD	391	const void *blob = gd->fdt_blob;
	392	int node = dev_of_offset(bus);
	393	int *ctar, len;
	394
2548493a	395	addr = dev_read_addr(bus);
5ea37664 AD	396	if (addr == FDT_ADDR_T_NONE)
	397	return -ENOMEM;
	398
	399	plat->regs_addr = addr;
	400
	401	plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
	402	MCF_DSPI_DEFAULT_MAX_CS);
	403
	404	plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
	405	MCF_DSPI_DEFAULT_SCK_FREQ);
	406
	407	plat->mode = fdtdec_get_int(blob, node, "spi-mode",
	408	MCF_DSPI_DEFAULT_MODE);
	409
	410	memset(plat->ctar, 0, sizeof(plat->ctar));
	411
	412	ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);
	413
	414	if (ctar && len) {
	415	int i, q, ctar_regs;
	416
	417	ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;
	418
	419	if (ctar_regs > MAX_CTAR_REGS)
	420	ctar_regs = MAX_CTAR_REGS;
	421
	422	for (i = 0; i < ctar_regs; i++) {
	423	for (q = 0; q < MAX_CTAR_FIELDS; q++)
	424	plat->ctar[i][q] = *ctar++;
	425	}
	426	}
	427
	428	debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
	429	(void *)plat->regs_addr,
	430	plat->speed_hz, plat->num_cs, plat->mode);
	431
	432	return 0;
dec61c78	433	}
5ea37664 AD	434
	435	static const struct udevice_id coldfire_spi_ids[] = {
	436	{ .compatible = "fsl,mcf-dspi" },
	437	{ }
	438	};
	439	#endif
	440
	441	static const struct dm_spi_ops coldfire_spi_ops = {
	442	.claim_bus = coldfire_spi_claim_bus,
	443	.release_bus = coldfire_spi_release_bus,
	444	.xfer = coldfire_spi_xfer,
	445	.set_speed = coldfire_spi_set_speed,
	446	.set_mode = coldfire_spi_set_mode,
	447	};
	448
	449	U_BOOT_DRIVER(coldfire_spi) = {
	450	.name = "spi_coldfire",
	451	.id = UCLASS_SPI,
	452	#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
	453	.of_match = coldfire_spi_ids,
d1998a9f	454	.of_to_plat = coldfire_dspi_of_to_plat,
8a8d24bd	455	.plat_auto = sizeof(struct coldfire_spi_plat),
5ea37664 AD	456	#endif
	457	.probe = coldfire_spi_probe,
	458	.ops = &coldfire_spi_ops,
41575d8e	459	.priv_auto = sizeof(struct coldfire_spi_priv),
5ea37664	460	};