projects / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 3225f34e BS |
2 | /* |
| 3 | * Configuation settings for the SAMA5D3xEK board. | |
| 4 | * | |
| 5 | * Copyright (C) 2012 - 2013 Atmel | |
| 6 | * | |
| 7 | * based on at91sam9m10g45ek.h by: | |
| 8 | * Stelian Pop <[email protected]> | |
| 9 | * Lead Tech Design <www.leadtechdesign.com> | |
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10 | */ |
| 11 | ||
| 12 | #ifndef __CONFIG_H | |
| 13 | #define __CONFIG_H | |
| 14 | ||
| b2d387bc | 15 | #include "at91-sama5_common.h" |
| 3225f34e | 16 | |
| 3225f34e BS |
17 | /* |
| 18 | * This needs to be defined for the OHCI code to work but it is defined as | |
| 19 | * ATMEL_ID_UHPHS in the CPU specific header files. | |
| 20 | */ | |
| e61ed48f | 21 | #define ATMEL_ID_UHP 32 |
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22 | |
| 23 | /* | |
| 24 | * Specify the clock enable bit in the PMC_SCER register. | |
| 25 | */ | |
| e61ed48f | 26 | #define ATMEL_PMC_UHP (1 << 6) |
| 3225f34e | 27 | |
| 3225f34e BS |
28 | /* board specific (not enough SRAM) */ |
| 29 | #define CONFIG_SAMA5D3_LCD_BASE 0x23E00000 | |
| 30 | ||
| d6b79434 | 31 | /* NOR flash */ |
| e856bdcf | 32 | #ifdef CONFIG_MTD_NOR_FLASH |
| d6b79434 BS |
33 | #define CONFIG_SYS_FLASH_BASE 0x10000000 |
| 34 | #define CONFIG_SYS_MAX_FLASH_SECT 131 | |
| 35 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
| d6b79434 | 36 | #endif |
| 3225f34e | 37 | |
| 3225f34e | 38 | /* SDRAM */ |
| e61ed48f | 39 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
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40 | #define CONFIG_SYS_SDRAM_SIZE 0x20000000 |
| 41 | ||
| c5e8885a | 42 | #ifdef CONFIG_SPL_BUILD |
| a97cb061 | 43 | #define CONFIG_SYS_INIT_SP_ADDR 0x318000 |
| c5e8885a | 44 | #else |
| 3225f34e | 45 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| a97cb061 | 46 | (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) |
| c5e8885a | 47 | #endif |
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48 | |
| 49 | /* SerialFlash */ | |
| 3225f34e | 50 | |
| 3225f34e | 51 | /* NAND flash */ |
| 3225f34e | 52 | #ifdef CONFIG_CMD_NAND |
| 3225f34e | 53 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| e61ed48f | 54 | #define CONFIG_SYS_NAND_BASE 0x60000000 |
| 3225f34e BS |
55 | /* our ALE is AD21 */ |
| 56 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) | |
| 57 | /* our CLE is AD22 */ | |
| 58 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) | |
| 8f1a80e9 | 59 | #endif |
| 3225f34e | 60 | |
| 3225f34e | 61 | /* USB */ |
| 3225f34e | 62 | #ifdef CONFIG_CMD_USB |
| dcd2f1a0 | 63 | #define CONFIG_USB_ATMEL_CLK_SEL_UPLL |
| 3225f34e BS |
64 | #define CONFIG_USB_OHCI_NEW |
| 65 | #define CONFIG_SYS_USB_OHCI_CPU_INIT | |
| 66 | #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI | |
| 67 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3" | |
| 68 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 | |
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69 | #endif |
| 70 | ||
| c5e8885a | 71 | /* SPL */ |
| a97cb061 | 72 | #define CONFIG_SPL_MAX_SIZE 0x18000 |
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73 | #define CONFIG_SPL_BSS_START_ADDR 0x20000000 |
| 74 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
| 75 | #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 | |
| 76 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 | |
| 77 | ||
| 8a45b0ba BS |
78 | #define CONFIG_SYS_MONITOR_LEN (512 << 10) |
| 79 | ||
| 5541543f | 80 | #ifdef CONFIG_SD_BOOT |
| 205b4f33 | 81 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
| 5541543f | 82 | #endif |
| 27019e4a | 83 | |
| 3225f34e | 84 | #endif |