[u-boot.git] / drivers / net / altera_tse.h

/*
 * Altera 10/100/1000 triple speed ethernet mac
 *
 * Copyright (C) 2008 Altera Corporation.
 * Copyright (C) 2010 Thomas Chou <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef _ALTERA_TSE_H_
#define _ALTERA_TSE_H_

#define __packed_1_    __packed __aligned(1)

/* dma type */
#define ALT_SGDMA	0
#define ALT_MSGDMA	1

/* SGDMA Stuff */
#define ALT_SGDMA_STATUS_BUSY_MSK				BIT(4)

#define ALT_SGDMA_CONTROL_RUN_MSK				BIT(5)
#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK			BIT(6)
#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK			BIT(16)

/*
 * Descriptor control bit masks & offsets
 *
 * Note: The control byte physically occupies bits [31:24] in memory.
 *	 The following bit-offsets are expressed relative to the LSB of
 *	 the control register bitfield.
 */
#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK		BIT(0)
#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK	BIT(1)
#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK	BIT(2)
#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK		BIT(7)

/*
 * Descriptor status bit masks & offsets
 *
 * Note: The status byte physically occupies bits [23:16] in memory.
 *	 The following bit-offsets are expressed relative to the LSB of
 *	 the status register bitfield.
 */
#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK	BIT(7)

/*
 * The SGDMA controller buffer descriptor allocates
 * 64 bits for each address. To support ANSI C, the
 * struct implementing a descriptor places 32-bits
 * of padding directly above each address; each pad must
 * be cleared when initializing a descriptor.
 */

/*
 * Buffer Descriptor data structure
 *
 */
struct alt_sgdma_descriptor {
	u32 source;	/* the address of data to be read. */
	u32 source_pad;

	u32 destination;	/* the address to write data */
	u32 destination_pad;

	u32 next;	/* the next descriptor in the list. */
	u32 next_pad;

	u16 bytes_to_transfer; /* the number of bytes to transfer */
	u8 read_burst;
	u8 write_burst;

	u16 actual_bytes_transferred;/* bytes transferred by DMA */
	u8 descriptor_status;
	u8 descriptor_control;

} __packed_1_;

/* SG-DMA Control/Status Slave registers map */

struct alt_sgdma_registers {
	u32 status;
	u32 status_pad[3];
	u32 control;
	u32 control_pad[3];
	u32 next_descriptor_pointer;
	u32 descriptor_pad[3];
};

/* mSGDMA Stuff */

/* mSGDMA extended descriptor format */
struct msgdma_extended_desc {
	u32 read_addr_lo;	/* data buffer source address low bits */
	u32 write_addr_lo;	/* data buffer destination address low bits */
	u32 len;
	u32 burst_seq_num;
	u32 stride;
	u32 read_addr_hi;	/* data buffer source address high bits */
	u32 write_addr_hi;	/* data buffer destination address high bits */
	u32 control;		/* characteristics of the transfer */
};

/* mSGDMA descriptor control field bit definitions */
#define MSGDMA_DESC_CTL_GEN_SOP		BIT(8)
#define MSGDMA_DESC_CTL_GEN_EOP		BIT(9)
#define MSGDMA_DESC_CTL_END_ON_EOP	BIT(12)
#define MSGDMA_DESC_CTL_END_ON_LEN	BIT(13)
#define MSGDMA_DESC_CTL_GO		BIT(31)

/* Tx buffer control flags */
#define MSGDMA_DESC_CTL_TX_SINGLE	(MSGDMA_DESC_CTL_GEN_SOP |	\
					 MSGDMA_DESC_CTL_GEN_EOP |	\
					 MSGDMA_DESC_CTL_GO)

#define MSGDMA_DESC_CTL_RX_SINGLE	(MSGDMA_DESC_CTL_END_ON_EOP |	\
					 MSGDMA_DESC_CTL_END_ON_LEN |	\
					 MSGDMA_DESC_CTL_GO)

/* mSGDMA extended descriptor stride definitions */
#define MSGDMA_DESC_TX_STRIDE		0x00010001
#define MSGDMA_DESC_RX_STRIDE		0x00010001

/* mSGDMA dispatcher control and status register map */
struct msgdma_csr {
	u32 status;		/* Read/Clear */
	u32 control;		/* Read/Write */
	u32 rw_fill_level;
	u32 resp_fill_level;	/* bit 15:0 */
	u32 rw_seq_num;
	u32 pad[3];		/* reserved */
};

/* mSGDMA CSR status register bit definitions */
#define MSGDMA_CSR_STAT_BUSY			BIT(0)
#define MSGDMA_CSR_STAT_RESETTING		BIT(6)
#define MSGDMA_CSR_STAT_MASK			0x3FF

/* mSGDMA CSR control register bit definitions */
#define MSGDMA_CSR_CTL_RESET			BIT(1)

/* mSGDMA response register map */
struct msgdma_response {
	u32 bytes_transferred;
	u32 status;
};

/* TSE Stuff */
#define ALTERA_TSE_CMD_TX_ENA_MSK		BIT(0)
#define ALTERA_TSE_CMD_RX_ENA_MSK		BIT(1)
#define ALTERA_TSE_CMD_ETH_SPEED_MSK		BIT(3)
#define ALTERA_TSE_CMD_HD_ENA_MSK		BIT(10)
#define ALTERA_TSE_CMD_SW_RESET_MSK		BIT(13)
#define ALTERA_TSE_CMD_ENA_10_MSK		BIT(25)

#define ALT_TSE_SW_RESET_TIMEOUT		(3 * CONFIG_SYS_HZ)
#define ALT_TSE_SGDMA_BUSY_TIMEOUT		(3 * CONFIG_SYS_HZ)

/* MAC register Space */

struct alt_tse_mac {
	u32 megacore_revision;
	u32 scratch_pad;
	u32 command_config;
	u32 mac_addr_0;
	u32 mac_addr_1;
	u32 max_frame_length;
	u32 pause_quanta;
	u32 rx_sel_empty_threshold;
	u32 rx_sel_full_threshold;
	u32 tx_sel_empty_threshold;
	u32 tx_sel_full_threshold;
	u32 rx_almost_empty_threshold;
	u32 rx_almost_full_threshold;
	u32 tx_almost_empty_threshold;
	u32 tx_almost_full_threshold;
	u32 mdio_phy0_addr;
	u32 mdio_phy1_addr;

	u32 reserved1[0x29];

	/*FIFO control register. */
	u32 tx_cmd_stat;
	u32 rx_cmd_stat;

	u32 reserved2[0x44];

	/*Registers 0 to 31 within PHY device 0/1 */
	u32 mdio_phy0[0x20];
	u32 mdio_phy1[0x20];

	/*4 Supplemental MAC Addresses */
	u32 supp_mac_addr_0_0;
	u32 supp_mac_addr_0_1;
	u32 supp_mac_addr_1_0;
	u32 supp_mac_addr_1_1;
	u32 supp_mac_addr_2_0;
	u32 supp_mac_addr_2_1;
	u32 supp_mac_addr_3_0;
	u32 supp_mac_addr_3_1;

	u32 reserved3[0x38];
};

struct tse_ops {
	int (*send)(struct udevice *dev, void *packet, int length);
	int (*recv)(struct udevice *dev, int flags, uchar **packetp);
	int (*free_pkt)(struct udevice *dev, uchar *packet, int length);
	void (*stop)(struct udevice *dev);
};

struct altera_tse_priv {
	struct alt_tse_mac *mac_dev;
	void *sgdma_rx;
	void *sgdma_tx;
	unsigned int rx_fifo_depth;
	unsigned int tx_fifo_depth;
	void *rx_desc;
	void *tx_desc;
	void *rx_resp;
	unsigned char *rx_buf;
	unsigned int phyaddr;
	unsigned int interface;
	struct phy_device *phydev;
	struct mii_dev *bus;
	const struct tse_ops *ops;
	int dma_type;
};

#endif /* _ALTERA_TSE_H_ */
Commit	Line	Data
c960b13e TC	1	/*
	2	* Altera 10/100/1000 triple speed ethernet mac
	3	*
	4	* Copyright (C) 2008 Altera Corporation.
	5	* Copyright (C) 2010 Thomas Chou <[email protected]>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#ifndef _ALTERA_TSE_H_
	12	#define _ALTERA_TSE_H_
	13
13146ec9	14	#define __packed_1_ __packed __aligned(1)
c960b13e	15
38fa4aca TC	16	/* dma type */
38fa4aca TC	17	#define ALT_SGDMA 0
e3e87260	18	#define ALT_MSGDMA 1
38fa4aca	19
c960b13e	20	/* SGDMA Stuff */
4c8df1d3	21	#define ALT_SGDMA_STATUS_BUSY_MSK BIT(4)
c960b13e	22
4c8df1d3 TC	23	#define ALT_SGDMA_CONTROL_RUN_MSK BIT(5)
	24	#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK BIT(6)
	25	#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK BIT(16)
c960b13e	26
c960b13e TC	27	/*
	28	* Descriptor control bit masks & offsets
	29	*
	30	* Note: The control byte physically occupies bits [31:24] in memory.
	31	* The following bit-offsets are expressed relative to the LSB of
	32	* the control register bitfield.
	33	*/
4c8df1d3 TC	34	#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK BIT(0)
	35	#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK BIT(1)
	36	#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK BIT(2)
	37	#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK BIT(7)
c960b13e TC	38
	39	/*
	40	* Descriptor status bit masks & offsets
	41	*
	42	* Note: The status byte physically occupies bits [23:16] in memory.
	43	* The following bit-offsets are expressed relative to the LSB of
	44	* the status register bitfield.
	45	*/
4c8df1d3	46	#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK BIT(7)
c960b13e TC	47
	48	/*
	49	* The SGDMA controller buffer descriptor allocates
	50	* 64 bits for each address. To support ANSI C, the
	51	* struct implementing a descriptor places 32-bits
	52	* of padding directly above each address; each pad must
	53	* be cleared when initializing a descriptor.
	54	*/
	55
	56	/*
	57	* Buffer Descriptor data structure
	58	*
	59	*/
	60	struct alt_sgdma_descriptor {
2cd0a52e TC	61	u32 source; /* the address of data to be read. */
2cd0a52e TC	62	u32 source_pad;
c960b13e	63
2cd0a52e TC	64	u32 destination; /* the address to write data */
2cd0a52e TC	65	u32 destination_pad;
c960b13e	66
2cd0a52e TC	67	u32 next; /* the next descriptor in the list. */
2cd0a52e TC	68	u32 next_pad;
c960b13e	69
2cd0a52e TC	70	u16 bytes_to_transfer; /* the number of bytes to transfer */
	71	u8 read_burst;
	72	u8 write_burst;
c960b13e	73
2cd0a52e TC	74	u16 actual_bytes_transferred;/* bytes transferred by DMA */
	75	u8 descriptor_status;
	76	u8 descriptor_control;
c960b13e TC	77
	78	} __packed_1_;
	79
	80	/* SG-DMA Control/Status Slave registers map */
	81
	82	struct alt_sgdma_registers {
2cd0a52e TC	83	u32 status;
	84	u32 status_pad[3];
	85	u32 control;
	86	u32 control_pad[3];
	87	u32 next_descriptor_pointer;
	88	u32 descriptor_pad[3];
c960b13e TC	89	};
c960b13e TC	90
e3e87260 TC	91	/* mSGDMA Stuff */
	92
	93	/* mSGDMA extended descriptor format */
	94	struct msgdma_extended_desc {
	95	u32 read_addr_lo; /* data buffer source address low bits */
	96	u32 write_addr_lo; /* data buffer destination address low bits */
	97	u32 len;
	98	u32 burst_seq_num;
	99	u32 stride;
	100	u32 read_addr_hi; /* data buffer source address high bits */
	101	u32 write_addr_hi; /* data buffer destination address high bits */
	102	u32 control; /* characteristics of the transfer */
	103	};
	104
	105	/* mSGDMA descriptor control field bit definitions */
	106	#define MSGDMA_DESC_CTL_GEN_SOP BIT(8)
	107	#define MSGDMA_DESC_CTL_GEN_EOP BIT(9)
	108	#define MSGDMA_DESC_CTL_END_ON_EOP BIT(12)
	109	#define MSGDMA_DESC_CTL_END_ON_LEN BIT(13)
	110	#define MSGDMA_DESC_CTL_GO BIT(31)
	111
	112	/* Tx buffer control flags */
	113	#define MSGDMA_DESC_CTL_TX_SINGLE (MSGDMA_DESC_CTL_GEN_SOP \| \
	114	MSGDMA_DESC_CTL_GEN_EOP \| \
	115	MSGDMA_DESC_CTL_GO)
	116
	117	#define MSGDMA_DESC_CTL_RX_SINGLE (MSGDMA_DESC_CTL_END_ON_EOP \| \
	118	MSGDMA_DESC_CTL_END_ON_LEN \| \
	119	MSGDMA_DESC_CTL_GO)
	120
	121	/* mSGDMA extended descriptor stride definitions */
	122	#define MSGDMA_DESC_TX_STRIDE 0x00010001
	123	#define MSGDMA_DESC_RX_STRIDE 0x00010001
	124
	125	/* mSGDMA dispatcher control and status register map */
	126	struct msgdma_csr {
	127	u32 status; /* Read/Clear */
	128	u32 control; /* Read/Write */
	129	u32 rw_fill_level;
	130	u32 resp_fill_level; /* bit 15:0 */
	131	u32 rw_seq_num;
	132	u32 pad[3]; /* reserved */
	133	};
	134
	135	/* mSGDMA CSR status register bit definitions */
	136	#define MSGDMA_CSR_STAT_BUSY BIT(0)
	137	#define MSGDMA_CSR_STAT_RESETTING BIT(6)
	138	#define MSGDMA_CSR_STAT_MASK 0x3FF
	139
	140	/* mSGDMA CSR control register bit definitions */
	141	#define MSGDMA_CSR_CTL_RESET BIT(1)
	142
	143	/* mSGDMA response register map */
	144	struct msgdma_response {
	145	u32 bytes_transferred;
	146	u32 status;
	147	};
	148
c960b13e	149	/* TSE Stuff */
4c8df1d3 TC	150	#define ALTERA_TSE_CMD_TX_ENA_MSK BIT(0)
	151	#define ALTERA_TSE_CMD_RX_ENA_MSK BIT(1)
	152	#define ALTERA_TSE_CMD_ETH_SPEED_MSK BIT(3)
	153	#define ALTERA_TSE_CMD_HD_ENA_MSK BIT(10)
	154	#define ALTERA_TSE_CMD_SW_RESET_MSK BIT(13)
	155	#define ALTERA_TSE_CMD_ENA_10_MSK BIT(25)
c960b13e	156
96fa1e43 TC	157	#define ALT_TSE_SW_RESET_TIMEOUT (3 * CONFIG_SYS_HZ)
96fa1e43 TC	158	#define ALT_TSE_SGDMA_BUSY_TIMEOUT (3 * CONFIG_SYS_HZ)
c960b13e TC	159
	160	/* MAC register Space */
	161
	162	struct alt_tse_mac {
2cd0a52e TC	163	u32 megacore_revision;
	164	u32 scratch_pad;
	165	u32 command_config;
	166	u32 mac_addr_0;
	167	u32 mac_addr_1;
	168	u32 max_frame_length;
	169	u32 pause_quanta;
	170	u32 rx_sel_empty_threshold;
	171	u32 rx_sel_full_threshold;
	172	u32 tx_sel_empty_threshold;
	173	u32 tx_sel_full_threshold;
	174	u32 rx_almost_empty_threshold;
	175	u32 rx_almost_full_threshold;
	176	u32 tx_almost_empty_threshold;
	177	u32 tx_almost_full_threshold;
	178	u32 mdio_phy0_addr;
	179	u32 mdio_phy1_addr;
	180
	181	u32 reserved1[0x29];
c960b13e TC	182
c960b13e TC	183	/FIFO control register. /
2cd0a52e TC	184	u32 tx_cmd_stat;
2cd0a52e TC	185	u32 rx_cmd_stat;
c960b13e	186
2cd0a52e	187	u32 reserved2[0x44];
c960b13e TC	188
c960b13e TC	189	/Registers 0 to 31 within PHY device 0/1 /
2cd0a52e TC	190	u32 mdio_phy0[0x20];
2cd0a52e TC	191	u32 mdio_phy1[0x20];
c960b13e TC	192
c960b13e TC	193	/4 Supplemental MAC Addresses /
2cd0a52e TC	194	u32 supp_mac_addr_0_0;
	195	u32 supp_mac_addr_0_1;
	196	u32 supp_mac_addr_1_0;
	197	u32 supp_mac_addr_1_1;
	198	u32 supp_mac_addr_2_0;
	199	u32 supp_mac_addr_2_1;
	200	u32 supp_mac_addr_3_0;
	201	u32 supp_mac_addr_3_1;
	202
	203	u32 reserved3[0x38];
c960b13e TC	204	};
c960b13e TC	205
38fa4aca TC	206	struct tse_ops {
	207	int (send)(struct udevice dev, void *packet, int length);
	208	int (recv)(struct udevice dev, int flags, uchar **packetp);
	209	int (free_pkt)(struct udevice dev, uchar *packet, int length);
	210	void (stop)(struct udevice dev);
	211	};
	212
c960b13e	213	struct altera_tse_priv {
96fa1e43	214	struct alt_tse_mac *mac_dev;
38fa4aca TC	215	void *sgdma_rx;
38fa4aca TC	216	void *sgdma_tx;
96fa1e43 TC	217	unsigned int rx_fifo_depth;
96fa1e43 TC	218	unsigned int tx_fifo_depth;
38fa4aca TC	219	void *rx_desc;
38fa4aca TC	220	void *tx_desc;
e3e87260	221	void *rx_resp;
96fa1e43	222	unsigned char *rx_buf;
c960b13e	223	unsigned int phyaddr;
96fa1e43 TC	224	unsigned int interface;
	225	struct phy_device *phydev;
	226	struct mii_dev *bus;
38fa4aca TC	227	const struct tse_ops *ops;
38fa4aca TC	228	int dma_type;
c960b13e TC	229	};
c960b13e TC	230
c960b13e	231	#endif /* _ALTERA_TSE_H_ */