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Commit | Line | Data |
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27e166b8 WD |
1 | ====================================================================== |
2 | Changes since U-Boot 1.1.4: | |
3 | ====================================================================== | |
4 | ||
8419c013 WD |
5 | * MPC5200: enable snooping of DMA transactions on XLB even if no PCI |
6 | is configured; othrwise DMA accesses aren't cache coherent which | |
7 | causes for example USB to fail. | |
8 | ||
cf48eb9a | 9 | * Some code cleanup |
bb74140d | 10 | |
cf48eb9a WD |
11 | * Fix dbau1x00 boards broken by dbau1550 patch |
12 | PLL:s were not set for boards other than 1550. | |
13 | Flash CFI caused card to hang due to undefined CFG_FLASH_BANKS_LIST. | |
14 | Default boot is now bootp for cards other than 1550. | |
15 | Patch by Thomas Lange, 10 Aug 2005 | |
16 | ||
17 | * Fixes common/cmd_flash.c: | |
18 | - fix some compiler/parser error, if using m68k tool chain | |
19 | - optical fix for protect on/off all messages, if using more | |
20 | then one bank | |
21 | Patch by Jens Scharsig, 28 Jul 2005 | |
27e166b8 | 22 | |
b81a4630 WD |
23 | * Fix Quad UART mapping on MCC200 board due to new HW revision |
24 | ||
b28a31ca WD |
25 | * Fix JFFS2 support for legacy NAND driver. |
26 | ||
27 | * Remove dependencies between DoC code and old legacy NAND driver. | |
28 | ||
29 | * Fix PM828_PCI target, for which PCI was *not* configured in. | |
30 | ||
5fbb2cd3 WD |
31 | * Fix Lite5200B support: initialize SDelay register |
32 | See Freescale's AN3221 "MPC5200B SDRAM Initialization and | |
33 | Configuration", 3.3.1 SDelay--MBAR + 0x0190 | |
34 | ||
2662b40c SR |
35 | * Changes/fixes for drivers/cfi_flash.c: |
36 | ||
37 | - Add Intel legacy lock/unlock support to common CFI driver | |
38 | ||
39 | On some Intel flash's (e.g. Intel J3) legacy unlocking is | |
40 | supported, meaning that unlocking of one sector will unlock | |
41 | all sectors of this bank. Using this feature, unlocking | |
42 | of all sectors upon startup (via env var "unlock=yes") will | |
43 | get much faster. | |
44 | ||
45 | - Fixed problem with multiple reads of envronment variable | |
46 | "unlock" as pointed out by Reinhard Arlt & Anders Larsen. | |
47 | ||
48 | - Removed unwanted linefeeds from "protect" command when | |
49 | CFG_FLASH_PROTECTION is enabled. | |
50 | ||
51 | - Changed p3p400 board to use CFG_FLASH_PROTECTION | |
52 | ||
53 | Patch by Stefan Roese, 01 Apr 2006 | |
54 | ||
55 | * Changes/fixes for drivers/cfi_flash.c: | |
56 | - Correctly handle the cases where CFG_HZ != 1000 (several | |
57 | XScale-based boards) | |
58 | - Fix the timeout calculation of buffered writes (off by a | |
59 | factor of 1000) | |
60 | Patch by Anders Larsen, 31 Mar 2006 | |
61 | ||
35118539 SR |
62 | * Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440) |
63 | ||
64 | 405 SDRAM: - The SDRAM parameters can now be defined in the board | |
cf48eb9a WD |
65 | config file and the 405 SDRAM controller values will |
66 | be calculated upon bootup (see PPChameleonEVB). | |
67 | When those settings are not defined in the board | |
68 | config file, the register setup will be as it is now, | |
69 | so this implementation should not break any current | |
70 | design using this code. | |
35118539 | 71 | |
cf48eb9a | 72 | Thanks to Andrea Marson from DAVE for this patch. |
35118539 SR |
73 | |
74 | 440 DDR: - Added function sdram_tr1_set to auto calculate the | |
cf48eb9a WD |
75 | TR1 value for the DDR. |
76 | - Added ECC support (see p3p440). | |
35118539 SR |
77 | |
78 | Patch by Stefan Roese, 17 Mar 2006 | |
79 | ||
db28ddb4 WD |
80 | * Fix CONFIG_SKIP_LOWLEVEL_INIT dependency in cpu/arm920t/start.S |
81 | Patch by Peter Menzebach, 13 Oct 2005 [DNX#2006040142000473] | |
82 | ||
534ff676 WD |
83 | * Add support for ymodem protocol download |
84 | Patch by Stefano Babic, 29 Mar 2006 | |
85 | ||
86 | * Memory Map Update for Delta board: U-Boot is at 0x80000000-0x84000000 | |
87 |