[u-boot.git] / include / configs / ls1021atwr.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_ARMV7_PSCI_1_0

#define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR

#define CONFIG_SYS_FSL_CLK

#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_DEEP_SLEEP

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 16 * 1024 * 1024)

#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE

#define CONFIG_SYS_CLK_FREQ		100000000
#define CONFIG_DDR_CLK_FREQ		100000000

#define DDR_SDRAM_CFG			0x470c0008
#define DDR_CS0_BNDS			0x008000bf
#define DDR_CS0_CONFIG			0x80014302
#define DDR_TIMING_CFG_0		0x50550004
#define DDR_TIMING_CFG_1		0xbcb38c56
#define DDR_TIMING_CFG_2		0x0040d120
#define DDR_TIMING_CFG_3		0x010e1000
#define DDR_TIMING_CFG_4		0x00000001
#define DDR_TIMING_CFG_5		0x03401400
#define DDR_SDRAM_CFG_2			0x00401010
#define DDR_SDRAM_MODE			0x00061c60
#define DDR_SDRAM_MODE_2		0x00180000
#define DDR_SDRAM_INTERVAL		0x18600618
#define DDR_DDR_WRLVL_CNTL		0x8655f605
#define DDR_DDR_WRLVL_CNTL_2		0x05060607
#define DDR_DDR_WRLVL_CNTL_3		0x05050505
#define DDR_DDR_CDR1			0x80040000
#define DDR_DDR_CDR2			0x00000001
#define DDR_SDRAM_CLK_CNTL		0x02000000
#define DDR_DDR_ZQ_CNTL			0x89080600
#define DDR_CS0_CONFIG_2		0
#define DDR_SDRAM_CFG_MEM_EN		0x80000000
#define SDRAM_CFG2_D_INIT		0x00000010
#define DDR_CDR2_VREF_TRAIN_EN		0x00000080
#define SDRAM_CFG2_FRC_SR		0x80000000
#define SDRAM_CFG_BI			0x00000001

#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI	board/freescale/ls1021atwr/ls102xa_pbi.cfg
#endif

#ifdef CONFIG_SD_BOOT
#ifdef CONFIG_SD_BOOT_QSPI
#define CONFIG_SYS_FSL_PBL_RCW	\
	board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
#else
#define CONFIG_SYS_FSL_PBL_RCW	\
	board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
#endif

#ifdef CONFIG_SECURE_BOOT
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image.
 */
#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
#endif /* ifdef CONFIG_SECURE_BOOT */

#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SPL_PAD_TO		0x1c000

#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
		CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#ifdef CONFIG_U_BOOT_HDR_SIZE
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image. Here u-boot max. size is 512K. So if binary
 * size increases then increase this size in case of secure boot as
 * it uses raw u-boot image instead of fit image.
 */
#define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN		0x100000
#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
#endif

#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM			0x80000000
#define PHYS_SDRAM_SIZE			(1u * 1024 * 1024 * 1024)

#define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE

#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
	!defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#endif

/*
 * IFC Definitions
 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_FSL_IFC
#define CONFIG_SYS_FLASH_BASE		0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)

/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_TRHZ_80)
#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
					FTIM0_NOR_TEADC(0x5) | \
					FTIM0_NOR_TAVDS(0x0) | \
					FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
					FTIM1_NOR_TRAD_NOR(0x1A) | \
					FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
					FTIM2_NOR_TCH(0x4) | \
					FTIM2_NOR_TWP(0x1c) | \
					FTIM2_NOR_TWPH(0x0e))
#define CONFIG_SYS_NOR_FTIM3		0

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }

#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_WRITE_SWAPPED_DATA
#endif

/* CPLD */

#define CONFIG_SYS_CPLD_BASE	0x7fb00000
#define CPLD_BASE_PHYS		CONFIG_SYS_CPLD_BASE

#define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_NOR_MODE_AVD_NOR | \
					CSOR_NOR_TRHZ_80)

/* CPLD Timing parameters for IFC GPCM */
#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xf) | \
					FTIM0_GPCM_TEADC(0xf) | \
					FTIM0_GPCM_TEAHC(0xf))
#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0xff))
#define CONFIG_SYS_FPGA_FTIM3           0x0
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_FPGA_FTIM3

/*
 * Serial Port
 */
#ifdef CONFIG_LPUART
#define CONFIG_LPUART_32B_REG
#else
#define CONFIG_SYS_NS16550_SERIAL
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#endif
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
#endif

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */

/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM		1
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5

/*
 * MMC
 */

/* SPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
/* QSPI */
#define QSPI0_AMBA_BASE			0x40000000
#define FSL_QSPI_FLASH_SIZE		(1 << 24)
#define FSL_QSPI_FLASH_NUM		2

/* DSPI */
#endif

/* DM SPI */
#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
#define CONFIG_DM_SPI_FLASH
#endif

/*
 * Video
 */
#ifdef CONFIG_VIDEO_FSL_DCU_FB
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO

#define CONFIG_FSL_DCU_SII9022A
#define CONFIG_SYS_I2C_DVI_BUS_NUM	1
#define CONFIG_SYS_I2C_DVI_ADDR		0x39
#endif

/*
 * eTSEC
 */

#ifdef CONFIG_TSEC_ENET
#define CONFIG_MII
#define CONFIG_MII_DEFAULT_TSEC		1
#define CONFIG_TSEC1			1
#define CONFIG_TSEC1_NAME		"eTSEC1"
#define CONFIG_TSEC2			1
#define CONFIG_TSEC2_NAME		"eTSEC2"
#define CONFIG_TSEC3			1
#define CONFIG_TSEC3_NAME		"eTSEC3"

#define TSEC1_PHY_ADDR			2
#define TSEC2_PHY_ADDR			0
#define TSEC3_PHY_ADDR			1

#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX			0
#define TSEC2_PHYIDX			0
#define TSEC3_PHYIDX			0

#define CONFIG_ETHPRIME			"eTSEC1"

#define CONFIG_PHY_ATHEROS

#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#endif

/* PCIe */
#define CONFIG_PCIE1		/* PCIE controller 1 */
#define CONFIG_PCIE2		/* PCIE controller 2 */

#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif

#define CONFIG_CMDLINE_TAG

#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR		0x01ee0200
#define COUNTER_FREQUENCY		12500000

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		256

#define CONFIG_FSL_DEVICE_DISABLE

#define BOOT_TARGET_DEVICES(func) \
	func(MMC, mmc, 0) \
	func(USB, usb, 0)
#include <config_distro_bootcmd.h>

#ifdef CONFIG_LPUART
#define CONFIG_EXTRA_ENV_SETTINGS       \
	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
	"initrd_high=0xffffffff\0"      \
	"fdt_high=0xffffffff\0"		\
	"fdt_addr=0x64f00000\0"		\
	"kernel_addr=0x65000000\0"	\
	"scriptaddr=0x80000000\0"	\
	"scripthdraddr=0x80080000\0"	\
	"fdtheader_addr_r=0x80100000\0"	\
	"kernelheader_addr_r=0x80200000\0"	\
	"kernel_addr_r=0x81000000\0"	\
	"fdt_addr_r=0x90000000\0"	\
	"ramdisk_addr_r=0xa0000000\0"	\
	"load_addr=0xa0000000\0"	\
	"kernel_size=0x2800000\0"	\
	"kernel_addr_sd=0x8000\0"	\
	"kernel_size_sd=0x14000\0"	\
	BOOTENV				\
	"boot_scripts=ls1021atwr_boot.scr\0"	\
	"boot_script_hdr=hdr_ls1021atwr_bs.out\0"	\
		"scan_dev_for_boot_part="	\
			"part list ${devtype} ${devnum} devplist; "	\
			"env exists devplist || setenv devplist 1; "	\
			"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "				\
				"${devnum}:${distro_bootpart} "		\
				"bootfstype; then "			\
				"run scan_dev_for_boot; "		\
			"fi; "			\
		"done\0"			\
	"scan_dev_for_boot="				  \
		"echo Scanning ${devtype} "		  \
				"${devnum}:${distro_bootpart}...; "  \
		"for prefix in ${boot_prefixes}; do "	  \
			"run scan_dev_for_scripts; "	  \
		"done;"					  \
		"\0"					  \
	"boot_a_script="				  \
		"load ${devtype} ${devnum}:${distro_bootpart} "  \
			"${scriptaddr} ${prefix}${script}; "    \
		"env exists secureboot && load ${devtype} "     \
			"${devnum}:${distro_bootpart} "		\
			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
			"&& esbc_validate ${scripthdraddr};"    \
		"source ${scriptaddr}\0"	  \
	"installer=load mmc 0:2 $load_addr "	\
		"/flex_installer_arm32.itb; "		\
		"bootm $load_addr#ls1021atwr\0"	\
	"qspi_bootcmd=echo Trying load from qspi..;"	\
		"sf probe && sf read $load_addr "	\
		"$kernel_addr $kernel_size && bootm $load_addr#$board\0"	\
	"nor_bootcmd=echo Trying load from nor..;"	\
		"cp.b $kernel_addr $load_addr "		\
		"$kernel_size && bootm $load_addr#$board\0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS	\
	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
	"initrd_high=0xffffffff\0"      \
	"fdt_high=0xffffffff\0"		\
	"fdt_addr=0x64f00000\0"		\
	"kernel_addr=0x61000000\0"	\
	"kernelheader_addr=0x60800000\0"	\
	"scriptaddr=0x80000000\0"	\
	"scripthdraddr=0x80080000\0"	\
	"fdtheader_addr_r=0x80100000\0"	\
	"kernelheader_addr_r=0x80200000\0"	\
	"kernel_addr_r=0x81000000\0"	\
	"kernelheader_size=0x40000\0"	\
	"fdt_addr_r=0x90000000\0"	\
	"ramdisk_addr_r=0xa0000000\0"	\
	"load_addr=0xa0000000\0"	\
	"kernel_size=0x2800000\0"	\
	"kernel_addr_sd=0x8000\0"	\
	"kernel_size_sd=0x14000\0"	\
	"kernelhdr_addr_sd=0x4000\0"		\
	"kernelhdr_size_sd=0x10\0"		\
	BOOTENV				\
	"boot_scripts=ls1021atwr_boot.scr\0"	\
	"boot_script_hdr=hdr_ls1021atwr_bs.out\0"	\
		"scan_dev_for_boot_part="	\
			"part list ${devtype} ${devnum} devplist; "	\
			"env exists devplist || setenv devplist 1; "	\
			"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "				\
				"${devnum}:${distro_bootpart} "		\
				"bootfstype; then "			\
				"run scan_dev_for_boot; "		\
			"fi; "			\
		"done\0"			\
	"scan_dev_for_boot="				  \
		"echo Scanning ${devtype} "		  \
				"${devnum}:${distro_bootpart}...; "  \
		"for prefix in ${boot_prefixes}; do "	  \
			"run scan_dev_for_scripts; "	  \
		"done;"					  \
		"\0"					  \
	"boot_a_script="				  \
		"load ${devtype} ${devnum}:${distro_bootpart} "  \
			"${scriptaddr} ${prefix}${script}; "    \
		"env exists secureboot && load ${devtype} "     \
			"${devnum}:${distro_bootpart} "		\
			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
			"&& esbc_validate ${scripthdraddr};"    \
		"source ${scriptaddr}\0"	  \
	"qspi_bootcmd=echo Trying load from qspi..;"	\
		"sf probe && sf read $load_addr "	\
		"$kernel_addr $kernel_size; env exists secureboot "	\
		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
		"bootm $load_addr#$board\0" \
	"nor_bootcmd=echo Trying load from nor..;"	\
		"cp.b $kernel_addr $load_addr "		\
		"$kernel_size; env exists secureboot "	\
		"&& cp.b $kernelheader_addr $kernelheader_addr_r "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
		"bootm $load_addr#$board\0"	\
	"sd_bootcmd=echo Trying load from SD ..;"       \
		"mmcinfo && mmc read $load_addr "	\
		"$kernel_addr_sd $kernel_size_sd && "	\
		"env exists secureboot && mmc read $kernelheader_addr_r "		\
		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
		" && esbc_validate ${kernelheader_addr_r};"	\
		"bootm $load_addr#$board\0"
#endif

#undef CONFIG_BOOTCOMMAND
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd"	\
			   "env exists secureboot && esbc_halt"
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "	\
			   "env exists secureboot && esbc_halt;"
#else
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;"	\
			   "env exists secureboot && esbc_halt;"
#endif

/*
 * Miscellaneous configurable options
 */

#define CONFIG_SYS_MEMTEST_START	0x80000000
#define CONFIG_SYS_MEMTEST_END		0x9fffffff

#define CONFIG_SYS_LOAD_ADDR		0x82000000

#define CONFIG_LS102XA_STREAM_ID

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
#endif

#define CONFIG_SYS_QE_FW_ADDR     0x60940000

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET		0x300000
#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_ENV_SIZE			0x20000
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_ENV_OFFSET		0x300000
#define CONFIG_ENV_SECT_SIZE		0x10000
#else
#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SIZE			0x20000
#define CONFIG_ENV_SECT_SIZE		0x20000 /* 128K (one sector) */
#endif

#define CONFIG_MISC_INIT_R

#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
c8a7d9da WH	2	/*
c8a7d9da WH	3	* Copyright 2014 Freescale Semiconductor, Inc.
c8a7d9da WH	4	*/
	5
	6	#ifndef __CONFIG_H
	7	#define __CONFIG_H
	8
aeb901f2	9	#define CONFIG_ARMV7_PSCI_1_0
340848b1	10
3288628a HZ	11	#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
3288628a HZ	12
18fb0e3c	13	#define CONFIG_SYS_FSL_CLK
c8a7d9da	14
c8a7d9da	15	#define CONFIG_SKIP_LOWLEVEL_INIT
99e1bd42	16	#define CONFIG_DEEP_SLEEP
c8a7d9da WH	17
	18	/*
	19	* Size of malloc() pool
	20	*/
	21	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
	22
	23	#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
	24	#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
	25
c8a7d9da WH	26	#define CONFIG_SYS_CLK_FREQ 100000000
	27	#define CONFIG_DDR_CLK_FREQ 100000000
	28
a88cc3bd YS	29	#define DDR_SDRAM_CFG 0x470c0008
	30	#define DDR_CS0_BNDS 0x008000bf
	31	#define DDR_CS0_CONFIG 0x80014302
	32	#define DDR_TIMING_CFG_0 0x50550004
	33	#define DDR_TIMING_CFG_1 0xbcb38c56
	34	#define DDR_TIMING_CFG_2 0x0040d120
	35	#define DDR_TIMING_CFG_3 0x010e1000
	36	#define DDR_TIMING_CFG_4 0x00000001
	37	#define DDR_TIMING_CFG_5 0x03401400
	38	#define DDR_SDRAM_CFG_2 0x00401010
	39	#define DDR_SDRAM_MODE 0x00061c60
	40	#define DDR_SDRAM_MODE_2 0x00180000
	41	#define DDR_SDRAM_INTERVAL 0x18600618
	42	#define DDR_DDR_WRLVL_CNTL 0x8655f605
	43	#define DDR_DDR_WRLVL_CNTL_2 0x05060607
	44	#define DDR_DDR_WRLVL_CNTL_3 0x05050505
	45	#define DDR_DDR_CDR1 0x80040000
	46	#define DDR_DDR_CDR2 0x00000001
	47	#define DDR_SDRAM_CLK_CNTL 0x02000000
	48	#define DDR_DDR_ZQ_CNTL 0x89080600
	49	#define DDR_CS0_CONFIG_2 0
	50	#define DDR_SDRAM_CFG_MEM_EN 0x80000000
99e1bd42 TY	51	#define SDRAM_CFG2_D_INIT 0x00000010
	52	#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
	53	#define SDRAM_CFG2_FRC_SR 0x80000000
	54	#define SDRAM_CFG_BI 0x00000001
a88cc3bd	55
8415bb68 AW	56	#ifdef CONFIG_RAMBOOT_PBL
	57	#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
	58	#endif
	59
	60	#ifdef CONFIG_SD_BOOT
947cee11 AW	61	#ifdef CONFIG_SD_BOOT_QSPI
	62	#define CONFIG_SYS_FSL_PBL_RCW \
	63	board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
	64	#else
	65	#define CONFIG_SYS_FSL_PBL_RCW \
	66	board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
	67	#endif
e7e720c2 SG	68
e7e720c2 SG	69	#ifdef CONFIG_SECURE_BOOT
e7e720c2 SG	70	/*
	71	* HDR would be appended at end of image and copied to DDR along
	72	* with U-Boot image.
	73	*/
693d4c9f	74	#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
e7e720c2	75	#endif /* ifdef CONFIG_SECURE_BOOT */
8415bb68 AW	76
	77	#define CONFIG_SPL_TEXT_BASE 0x10000000
	78	#define CONFIG_SPL_MAX_SIZE 0x1a000
	79	#define CONFIG_SPL_STACK 0x1001d000
	80	#define CONFIG_SPL_PAD_TO 0x1c000
8415bb68	81
99e1bd42 TY	82	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
99e1bd42 TY	83	CONFIG_SYS_MONITOR_LEN)
8415bb68 AW	84	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	85	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	86	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
e7e720c2 SG	87
	88	#ifdef CONFIG_U_BOOT_HDR_SIZE
	89	/*
	90	* HDR would be appended at end of image and copied to DDR along
	91	* with U-Boot image. Here u-boot max. size is 512K. So if binary
	92	* size increases then increase this size in case of secure boot as
	93	* it uses raw u-boot image instead of fit image.
	94	*/
9b6639fa	95	#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
e7e720c2	96	#else
9b6639fa	97	#define CONFIG_SYS_MONITOR_LEN 0x100000
e7e720c2	98	#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
8415bb68 AW	99	#endif
8415bb68 AW	100
c8a7d9da WH	101	#define CONFIG_NR_DRAM_BANKS 1
	102	#define PHYS_SDRAM 0x80000000
	103	#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
	104
	105	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
	106	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	107
4c59ab9c AW	108	#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
4c59ab9c AW	109	!defined(CONFIG_QSPI_BOOT)
eaa859e7	110	#define CONFIG_U_QE
5aa03ddd	111	#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
eaa859e7 ZQ	112	#endif
eaa859e7 ZQ	113
c8a7d9da WH	114	/*
	115	* IFC Definitions
	116	*/
947cee11	117	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
c8a7d9da WH	118	#define CONFIG_FSL_IFC
	119	#define CONFIG_SYS_FLASH_BASE 0x60000000
	120	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	121
	122	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	123	#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	124	CSPR_PORT_SIZE_16 \| \
	125	CSPR_MSEL_NOR \| \
	126	CSPR_V)
	127	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
	128
	129	/* NOR Flash Timing Params */
	130	#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	131	CSOR_NOR_TRHZ_80)
	132	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	133	FTIM0_NOR_TEADC(0x5) \| \
	134	FTIM0_NOR_TAVDS(0x0) \| \
	135	FTIM0_NOR_TEAHC(0x5))
	136	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	137	FTIM1_NOR_TRAD_NOR(0x1A) \| \
	138	FTIM1_NOR_TSEQRAD_NOR(0x13))
	139	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	140	FTIM2_NOR_TCH(0x4) \| \
	141	FTIM2_NOR_TWP(0x1c) \| \
	142	FTIM2_NOR_TWPH(0x0e))
	143	#define CONFIG_SYS_NOR_FTIM3 0
	144
	145	#define CONFIG_FLASH_CFI_DRIVER
	146	#define CONFIG_SYS_FLASH_CFI
	147	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	148	#define CONFIG_SYS_FLASH_QUIET_TEST
	149	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	150
	151	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	152	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	153	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	154	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	155
	156	#define CONFIG_SYS_FLASH_EMPTY_INFO
	157	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
	158
	159	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
272c5265	160	#define CONFIG_SYS_WRITE_SWAPPED_DATA
d612f0ab	161	#endif
c8a7d9da WH	162
	163	/* CPLD */
	164
	165	#define CONFIG_SYS_CPLD_BASE 0x7fb00000
	166	#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
	167
	168	#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
	169	#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) \| \
	170	CSPR_PORT_SIZE_8 \| \
	171	CSPR_MSEL_GPCM \| \
	172	CSPR_V)
	173	#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
	174	#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	175	CSOR_NOR_NOR_MODE_AVD_NOR \| \
	176	CSOR_NOR_TRHZ_80)
	177
	178	/* CPLD Timing parameters for IFC GPCM */
	179	#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) \| \
	180	FTIM0_GPCM_TEADC(0xf) \| \
	181	FTIM0_GPCM_TEAHC(0xf))
	182	#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	183	FTIM1_GPCM_TRAD(0x3f))
	184	#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
	185	FTIM2_GPCM_TCH(0xf) \| \
	186	FTIM2_GPCM_TWP(0xff))
	187	#define CONFIG_SYS_FPGA_FTIM3 0x0
	188	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	189	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
	190	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	191	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	192	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	193	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	194	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	195	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	196	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
	197	#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
	198	#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
	199	#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
	200	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
	201	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
	202	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
	203	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
	204
	205	/*
	206	* Serial Port
	207	*/
55d53ab4	208	#ifdef CONFIG_LPUART
55d53ab4 AW	209	#define CONFIG_LPUART_32B_REG
55d53ab4 AW	210	#else
c8a7d9da	211	#define CONFIG_SYS_NS16550_SERIAL
f833cd62	212	#ifndef CONFIG_DM_SERIAL
c8a7d9da	213	#define CONFIG_SYS_NS16550_REG_SIZE 1
f833cd62	214	#endif
c8a7d9da	215	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
55d53ab4	216	#endif
c8a7d9da	217
c8a7d9da WH	218	/*
	219	* I2C
	220	*/
c8a7d9da WH	221	#define CONFIG_SYS_I2C
c8a7d9da WH	222	#define CONFIG_SYS_I2C_MXC
03544c66 AA	223	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	224	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e	225	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
c8a7d9da	226
5175a288	227	/* EEPROM */
5175a288 AW	228	#define CONFIG_ID_EEPROM
	229	#define CONFIG_SYS_I2C_EEPROM_NXID
	230	#define CONFIG_SYS_EEPROM_BUS_NUM 1
	231	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
	232	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	233	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	234	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
5175a288	235
c8a7d9da WH	236	/*
	237	* MMC
	238	*/
c8a7d9da	239
9dd3d3c0	240	/* SPI */
947cee11	241	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
9dd3d3c0	242	/* QSPI */
d612f0ab AW	243	#define QSPI0_AMBA_BASE 0x40000000
	244	#define FSL_QSPI_FLASH_SIZE (1 << 24)
	245	#define FSL_QSPI_FLASH_NUM 2
	246
03d1d568	247	/* DSPI */
03d1d568 YY	248	#endif
03d1d568 YY	249
9dd3d3c0 HW	250	/* DM SPI */
9dd3d3c0 HW	251	#if defined(CONFIG_FSL_DSPI) \|\| defined(CONFIG_FSL_QSPI)
9dd3d3c0 HW	252	#define CONFIG_DM_SPI_FLASH
9dd3d3c0 HW	253	#endif
d612f0ab	254
b4ecc8c6 WH	255	/*
	256	* Video
	257	*/
b215fb3f	258	#ifdef CONFIG_VIDEO_FSL_DCU_FB
b4ecc8c6 WH	259	#define CONFIG_VIDEO_LOGO
	260	#define CONFIG_VIDEO_BMP_LOGO
	261
	262	#define CONFIG_FSL_DCU_SII9022A
	263	#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
	264	#define CONFIG_SYS_I2C_DVI_ADDR 0x39
	265	#endif
	266
c8a7d9da WH	267	/*
	268	* eTSEC
	269	*/
c8a7d9da WH	270
	271	#ifdef CONFIG_TSEC_ENET
	272	#define CONFIG_MII
	273	#define CONFIG_MII_DEFAULT_TSEC 1
	274	#define CONFIG_TSEC1 1
	275	#define CONFIG_TSEC1_NAME "eTSEC1"
	276	#define CONFIG_TSEC2 1
	277	#define CONFIG_TSEC2_NAME "eTSEC2"
	278	#define CONFIG_TSEC3 1
	279	#define CONFIG_TSEC3_NAME "eTSEC3"
	280
	281	#define TSEC1_PHY_ADDR 2
	282	#define TSEC2_PHY_ADDR 0
	283	#define TSEC3_PHY_ADDR 1
	284
	285	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	286	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	287	#define TSEC3_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	288
	289	#define TSEC1_PHYIDX 0
	290	#define TSEC2_PHYIDX 0
	291	#define TSEC3_PHYIDX 0
	292
	293	#define CONFIG_ETHPRIME "eTSEC1"
	294
c8a7d9da WH	295	#define CONFIG_PHY_ATHEROS
	296
	297	#define CONFIG_HAS_ETH0
	298	#define CONFIG_HAS_ETH1
	299	#define CONFIG_HAS_ETH2
	300	#endif
	301
da419027	302	/* PCIe */
b38eaec5 RD	303	#define CONFIG_PCIE1 /* PCIE controller 1 */
b38eaec5 RD	304	#define CONFIG_PCIE2 /* PCIE controller 2 */
da419027	305
180b8688	306	#ifdef CONFIG_PCI
180b8688	307	#define CONFIG_PCI_SCAN_SHOW
180b8688 ML	308	#endif
180b8688 ML	309
c8a7d9da	310	#define CONFIG_CMDLINE_TAG
8415bb68	311
1a2826f6	312	#define CONFIG_PEN_ADDR_BIG_ENDIAN
435acd83	313	#define CONFIG_LAYERSCAPE_NS_ACCESS
1a2826f6	314	#define CONFIG_SMP_PEN_ADDR 0x01ee0200
e4916e85	315	#define COUNTER_FREQUENCY 12500000
1a2826f6	316
c8a7d9da	317	#define CONFIG_HWCONFIG
03c22449 ZZ	318	#define HWCONFIG_BUFFER_SIZE 256
	319
	320	#define CONFIG_FSL_DEVICE_DISABLE
c8a7d9da	321
a65d7408 AW	322	#define BOOT_TARGET_DEVICES(func) \
	323	func(MMC, mmc, 0) \
	324	func(USB, usb, 0)
	325	#include <config_distro_bootcmd.h>
c8a7d9da	326
55d53ab4 AW	327	#ifdef CONFIG_LPUART
	328	#define CONFIG_EXTRA_ENV_SETTINGS \
	329	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
7ff7166c	330	"initrd_high=0xffffffff\0" \
a65d7408 AW	331	"fdt_high=0xffffffff\0" \
	332	"fdt_addr=0x64f00000\0" \
	333	"kernel_addr=0x65000000\0" \
	334	"scriptaddr=0x80000000\0" \
b8ae6798	335	"scripthdraddr=0x80080000\0" \
a65d7408 AW	336	"fdtheader_addr_r=0x80100000\0" \
	337	"kernelheader_addr_r=0x80200000\0" \
	338	"kernel_addr_r=0x81000000\0" \
	339	"fdt_addr_r=0x90000000\0" \
	340	"ramdisk_addr_r=0xa0000000\0" \
	341	"load_addr=0xa0000000\0" \
	342	"kernel_size=0x2800000\0" \
397a173e SL	343	"kernel_addr_sd=0x8000\0" \
397a173e SL	344	"kernel_size_sd=0x14000\0" \
a65d7408 AW	345	BOOTENV \
a65d7408 AW	346	"boot_scripts=ls1021atwr_boot.scr\0" \
b8ae6798	347	"boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
a65d7408 AW	348	"scan_dev_for_boot_part=" \
	349	"part list ${devtype} ${devnum} devplist; " \
	350	"env exists devplist \|\| setenv devplist 1; " \
	351	"for distro_bootpart in ${devplist}; do " \
	352	"if fstype ${devtype} " \
	353	"${devnum}:${distro_bootpart} " \
	354	"bootfstype; then " \
	355	"run scan_dev_for_boot; " \
	356	"fi; " \
	357	"done\0" \
b8ae6798 SG	358	"scan_dev_for_boot=" \
	359	"echo Scanning ${devtype} " \
	360	"${devnum}:${distro_bootpart}...; " \
	361	"for prefix in ${boot_prefixes}; do " \
	362	"run scan_dev_for_scripts; " \
	363	"done;" \
	364	"\0" \
	365	"boot_a_script=" \
	366	"load ${devtype} ${devnum}:${distro_bootpart} " \
	367	"${scriptaddr} ${prefix}${script}; " \
	368	"env exists secureboot && load ${devtype} " \
	369	"${devnum}:${distro_bootpart} " \
	370	"${scripthdraddr} ${prefix}${boot_script_hdr} " \
	371	"&& esbc_validate ${scripthdraddr};" \
	372	"source ${scriptaddr}\0" \
a65d7408 AW	373	"installer=load mmc 0:2 $load_addr " \
	374	"/flex_installer_arm32.itb; " \
	375	"bootm $load_addr#ls1021atwr\0" \
	376	"qspi_bootcmd=echo Trying load from qspi..;" \
	377	"sf probe && sf read $load_addr " \
	378	"$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
	379	"nor_bootcmd=echo Trying load from nor..;" \
	380	"cp.b $kernel_addr $load_addr " \
	381	"$kernel_size && bootm $load_addr#$board\0"
55d53ab4	382	#else
c8a7d9da WH	383	#define CONFIG_EXTRA_ENV_SETTINGS \
c8a7d9da WH	384	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
7ff7166c	385	"initrd_high=0xffffffff\0" \
a65d7408 AW	386	"fdt_high=0xffffffff\0" \
a65d7408 AW	387	"fdt_addr=0x64f00000\0" \
9b457cc6 VPB	388	"kernel_addr=0x61000000\0" \
9b457cc6 VPB	389	"kernelheader_addr=0x60800000\0" \
a65d7408	390	"scriptaddr=0x80000000\0" \
b8ae6798	391	"scripthdraddr=0x80080000\0" \
a65d7408 AW	392	"fdtheader_addr_r=0x80100000\0" \
	393	"kernelheader_addr_r=0x80200000\0" \
	394	"kernel_addr_r=0x81000000\0" \
9b457cc6	395	"kernelheader_size=0x40000\0" \
a65d7408 AW	396	"fdt_addr_r=0x90000000\0" \
	397	"ramdisk_addr_r=0xa0000000\0" \
	398	"load_addr=0xa0000000\0" \
	399	"kernel_size=0x2800000\0" \
9b457cc6 VPB	400	"kernel_addr_sd=0x8000\0" \
	401	"kernel_size_sd=0x14000\0" \
	402	"kernelhdr_addr_sd=0x4000\0" \
	403	"kernelhdr_size_sd=0x10\0" \
a65d7408 AW	404	BOOTENV \
a65d7408 AW	405	"boot_scripts=ls1021atwr_boot.scr\0" \
b8ae6798	406	"boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
a65d7408 AW	407	"scan_dev_for_boot_part=" \
	408	"part list ${devtype} ${devnum} devplist; " \
	409	"env exists devplist \|\| setenv devplist 1; " \
	410	"for distro_bootpart in ${devplist}; do " \
	411	"if fstype ${devtype} " \
	412	"${devnum}:${distro_bootpart} " \
	413	"bootfstype; then " \
	414	"run scan_dev_for_boot; " \
	415	"fi; " \
	416	"done\0" \
b8ae6798 SG	417	"scan_dev_for_boot=" \
	418	"echo Scanning ${devtype} " \
	419	"${devnum}:${distro_bootpart}...; " \
	420	"for prefix in ${boot_prefixes}; do " \
	421	"run scan_dev_for_scripts; " \
	422	"done;" \
	423	"\0" \
	424	"boot_a_script=" \
	425	"load ${devtype} ${devnum}:${distro_bootpart} " \
	426	"${scriptaddr} ${prefix}${script}; " \
	427	"env exists secureboot && load ${devtype} " \
	428	"${devnum}:${distro_bootpart} " \
	429	"${scripthdraddr} ${prefix}${boot_script_hdr} " \
	430	"&& esbc_validate ${scripthdraddr};" \
	431	"source ${scriptaddr}\0" \
a65d7408 AW	432	"qspi_bootcmd=echo Trying load from qspi..;" \
a65d7408 AW	433	"sf probe && sf read $load_addr " \
9b457cc6 VPB	434	"$kernel_addr $kernel_size; env exists secureboot " \
	435	"&& sf read $kernelheader_addr_r $kernelheader_addr " \
	436	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
	437	"bootm $load_addr#$board\0" \
a65d7408 AW	438	"nor_bootcmd=echo Trying load from nor..;" \
a65d7408 AW	439	"cp.b $kernel_addr $load_addr " \
9b457cc6 VPB	440	"$kernel_size; env exists secureboot " \
	441	"&& cp.b $kernelheader_addr $kernelheader_addr_r " \
	442	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
	443	"bootm $load_addr#$board\0" \
397a173e SL	444	"sd_bootcmd=echo Trying load from SD ..;" \
	445	"mmcinfo && mmc read $load_addr " \
	446	"$kernel_addr_sd $kernel_size_sd && " \
9b457cc6 VPB	447	"env exists secureboot && mmc read $kernelheader_addr_r " \
	448	"$kernelhdr_addr_sd $kernelhdr_size_sd " \
	449	" && esbc_validate ${kernelheader_addr_r};" \
397a173e	450	"bootm $load_addr#$board\0"
55d53ab4	451	#endif
c8a7d9da	452
a65d7408 AW	453	#undef CONFIG_BOOTCOMMAND
a65d7408 AW	454	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
9b457cc6 VPB	455	#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd" \
9b457cc6 VPB	456	"env exists secureboot && esbc_halt"
397a173e	457	#elif defined(CONFIG_SD_BOOT)
9b457cc6 VPB	458	#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
9b457cc6 VPB	459	"env exists secureboot && esbc_halt;"
a65d7408	460	#else
9b457cc6 VPB	461	#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \
9b457cc6 VPB	462	"env exists secureboot && esbc_halt;"
a65d7408 AW	463	#endif
a65d7408 AW	464
c8a7d9da WH	465	/*
	466	* Miscellaneous configurable options
	467	*/
c8a7d9da	468
c8a7d9da WH	469	#define CONFIG_SYS_MEMTEST_START 0x80000000
	470	#define CONFIG_SYS_MEMTEST_END 0x9fffffff
	471
	472	#define CONFIG_SYS_LOAD_ADDR 0x82000000
c8a7d9da	473
660673af XL	474	#define CONFIG_LS102XA_STREAM_ID
660673af XL	475
c8a7d9da WH	476	#define CONFIG_SYS_INIT_SP_OFFSET \
	477	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	478	#define CONFIG_SYS_INIT_SP_ADDR \
	479	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	480
8415bb68 AW	481	#ifdef CONFIG_SPL_BUILD
	482	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	483	#else
c8a7d9da	484	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
8415bb68	485	#endif
c8a7d9da	486
615bfce5	487	#define CONFIG_SYS_QE_FW_ADDR 0x60940000
eaa859e7	488
c8a7d9da WH	489	/*
	490	* Environment
	491	*/
	492	#define CONFIG_ENV_OVERWRITE
	493
8415bb68	494	#if defined(CONFIG_SD_BOOT)
615bfce5	495	#define CONFIG_ENV_OFFSET 0x300000
8415bb68 AW	496	#define CONFIG_SYS_MMC_ENV_DEV 0
8415bb68 AW	497	#define CONFIG_ENV_SIZE 0x20000
d612f0ab	498	#elif defined(CONFIG_QSPI_BOOT)
d612f0ab	499	#define CONFIG_ENV_SIZE 0x2000
615bfce5	500	#define CONFIG_ENV_OFFSET 0x300000
d612f0ab	501	#define CONFIG_ENV_SECT_SIZE 0x10000
8415bb68	502	#else
615bfce5	503	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
c8a7d9da WH	504	#define CONFIG_ENV_SIZE 0x20000
c8a7d9da WH	505	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
8415bb68	506	#endif
c8a7d9da	507
4ba4a095 RG	508	#define CONFIG_MISC_INIT_R
4ba4a095 RG	509
ef6c55a2	510	#include <asm/fsl_secure_boot.h>
cc7b8b9a	511	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
4ba4a095	512
c8a7d9da	513	#endif