SPDX: Convert all of our single license tags to Linux Kernel style
[u-boot.git] / include / configs / MPC832XEMDS.h
CommitLineData
83d290c5 1/* SPDX-License-Identifier: GPL-2.0+ */
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2/*
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
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4 */
5
6#ifndef __CONFIG_H
7#define __CONFIG_H
8
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9/*
10 * High Level Configuration Options
11 */
12#define CONFIG_E300 1 /* E300 family */
13#define CONFIG_QE 1 /* Has QE */
2c7920af 14#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
24c3aca3 15#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
2ae18241 16
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17/*
18 * System Clock Setup
19 */
20#ifdef CONFIG_PCISLAVE
21#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
22#else
23#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
24#endif
25
26#ifndef CONFIG_SYS_CLK_FREQ
27#define CONFIG_SYS_CLK_FREQ 66000000
28#endif
29
30/*
31 * Hardware Reset Configuration Word
32 */
6d0f6bcf 33#define CONFIG_SYS_HRCW_LOW (\
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34 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
35 HRCWL_DDR_TO_SCB_CLK_2X1 |\
36 HRCWL_VCO_1X2 |\
37 HRCWL_CSB_TO_CLKIN_2X1 |\
38 HRCWL_CORE_TO_CSB_2X1 |\
39 HRCWL_CE_PLL_VCO_DIV_2 |\
40 HRCWL_CE_PLL_DIV_1X1 |\
41 HRCWL_CE_TO_PLL_1X3)
42
43#ifdef CONFIG_PCISLAVE
6d0f6bcf 44#define CONFIG_SYS_HRCW_HIGH (\
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45 HRCWH_PCI_AGENT |\
46 HRCWH_PCI1_ARBITER_DISABLE |\
47 HRCWH_CORE_ENABLE |\
48 HRCWH_FROM_0XFFF00100 |\
49 HRCWH_BOOTSEQ_DISABLE |\
50 HRCWH_SW_WATCHDOG_DISABLE |\
51 HRCWH_ROM_LOC_LOCAL_16BIT |\
52 HRCWH_BIG_ENDIAN |\
53 HRCWH_LALE_NORMAL)
54#else
6d0f6bcf 55#define CONFIG_SYS_HRCW_HIGH (\
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56 HRCWH_PCI_HOST |\
57 HRCWH_PCI1_ARBITER_ENABLE |\
58 HRCWH_CORE_ENABLE |\
59 HRCWH_FROM_0X00000100 |\
60 HRCWH_BOOTSEQ_DISABLE |\
61 HRCWH_SW_WATCHDOG_DISABLE |\
62 HRCWH_ROM_LOC_LOCAL_16BIT |\
63 HRCWH_BIG_ENDIAN |\
64 HRCWH_LALE_NORMAL)
65#endif
66
67/*
68 * System IO Config
69 */
6d0f6bcf 70#define CONFIG_SYS_SICRL 0x00000000
24c3aca3 71
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72/*
73 * IMMR new address
74 */
6d0f6bcf 75#define CONFIG_SYS_IMMR 0xE0000000
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76
77/*
78 * DDR Setup
79 */
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80#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
81#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
6d0f6bcf 82#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
989091ac 83#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
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84
85#undef CONFIG_SPD_EEPROM
86#if defined(CONFIG_SPD_EEPROM)
87/* Determine DDR configuration from I2C interface
88 */
89#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
90#else
91/* Manually set up DDR parameters
92 */
6d0f6bcf 93#define CONFIG_SYS_DDR_SIZE 128 /* MB */
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94#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
95 | CSCONFIG_AP \
96 | CSCONFIG_ODT_WR_CFG \
97 | CSCONFIG_ROW_BIT_13 \
98 | CSCONFIG_COL_BIT_10)
99 /* 0x80840102 */
100#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
101 | (0 << TIMING_CFG0_WRT_SHIFT) \
102 | (0 << TIMING_CFG0_RRT_SHIFT) \
103 | (0 << TIMING_CFG0_WWT_SHIFT) \
104 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
105 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
106 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
107 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
108 /* 0x00220802 */
109#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
110 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
111 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
112 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
113 | (13 << TIMING_CFG1_REFREC_SHIFT) \
114 | (3 << TIMING_CFG1_WRREC_SHIFT) \
115 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
116 | (2 << TIMING_CFG1_WRTORD_SHIFT))
117 /* 0x3935D322 */
118#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
119 | (31 << TIMING_CFG2_CPO_SHIFT) \
120 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
121 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
122 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
123 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
124 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
125 /* 0x0F9048CA */
989091ac 126#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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127#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
128 /* 0x02000000 */
129#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
130 | (0x0232 << SDRAM_MODE_SD_SHIFT))
131 /* 0x44400232 */
6d0f6bcf 132#define CONFIG_SYS_DDR_MODE2 0x8000c000
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133#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
134 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
135 /* 0x03200064 */
989091ac 136#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
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137#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
138 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
139 | SDRAM_CFG_32_BE)
140 /* 0x43080000 */
6d0f6bcf 141#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
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142#endif
143
144/*
145 * Memory test
146 */
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147#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
148#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
149#define CONFIG_SYS_MEMTEST_END 0x00100000
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150
151/*
152 * The reserved memory
153 */
14d0a02a 154#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
24c3aca3 155
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156#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
157#define CONFIG_SYS_RAMBOOT
24c3aca3 158#else
6d0f6bcf 159#undef CONFIG_SYS_RAMBOOT
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160#endif
161
6d0f6bcf 162/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
16c8c170 163#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
3b6b256c 164#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
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165
166/*
167 * Initial RAM Base Address Setup
168 */
6d0f6bcf 169#define CONFIG_SYS_INIT_RAM_LOCK 1
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170#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
171#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
172#define CONFIG_SYS_GBL_DATA_OFFSET \
173 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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174
175/*
176 * Local Bus Configuration & Clock Setup
177 */
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178#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
179#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
6d0f6bcf 180#define CONFIG_SYS_LBC_LBCR 0x00000000
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181
182/*
183 * FLASH on the Local Bus
184 */
6d0f6bcf 185#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
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186#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
187#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
188#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
189#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
24c3aca3 190
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191 /* Window base at flash base */
192#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
7d6a0982 193#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
24c3aca3 194
989091ac 195#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
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196 | BR_PS_16 /* 16 bit port */ \
197 | BR_MS_GPCM /* MSEL = GPCM */ \
198 | BR_V) /* valid */
199#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
200 | OR_GPCM_XAM \
201 | OR_GPCM_CSNT \
202 | OR_GPCM_ACS_DIV2 \
203 | OR_GPCM_XACS \
204 | OR_GPCM_SCY_15 \
205 | OR_GPCM_TRLX_SET \
206 | OR_GPCM_EHTR_SET \
207 | OR_GPCM_EAD)
208 /* 0xfe006ff7 */
24c3aca3 209
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210#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
211#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
24c3aca3 212
6d0f6bcf 213#undef CONFIG_SYS_FLASH_CHECKSUM
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214
215/*
216 * BCSR on the Local Bus
217 */
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218#define CONFIG_SYS_BCSR 0xF8000000
219 /* Access window base at BCSR base */
220#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
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221#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
222
223#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
224 | BR_PS_8 \
225 | BR_MS_GPCM \
226 | BR_V)
227#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
228 | OR_GPCM_XAM \
229 | OR_GPCM_CSNT \
230 | OR_GPCM_XACS \
231 | OR_GPCM_SCY_15 \
232 | OR_GPCM_TRLX_SET \
233 | OR_GPCM_EHTR_SET \
234 | OR_GPCM_EAD)
235 /* 0xFFFFE9F7 */
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236
237/*
238 * Windows to access PIB via local bus
239 */
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240 /* PIB window base 0xF8008000 */
241#define CONFIG_SYS_PIB_BASE 0xF8008000
242#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
243#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE
244#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
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245
246/*
247 * CS2 on Local Bus, to PIB
248 */
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249#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \
250 | BR_PS_8 \
251 | BR_MS_GPCM \
252 | BR_V)
253 /* 0xF8008801 */
254#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
255 | OR_GPCM_XAM \
256 | OR_GPCM_CSNT \
257 | OR_GPCM_XACS \
258 | OR_GPCM_SCY_15 \
259 | OR_GPCM_TRLX_SET \
260 | OR_GPCM_EHTR_SET \
261 | OR_GPCM_EAD)
262 /* 0xffffe9f7 */
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263
264/*
265 * CS3 on Local Bus, to PIB
266 */
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267#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \
268 CONFIG_SYS_PIB_WINDOW_SIZE) \
269 | BR_PS_8 \
270 | BR_MS_GPCM \
271 | BR_V)
272 /* 0xF8010801 */
273#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
274 | OR_GPCM_XAM \
275 | OR_GPCM_CSNT \
276 | OR_GPCM_XACS \
277 | OR_GPCM_SCY_15 \
278 | OR_GPCM_TRLX_SET \
279 | OR_GPCM_EHTR_SET \
280 | OR_GPCM_EAD)
281 /* 0xffffe9f7 */
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282
283/*
284 * Serial Port
285 */
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286#define CONFIG_SYS_NS16550_SERIAL
287#define CONFIG_SYS_NS16550_REG_SIZE 1
288#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
24c3aca3 289
6d0f6bcf 290#define CONFIG_SYS_BAUDRATE_TABLE \
989091ac 291 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
24c3aca3 292
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293#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
294#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
24c3aca3 295
24c3aca3 296/* I2C */
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297#define CONFIG_SYS_I2C
298#define CONFIG_SYS_I2C_FSL
299#define CONFIG_SYS_FSL_I2C_SPEED 400000
300#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
301#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
302#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
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303
304/*
305 * Config on-board RTC
306 */
307#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
6d0f6bcf 308#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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309
310/*
311 * General PCI
312 * Addresses are mapped 1-1.
313 */
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314#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
315#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
316#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
317#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
318#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
319#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
320#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
321#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
322#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
24c3aca3 323
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324#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
325#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
326#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
24c3aca3 327
24c3aca3 328#ifdef CONFIG_PCI
842033e6 329#define CONFIG_PCI_INDIRECT_BRIDGE
24c3aca3 330
9993e196 331#define CONFIG_83XX_PCI_STREAMING
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332
333#undef CONFIG_EEPRO100
334#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf 335#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
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336
337#endif /* CONFIG_PCI */
338
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339/*
340 * QE UEC ethernet configuration
341 */
342#define CONFIG_UEC_ETH
78b7a8ef 343#define CONFIG_ETHPRIME "UEC0"
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344
345#define CONFIG_UEC_ETH1 /* ETH3 */
346
347#ifdef CONFIG_UEC_ETH1
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348#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
349#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
350#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
351#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
352#define CONFIG_SYS_UEC1_PHY_ADDR 3
865ff856 353#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
582c55a0 354#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
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355#endif
356
357#define CONFIG_UEC_ETH2 /* ETH4 */
358
359#ifdef CONFIG_UEC_ETH2
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360#define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */
361#define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
362#define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
363#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
364#define CONFIG_SYS_UEC2_PHY_ADDR 4
865ff856 365#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
582c55a0 366#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
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367#endif
368
369/*
370 * Environment
371 */
6d0f6bcf 372#ifndef CONFIG_SYS_RAMBOOT
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373 #define CONFIG_ENV_ADDR \
374 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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375 #define CONFIG_ENV_SECT_SIZE 0x20000
376 #define CONFIG_ENV_SIZE 0x2000
24c3aca3 377#else
6d0f6bcf 378 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
0e8d1586 379 #define CONFIG_ENV_SIZE 0x2000
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380#endif
381
382#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf 383#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
24c3aca3 384
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385/*
386 * BOOTP options
387 */
388#define CONFIG_BOOTP_BOOTFILESIZE
079a136c 389
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390/*
391 * Command line configuration.
392 */
8ea5499a 393
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394#undef CONFIG_WATCHDOG /* watchdog disabled */
395
396/*
397 * Miscellaneous configurable options
398 */
989091ac 399#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
24c3aca3 400
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401/*
402 * For booting Linux, the board info and command line data
9f530d59 403 * have to be in the first 256 MB of memory, since this is
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404 * the maximum mapped by the Linux kernel during initialization.
405 */
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406 /* Initial Memory map for Linux */
407#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
63865278 408#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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409
410/*
411 * Core HID Setup
412 */
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413#define CONFIG_SYS_HID0_INIT 0x000000000
414#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
415 HID0_ENABLE_INSTRUCTION_CACHE)
6d0f6bcf 416#define CONFIG_SYS_HID2 HID2_HBE
24c3aca3 417
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418/*
419 * MMU Setup
420 */
421
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422#define CONFIG_HIGH_BATS 1 /* High BATs supported */
423
24c3aca3 424/* DDR: cache cacheable */
989091ac 425#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
72cd4087 426 | BATL_PP_RW \
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427 | BATL_MEMCOHERENCE)
428#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
429 | BATU_BL_256M \
430 | BATU_VS \
431 | BATU_VP)
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432#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
433#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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434
435/* IMMRBAR & PCI IO: cache-inhibit and guarded */
989091ac 436#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
72cd4087 437 | BATL_PP_RW \
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438 | BATL_CACHEINHIBIT \
439 | BATL_GUARDEDSTORAGE)
440#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
441 | BATU_BL_4M \
442 | BATU_VS \
443 | BATU_VP)
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444#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
445#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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446
447/* BCSR: cache-inhibit and guarded */
989091ac 448#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
72cd4087 449 | BATL_PP_RW \
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450 | BATL_CACHEINHIBIT \
451 | BATL_GUARDEDSTORAGE)
452#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
453 | BATU_BL_128K \
454 | BATU_VS \
455 | BATU_VP)
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456#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
457#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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458
459/* FLASH: icache cacheable, but dcache-inhibit and guarded */
989091ac 460#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
72cd4087 461 | BATL_PP_RW \
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462 | BATL_MEMCOHERENCE)
463#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
464 | BATU_BL_32M \
465 | BATU_VS \
466 | BATU_VP)
467#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
72cd4087 468 | BATL_PP_RW \
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469 | BATL_CACHEINHIBIT \
470 | BATL_GUARDEDSTORAGE)
6d0f6bcf 471#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
24c3aca3 472
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473#define CONFIG_SYS_IBAT4L (0)
474#define CONFIG_SYS_IBAT4U (0)
475#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
476#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
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477
478/* Stack in dcache: cacheable, no memory coherence */
72cd4087 479#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
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480#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
481 | BATU_BL_128K \
482 | BATU_VS \
483 | BATU_VP)
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484#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
485#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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486
487#ifdef CONFIG_PCI
488/* PCI MEM space: cacheable */
989091ac 489#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
72cd4087 490 | BATL_PP_RW \
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491 | BATL_MEMCOHERENCE)
492#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
493 | BATU_BL_256M \
494 | BATU_VS \
495 | BATU_VP)
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496#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
497#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
24c3aca3 498/* PCI MMIO space: cache-inhibit and guarded */
989091ac 499#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
72cd4087 500 | BATL_PP_RW \
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501 | BATL_CACHEINHIBIT \
502 | BATL_GUARDEDSTORAGE)
503#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
504 | BATU_BL_256M \
505 | BATU_VS \
506 | BATU_VP)
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507#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
508#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
24c3aca3 509#else
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510#define CONFIG_SYS_IBAT6L (0)
511#define CONFIG_SYS_IBAT6U (0)
512#define CONFIG_SYS_IBAT7L (0)
513#define CONFIG_SYS_IBAT7U (0)
514#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
515#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
516#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
517#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
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518#endif
519
8ea5499a 520#if defined(CONFIG_CMD_KGDB)
24c3aca3 521#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
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522#endif
523
524/*
525 * Environment Configuration
9993e196 526 */ #define CONFIG_ENV_OVERWRITE
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527
528#if defined(CONFIG_UEC_ETH)
977b5758 529#define CONFIG_HAS_ETH0
24c3aca3 530#define CONFIG_HAS_ETH1
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531#endif
532
79f516bc 533#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
24c3aca3 534
24c3aca3 535#define CONFIG_EXTRA_ENV_SETTINGS \
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536 "netdev=eth0\0" \
537 "consoledev=ttyS0\0" \
538 "ramdiskaddr=1000000\0" \
539 "ramdiskfile=ramfs.83xx\0" \
540 "fdtaddr=780000\0" \
541 "fdtfile=mpc832x_mds.dtb\0" \
542 ""
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543
544#define CONFIG_NFSBOOTCOMMAND \
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545 "setenv bootargs root=/dev/nfs rw " \
546 "nfsroot=$serverip:$rootpath " \
547 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
548 "$netdev:off " \
549 "console=$consoledev,$baudrate $othbootargs;" \
550 "tftp $loadaddr $bootfile;" \
551 "tftp $fdtaddr $fdtfile;" \
552 "bootm $loadaddr - $fdtaddr"
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553
554#define CONFIG_RAMBOOTCOMMAND \
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555 "setenv bootargs root=/dev/ram rw " \
556 "console=$consoledev,$baudrate $othbootargs;" \
557 "tftp $ramdiskaddr $ramdiskfile;" \
558 "tftp $loadaddr $bootfile;" \
559 "tftp $fdtaddr $fdtfile;" \
560 "bootm $loadaddr $ramdiskaddr $fdtaddr"
24c3aca3 561
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562#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
563
564#endif /* __CONFIG_H */
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