Commit | Line | Data |
---|---|---|
83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
49ecaa92 | 2 | /* |
3 | * Pinctrl driver for Rockchip 3036 SoCs | |
4 | * (C) Copyright 2015 Rockchip Electronics Co., Ltd | |
49ecaa92 | 5 | */ |
6 | ||
7 | #include <common.h> | |
8 | #include <dm.h> | |
9 | #include <errno.h> | |
10 | #include <syscon.h> | |
11 | #include <asm/io.h> | |
12 | #include <asm/arch/clock.h> | |
13 | #include <asm/arch/grf_rk3036.h> | |
14 | #include <asm/arch/hardware.h> | |
15 | #include <asm/arch/periph.h> | |
16 | #include <dm/pinctrl.h> | |
17 | ||
b1d093d2 AK |
18 | /* GRF_GPIO0A_IOMUX */ |
19 | enum { | |
20 | GPIO0A3_SHIFT = 6, | |
21 | GPIO0A3_MASK = 1 << GPIO0A3_SHIFT, | |
22 | GPIO0A3_GPIO = 0, | |
23 | GPIO0A3_I2C1_SDA, | |
24 | ||
25 | GPIO0A2_SHIFT = 4, | |
26 | GPIO0A2_MASK = 1 << GPIO0A2_SHIFT, | |
27 | GPIO0A2_GPIO = 0, | |
28 | GPIO0A2_I2C1_SCL, | |
29 | ||
30 | GPIO0A1_SHIFT = 2, | |
31 | GPIO0A1_MASK = 3 << GPIO0A1_SHIFT, | |
32 | GPIO0A1_GPIO = 0, | |
33 | GPIO0A1_I2C0_SDA, | |
34 | GPIO0A1_PWM2, | |
35 | ||
36 | GPIO0A0_SHIFT = 0, | |
37 | GPIO0A0_MASK = 3 << GPIO0A0_SHIFT, | |
38 | GPIO0A0_GPIO = 0, | |
39 | GPIO0A0_I2C0_SCL, | |
40 | GPIO0A0_PWM1, | |
41 | }; | |
42 | ||
43 | /* GRF_GPIO0B_IOMUX */ | |
44 | enum { | |
45 | GPIO0B6_SHIFT = 12, | |
46 | GPIO0B6_MASK = 3 << GPIO0B6_SHIFT, | |
47 | GPIO0B6_GPIO = 0, | |
48 | GPIO0B6_MMC1_D3, | |
49 | GPIO0B6_I2S1_SCLK, | |
50 | ||
51 | GPIO0B5_SHIFT = 10, | |
52 | GPIO0B5_MASK = 3 << GPIO0B5_SHIFT, | |
53 | GPIO0B5_GPIO = 0, | |
54 | GPIO0B5_MMC1_D2, | |
55 | GPIO0B5_I2S1_SDI, | |
56 | ||
57 | GPIO0B4_SHIFT = 8, | |
58 | GPIO0B4_MASK = 3 << GPIO0B4_SHIFT, | |
59 | GPIO0B4_GPIO = 0, | |
60 | GPIO0B4_MMC1_D1, | |
61 | GPIO0B4_I2S1_LRCKTX, | |
62 | ||
63 | GPIO0B3_SHIFT = 6, | |
64 | GPIO0B3_MASK = 3 << GPIO0B3_SHIFT, | |
65 | GPIO0B3_GPIO = 0, | |
66 | GPIO0B3_MMC1_D0, | |
67 | GPIO0B3_I2S1_LRCKRX, | |
68 | ||
69 | GPIO0B1_SHIFT = 2, | |
70 | GPIO0B1_MASK = 3 << GPIO0B1_SHIFT, | |
71 | GPIO0B1_GPIO = 0, | |
72 | GPIO0B1_MMC1_CLKOUT, | |
73 | GPIO0B1_I2S1_MCLK, | |
74 | ||
75 | GPIO0B0_SHIFT = 0, | |
76 | GPIO0B0_MASK = 3, | |
77 | GPIO0B0_GPIO = 0, | |
78 | GPIO0B0_MMC1_CMD, | |
79 | GPIO0B0_I2S1_SDO, | |
80 | }; | |
81 | ||
82 | /* GRF_GPIO0C_IOMUX */ | |
83 | enum { | |
84 | GPIO0C4_SHIFT = 8, | |
85 | GPIO0C4_MASK = 1 << GPIO0C4_SHIFT, | |
86 | GPIO0C4_GPIO = 0, | |
87 | GPIO0C4_DRIVE_VBUS, | |
88 | ||
89 | GPIO0C3_SHIFT = 6, | |
90 | GPIO0C3_MASK = 1 << GPIO0C3_SHIFT, | |
91 | GPIO0C3_GPIO = 0, | |
92 | GPIO0C3_UART0_CTSN, | |
93 | ||
94 | GPIO0C2_SHIFT = 4, | |
95 | GPIO0C2_MASK = 1 << GPIO0C2_SHIFT, | |
96 | GPIO0C2_GPIO = 0, | |
97 | GPIO0C2_UART0_RTSN, | |
98 | ||
99 | GPIO0C1_SHIFT = 2, | |
100 | GPIO0C1_MASK = 1 << GPIO0C1_SHIFT, | |
101 | GPIO0C1_GPIO = 0, | |
102 | GPIO0C1_UART0_SIN, | |
103 | ||
104 | ||
105 | GPIO0C0_SHIFT = 0, | |
106 | GPIO0C0_MASK = 1 << GPIO0C0_SHIFT, | |
107 | GPIO0C0_GPIO = 0, | |
108 | GPIO0C0_UART0_SOUT, | |
109 | }; | |
110 | ||
111 | /* GRF_GPIO0D_IOMUX */ | |
112 | enum { | |
113 | GPIO0D4_SHIFT = 8, | |
114 | GPIO0D4_MASK = 1 << GPIO0D4_SHIFT, | |
115 | GPIO0D4_GPIO = 0, | |
116 | GPIO0D4_SPDIF, | |
117 | ||
118 | GPIO0D3_SHIFT = 6, | |
119 | GPIO0D3_MASK = 1 << GPIO0D3_SHIFT, | |
120 | GPIO0D3_GPIO = 0, | |
121 | GPIO0D3_PWM3, | |
122 | ||
123 | GPIO0D2_SHIFT = 4, | |
124 | GPIO0D2_MASK = 1 << GPIO0D2_SHIFT, | |
125 | GPIO0D2_GPIO = 0, | |
126 | GPIO0D2_PWM0, | |
127 | }; | |
128 | ||
129 | /* GRF_GPIO1A_IOMUX */ | |
130 | enum { | |
131 | GPIO1A5_SHIFT = 10, | |
132 | GPIO1A5_MASK = 1 << GPIO1A5_SHIFT, | |
133 | GPIO1A5_GPIO = 0, | |
134 | GPIO1A5_I2S_SDI, | |
135 | ||
136 | GPIO1A4_SHIFT = 8, | |
137 | GPIO1A4_MASK = 1 << GPIO1A4_SHIFT, | |
138 | GPIO1A4_GPIO = 0, | |
139 | GPIO1A4_I2S_SD0, | |
140 | ||
141 | GPIO1A3_SHIFT = 6, | |
142 | GPIO1A3_MASK = 1 << GPIO1A3_SHIFT, | |
143 | GPIO1A3_GPIO = 0, | |
144 | GPIO1A3_I2S_LRCKTX, | |
145 | ||
146 | GPIO1A2_SHIFT = 4, | |
147 | GPIO1A2_MASK = 3 << GPIO1A2_SHIFT, | |
148 | GPIO1A2_GPIO = 0, | |
149 | GPIO1A2_I2S_LRCKRX, | |
150 | GPIO1A2_PWM1_0, | |
151 | ||
152 | GPIO1A1_SHIFT = 2, | |
153 | GPIO1A1_MASK = 1 << GPIO1A1_SHIFT, | |
154 | GPIO1A1_GPIO = 0, | |
155 | GPIO1A1_I2S_SCLK, | |
156 | ||
157 | GPIO1A0_SHIFT = 0, | |
158 | GPIO1A0_MASK = 1 << GPIO1A0_SHIFT, | |
159 | GPIO1A0_GPIO = 0, | |
160 | GPIO1A0_I2S_MCLK, | |
161 | ||
162 | }; | |
163 | ||
164 | /* GRF_GPIO1B_IOMUX */ | |
165 | enum { | |
166 | GPIO1B7_SHIFT = 14, | |
167 | GPIO1B7_MASK = 1 << GPIO1B7_SHIFT, | |
168 | GPIO1B7_GPIO = 0, | |
169 | GPIO1B7_MMC0_CMD, | |
170 | ||
171 | GPIO1B3_SHIFT = 6, | |
172 | GPIO1B3_MASK = 1 << GPIO1B3_SHIFT, | |
173 | GPIO1B3_GPIO = 0, | |
174 | GPIO1B3_HDMI_HPD, | |
175 | ||
176 | GPIO1B2_SHIFT = 4, | |
177 | GPIO1B2_MASK = 1 << GPIO1B2_SHIFT, | |
178 | GPIO1B2_GPIO = 0, | |
179 | GPIO1B2_HDMI_SCL, | |
180 | ||
181 | GPIO1B1_SHIFT = 2, | |
182 | GPIO1B1_MASK = 1 << GPIO1B1_SHIFT, | |
183 | GPIO1B1_GPIO = 0, | |
184 | GPIO1B1_HDMI_SDA, | |
185 | ||
186 | GPIO1B0_SHIFT = 0, | |
187 | GPIO1B0_MASK = 1 << GPIO1B0_SHIFT, | |
188 | GPIO1B0_GPIO = 0, | |
189 | GPIO1B0_HDMI_CEC, | |
190 | }; | |
191 | ||
192 | /* GRF_GPIO1C_IOMUX */ | |
193 | enum { | |
194 | GPIO1C5_SHIFT = 10, | |
195 | GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, | |
196 | GPIO1C5_GPIO = 0, | |
197 | GPIO1C5_MMC0_D3, | |
198 | GPIO1C5_JTAG_TMS, | |
199 | ||
200 | GPIO1C4_SHIFT = 8, | |
201 | GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, | |
202 | GPIO1C4_GPIO = 0, | |
203 | GPIO1C4_MMC0_D2, | |
204 | GPIO1C4_JTAG_TCK, | |
205 | ||
206 | GPIO1C3_SHIFT = 6, | |
207 | GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, | |
208 | GPIO1C3_GPIO = 0, | |
209 | GPIO1C3_MMC0_D1, | |
210 | GPIO1C3_UART2_SOUT, | |
211 | ||
212 | GPIO1C2_SHIFT = 4, | |
213 | GPIO1C2_MASK = 3 << GPIO1C2_SHIFT , | |
214 | GPIO1C2_GPIO = 0, | |
215 | GPIO1C2_MMC0_D0, | |
216 | GPIO1C2_UART2_SIN, | |
217 | ||
218 | GPIO1C1_SHIFT = 2, | |
219 | GPIO1C1_MASK = 1 << GPIO1C1_SHIFT, | |
220 | GPIO1C1_GPIO = 0, | |
221 | GPIO1C1_MMC0_DETN, | |
222 | ||
223 | GPIO1C0_SHIFT = 0, | |
224 | GPIO1C0_MASK = 1 << GPIO1C0_SHIFT, | |
225 | GPIO1C0_GPIO = 0, | |
226 | GPIO1C0_MMC0_CLKOUT, | |
227 | }; | |
228 | ||
229 | /* GRF_GPIO1D_IOMUX */ | |
230 | enum { | |
231 | GPIO1D7_SHIFT = 14, | |
232 | GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, | |
233 | GPIO1D7_GPIO = 0, | |
234 | GPIO1D7_NAND_D7, | |
235 | GPIO1D7_EMMC_D7, | |
236 | GPIO1D7_SPI_CSN1, | |
237 | ||
238 | GPIO1D6_SHIFT = 12, | |
239 | GPIO1D6_MASK = 3 << GPIO1D6_SHIFT, | |
240 | GPIO1D6_GPIO = 0, | |
241 | GPIO1D6_NAND_D6, | |
242 | GPIO1D6_EMMC_D6, | |
243 | GPIO1D6_SPI_CSN0, | |
244 | ||
245 | GPIO1D5_SHIFT = 10, | |
246 | GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, | |
247 | GPIO1D5_GPIO = 0, | |
248 | GPIO1D5_NAND_D5, | |
249 | GPIO1D5_EMMC_D5, | |
250 | GPIO1D5_SPI_TXD, | |
251 | ||
252 | GPIO1D4_SHIFT = 8, | |
253 | GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, | |
254 | GPIO1D4_GPIO = 0, | |
255 | GPIO1D4_NAND_D4, | |
256 | GPIO1D4_EMMC_D4, | |
257 | GPIO1D4_SPI_RXD, | |
258 | ||
259 | GPIO1D3_SHIFT = 6, | |
260 | GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, | |
261 | GPIO1D3_GPIO = 0, | |
262 | GPIO1D3_NAND_D3, | |
263 | GPIO1D3_EMMC_D3, | |
264 | GPIO1D3_SFC_SIO3, | |
265 | ||
266 | GPIO1D2_SHIFT = 4, | |
267 | GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, | |
268 | GPIO1D2_GPIO = 0, | |
269 | GPIO1D2_NAND_D2, | |
270 | GPIO1D2_EMMC_D2, | |
271 | GPIO1D2_SFC_SIO2, | |
272 | ||
273 | GPIO1D1_SHIFT = 2, | |
274 | GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, | |
275 | GPIO1D1_GPIO = 0, | |
276 | GPIO1D1_NAND_D1, | |
277 | GPIO1D1_EMMC_D1, | |
278 | GPIO1D1_SFC_SIO1, | |
279 | ||
280 | GPIO1D0_SHIFT = 0, | |
281 | GPIO1D0_MASK = 3 << GPIO1D0_SHIFT, | |
282 | GPIO1D0_GPIO = 0, | |
283 | GPIO1D0_NAND_D0, | |
284 | GPIO1D0_EMMC_D0, | |
285 | GPIO1D0_SFC_SIO0, | |
286 | }; | |
287 | ||
288 | /* GRF_GPIO2A_IOMUX */ | |
289 | enum { | |
290 | GPIO2A7_SHIFT = 14, | |
291 | GPIO2A7_MASK = 1 << GPIO2A7_SHIFT, | |
292 | GPIO2A7_GPIO = 0, | |
293 | GPIO2A7_TESTCLK_OUT, | |
294 | ||
295 | GPIO2A6_SHIFT = 12, | |
296 | GPIO2A6_MASK = 1 << GPIO2A6_SHIFT, | |
297 | GPIO2A6_GPIO = 0, | |
298 | GPIO2A6_NAND_CS0, | |
299 | ||
300 | GPIO2A4_SHIFT = 8, | |
301 | GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, | |
302 | GPIO2A4_GPIO = 0, | |
303 | GPIO2A4_NAND_RDY, | |
304 | GPIO2A4_EMMC_CMD, | |
305 | GPIO2A3_SFC_CLK, | |
306 | ||
307 | GPIO2A3_SHIFT = 6, | |
308 | GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, | |
309 | GPIO2A3_GPIO = 0, | |
310 | GPIO2A3_NAND_RDN, | |
311 | GPIO2A4_SFC_CSN1, | |
312 | ||
313 | GPIO2A2_SHIFT = 4, | |
314 | GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, | |
315 | GPIO2A2_GPIO = 0, | |
316 | GPIO2A2_NAND_WRN, | |
317 | GPIO2A4_SFC_CSN0, | |
318 | ||
319 | GPIO2A1_SHIFT = 2, | |
320 | GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, | |
321 | GPIO2A1_GPIO = 0, | |
322 | GPIO2A1_NAND_CLE, | |
323 | GPIO2A1_EMMC_CLKOUT, | |
324 | ||
325 | GPIO2A0_SHIFT = 0, | |
326 | GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, | |
327 | GPIO2A0_GPIO = 0, | |
328 | GPIO2A0_NAND_ALE, | |
329 | GPIO2A0_SPI_CLK, | |
330 | }; | |
331 | ||
332 | /* GRF_GPIO2B_IOMUX */ | |
333 | enum { | |
334 | GPIO2B7_SHIFT = 14, | |
335 | GPIO2B7_MASK = 1 << GPIO2B7_SHIFT, | |
336 | GPIO2B7_GPIO = 0, | |
337 | GPIO2B7_MAC_RXER, | |
338 | ||
339 | GPIO2B6_SHIFT = 12, | |
340 | GPIO2B6_MASK = 3 << GPIO2B6_SHIFT, | |
341 | GPIO2B6_GPIO = 0, | |
342 | GPIO2B6_MAC_CLKOUT, | |
343 | GPIO2B6_MAC_CLKIN, | |
344 | ||
345 | GPIO2B5_SHIFT = 10, | |
346 | GPIO2B5_MASK = 1 << GPIO2B5_SHIFT, | |
347 | GPIO2B5_GPIO = 0, | |
348 | GPIO2B5_MAC_TXEN, | |
349 | ||
350 | GPIO2B4_SHIFT = 8, | |
351 | GPIO2B4_MASK = 1 << GPIO2B4_SHIFT, | |
352 | GPIO2B4_GPIO = 0, | |
353 | GPIO2B4_MAC_MDIO, | |
354 | ||
355 | GPIO2B2_SHIFT = 4, | |
356 | GPIO2B2_MASK = 1 << GPIO2B2_SHIFT, | |
357 | GPIO2B2_GPIO = 0, | |
358 | GPIO2B2_MAC_CRS, | |
359 | }; | |
360 | ||
361 | /* GRF_GPIO2C_IOMUX */ | |
362 | enum { | |
363 | GPIO2C7_SHIFT = 14, | |
364 | GPIO2C7_MASK = 3 << GPIO2C7_SHIFT, | |
365 | GPIO2C7_GPIO = 0, | |
366 | GPIO2C7_UART1_SOUT, | |
367 | GPIO2C7_TESTCLK_OUT1, | |
368 | ||
369 | GPIO2C6_SHIFT = 12, | |
370 | GPIO2C6_MASK = 1 << GPIO2C6_SHIFT, | |
371 | GPIO2C6_GPIO = 0, | |
372 | GPIO2C6_UART1_SIN, | |
373 | ||
374 | GPIO2C5_SHIFT = 10, | |
375 | GPIO2C5_MASK = 1 << GPIO2C5_SHIFT, | |
376 | GPIO2C5_GPIO = 0, | |
377 | GPIO2C5_I2C2_SCL, | |
378 | ||
379 | GPIO2C4_SHIFT = 8, | |
380 | GPIO2C4_MASK = 1 << GPIO2C4_SHIFT, | |
381 | GPIO2C4_GPIO = 0, | |
382 | GPIO2C4_I2C2_SDA, | |
383 | ||
384 | GPIO2C3_SHIFT = 6, | |
385 | GPIO2C3_MASK = 1 << GPIO2C3_SHIFT, | |
386 | GPIO2C3_GPIO = 0, | |
387 | GPIO2C3_MAC_TXD0, | |
388 | ||
389 | GPIO2C2_SHIFT = 4, | |
390 | GPIO2C2_MASK = 1 << GPIO2C2_SHIFT, | |
391 | GPIO2C2_GPIO = 0, | |
392 | GPIO2C2_MAC_TXD1, | |
393 | ||
394 | GPIO2C1_SHIFT = 2, | |
395 | GPIO2C1_MASK = 1 << GPIO2C1_SHIFT, | |
396 | GPIO2C1_GPIO = 0, | |
397 | GPIO2C1_MAC_RXD0, | |
398 | ||
399 | GPIO2C0_SHIFT = 0, | |
400 | GPIO2C0_MASK = 1 << GPIO2C0_SHIFT, | |
401 | GPIO2C0_GPIO = 0, | |
402 | GPIO2C0_MAC_RXD1, | |
403 | }; | |
404 | ||
405 | /* GRF_GPIO2D_IOMUX */ | |
406 | enum { | |
407 | GPIO2D6_SHIFT = 12, | |
408 | GPIO2D6_MASK = 1 << GPIO2D6_SHIFT, | |
409 | GPIO2D6_GPIO = 0, | |
410 | GPIO2D6_I2S_SDO1, | |
411 | ||
412 | GPIO2D5_SHIFT = 10, | |
413 | GPIO2D5_MASK = 1 << GPIO2D5_SHIFT, | |
414 | GPIO2D5_GPIO = 0, | |
415 | GPIO2D5_I2S_SDO2, | |
416 | ||
417 | GPIO2D4_SHIFT = 8, | |
418 | GPIO2D4_MASK = 1 << GPIO2D4_SHIFT, | |
419 | GPIO2D4_GPIO = 0, | |
420 | GPIO2D4_I2S_SDO3, | |
421 | ||
422 | GPIO2D1_SHIFT = 2, | |
423 | GPIO2D1_MASK = 1 << GPIO2D1_SHIFT, | |
424 | GPIO2D1_GPIO = 0, | |
425 | GPIO2D1_MAC_MDC, | |
426 | }; | |
427 | ||
49ecaa92 | 428 | struct rk3036_pinctrl_priv { |
429 | struct rk3036_grf *grf; | |
430 | }; | |
431 | ||
432 | static void pinctrl_rk3036_pwm_config(struct rk3036_grf *grf, int pwm_id) | |
433 | { | |
434 | switch (pwm_id) { | |
435 | case PERIPH_ID_PWM0: | |
3c421f6f | 436 | rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK, |
49ecaa92 | 437 | GPIO0D2_PWM0 << GPIO0D2_SHIFT); |
438 | break; | |
439 | case PERIPH_ID_PWM1: | |
3c421f6f | 440 | rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A0_MASK, |
49ecaa92 | 441 | GPIO0A0_PWM1 << GPIO0A0_SHIFT); |
442 | break; | |
443 | case PERIPH_ID_PWM2: | |
3c421f6f | 444 | rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A1_MASK, |
49ecaa92 | 445 | GPIO0A1_PWM2 << GPIO0A1_SHIFT); |
446 | break; | |
447 | case PERIPH_ID_PWM3: | |
3c421f6f | 448 | rk_clrsetreg(&grf->gpio0a_iomux, GPIO0D3_MASK, |
49ecaa92 | 449 | GPIO0D3_PWM3 << GPIO0D3_SHIFT); |
450 | break; | |
451 | default: | |
452 | debug("pwm id = %d iomux error!\n", pwm_id); | |
453 | break; | |
454 | } | |
455 | } | |
456 | ||
457 | static void pinctrl_rk3036_i2c_config(struct rk3036_grf *grf, int i2c_id) | |
458 | { | |
459 | switch (i2c_id) { | |
460 | case PERIPH_ID_I2C0: | |
461 | rk_clrsetreg(&grf->gpio0a_iomux, | |
3c421f6f | 462 | GPIO0A1_MASK | GPIO0A0_MASK, |
49ecaa92 | 463 | GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT | |
464 | GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT); | |
465 | ||
466 | break; | |
467 | case PERIPH_ID_I2C1: | |
468 | rk_clrsetreg(&grf->gpio0a_iomux, | |
3c421f6f | 469 | GPIO0A3_MASK | GPIO0A2_MASK, |
49ecaa92 | 470 | GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT | |
471 | GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT); | |
472 | break; | |
473 | case PERIPH_ID_I2C2: | |
474 | rk_clrsetreg(&grf->gpio2c_iomux, | |
3c421f6f | 475 | GPIO2C5_MASK | GPIO2C4_MASK, |
49ecaa92 | 476 | GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT | |
477 | GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT); | |
478 | ||
479 | break; | |
480 | } | |
481 | } | |
482 | ||
483 | static void pinctrl_rk3036_spi_config(struct rk3036_grf *grf, int cs) | |
484 | { | |
485 | switch (cs) { | |
486 | case 0: | |
3c421f6f | 487 | rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D6_MASK, |
49ecaa92 | 488 | GPIO1D6_SPI_CSN0 << GPIO1D6_SHIFT); |
489 | break; | |
490 | case 1: | |
3c421f6f | 491 | rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D7_MASK, |
49ecaa92 | 492 | GPIO1D7_SPI_CSN1 << GPIO1D7_SHIFT); |
493 | break; | |
494 | } | |
495 | rk_clrsetreg(&grf->gpio1d_iomux, | |
3c421f6f | 496 | GPIO1D5_MASK | GPIO1D4_MASK, |
49ecaa92 | 497 | GPIO1D5_SPI_TXD << GPIO1D5_SHIFT | |
498 | GPIO1D4_SPI_RXD << GPIO1D4_SHIFT); | |
499 | ||
3c421f6f | 500 | rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A0_MASK, |
49ecaa92 | 501 | GPIO2A0_SPI_CLK << GPIO2A0_SHIFT); |
502 | } | |
503 | ||
504 | static void pinctrl_rk3036_uart_config(struct rk3036_grf *grf, int uart_id) | |
505 | { | |
506 | switch (uart_id) { | |
507 | case PERIPH_ID_UART0: | |
508 | rk_clrsetreg(&grf->gpio0c_iomux, | |
3c421f6f KY |
509 | GPIO0C3_MASK | GPIO0C2_MASK | |
510 | GPIO0C1_MASK | GPIO0C0_MASK, | |
49ecaa92 | 511 | GPIO0C3_UART0_CTSN << GPIO0C3_SHIFT | |
512 | GPIO0C2_UART0_RTSN << GPIO0C2_SHIFT | | |
513 | GPIO0C1_UART0_SIN << GPIO0C1_SHIFT | | |
514 | GPIO0C0_UART0_SOUT << GPIO0C0_SHIFT); | |
515 | break; | |
516 | case PERIPH_ID_UART1: | |
517 | rk_clrsetreg(&grf->gpio2c_iomux, | |
3c421f6f | 518 | GPIO2C7_MASK | GPIO2C6_MASK, |
49ecaa92 | 519 | GPIO2C7_UART1_SOUT << GPIO2C7_SHIFT | |
520 | GPIO2C6_UART1_SIN << GPIO2C6_SHIFT); | |
521 | break; | |
522 | case PERIPH_ID_UART2: | |
523 | rk_clrsetreg(&grf->gpio1c_iomux, | |
3c421f6f | 524 | GPIO1C3_MASK | GPIO1C2_MASK, |
49ecaa92 | 525 | GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT | |
526 | GPIO1C2_UART2_SIN << GPIO1C2_SHIFT); | |
527 | break; | |
528 | } | |
529 | } | |
530 | ||
531 | static void pinctrl_rk3036_sdmmc_config(struct rk3036_grf *grf, int mmc_id) | |
532 | { | |
533 | switch (mmc_id) { | |
534 | case PERIPH_ID_EMMC: | |
535 | rk_clrsetreg(&grf->gpio1d_iomux, 0xffff, | |
536 | GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT | | |
537 | GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT | | |
538 | GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT | | |
539 | GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT | | |
540 | GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT | | |
541 | GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT | | |
542 | GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT | | |
543 | GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT); | |
544 | rk_clrsetreg(&grf->gpio2a_iomux, | |
3c421f6f | 545 | GPIO2A4_MASK | GPIO2A1_MASK, |
49ecaa92 | 546 | GPIO2A4_EMMC_CMD << GPIO2A4_SHIFT | |
547 | GPIO2A1_EMMC_CLKOUT << GPIO2A1_SHIFT); | |
548 | break; | |
549 | case PERIPH_ID_SDCARD: | |
550 | rk_clrsetreg(&grf->gpio1c_iomux, 0xffff, | |
551 | GPIO1C5_MMC0_D3 << GPIO1C5_SHIFT | | |
552 | GPIO1C4_MMC0_D2 << GPIO1C4_SHIFT | | |
553 | GPIO1C3_MMC0_D1 << GPIO1C3_SHIFT | | |
554 | GPIO1C2_MMC0_D0 << GPIO1C2_SHIFT | | |
555 | GPIO1C1_MMC0_DETN << GPIO1C1_SHIFT | | |
556 | GPIO1C0_MMC0_CLKOUT << GPIO1C0_SHIFT); | |
557 | break; | |
558 | } | |
559 | } | |
560 | ||
561 | static int rk3036_pinctrl_request(struct udevice *dev, int func, int flags) | |
562 | { | |
563 | struct rk3036_pinctrl_priv *priv = dev_get_priv(dev); | |
564 | ||
565 | debug("%s: func=%x, flags=%x\n", __func__, func, flags); | |
566 | switch (func) { | |
567 | case PERIPH_ID_PWM0: | |
568 | case PERIPH_ID_PWM1: | |
569 | case PERIPH_ID_PWM2: | |
570 | case PERIPH_ID_PWM3: | |
571 | pinctrl_rk3036_pwm_config(priv->grf, func); | |
572 | break; | |
573 | case PERIPH_ID_I2C0: | |
574 | case PERIPH_ID_I2C1: | |
575 | case PERIPH_ID_I2C2: | |
576 | pinctrl_rk3036_i2c_config(priv->grf, func); | |
577 | break; | |
578 | case PERIPH_ID_SPI0: | |
579 | pinctrl_rk3036_spi_config(priv->grf, flags); | |
580 | break; | |
581 | case PERIPH_ID_UART0: | |
582 | case PERIPH_ID_UART1: | |
583 | case PERIPH_ID_UART2: | |
584 | pinctrl_rk3036_uart_config(priv->grf, func); | |
585 | break; | |
586 | case PERIPH_ID_SDMMC0: | |
587 | case PERIPH_ID_SDMMC1: | |
588 | pinctrl_rk3036_sdmmc_config(priv->grf, func); | |
589 | break; | |
590 | default: | |
591 | return -EINVAL; | |
592 | } | |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
597 | static int rk3036_pinctrl_get_periph_id(struct udevice *dev, | |
598 | struct udevice *periph) | |
599 | { | |
600 | u32 cell[3]; | |
601 | int ret; | |
602 | ||
9f4f914d | 603 | ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); |
49ecaa92 | 604 | if (ret < 0) |
605 | return -EINVAL; | |
606 | ||
607 | switch (cell[1]) { | |
608 | case 14: | |
609 | return PERIPH_ID_SDCARD; | |
610 | case 16: | |
611 | return PERIPH_ID_EMMC; | |
612 | case 20: | |
613 | return PERIPH_ID_UART0; | |
614 | case 21: | |
615 | return PERIPH_ID_UART1; | |
616 | case 22: | |
617 | return PERIPH_ID_UART2; | |
618 | case 23: | |
619 | return PERIPH_ID_SPI0; | |
620 | case 24: | |
621 | return PERIPH_ID_I2C0; | |
622 | case 25: | |
623 | return PERIPH_ID_I2C1; | |
624 | case 26: | |
625 | return PERIPH_ID_I2C2; | |
626 | case 30: | |
627 | return PERIPH_ID_PWM0; | |
628 | } | |
629 | return -ENOENT; | |
630 | } | |
631 | ||
632 | static int rk3036_pinctrl_set_state_simple(struct udevice *dev, | |
633 | struct udevice *periph) | |
634 | { | |
635 | int func; | |
636 | ||
637 | func = rk3036_pinctrl_get_periph_id(dev, periph); | |
638 | if (func < 0) | |
639 | return func; | |
640 | return rk3036_pinctrl_request(dev, func, 0); | |
641 | } | |
642 | ||
643 | static struct pinctrl_ops rk3036_pinctrl_ops = { | |
644 | .set_state_simple = rk3036_pinctrl_set_state_simple, | |
645 | .request = rk3036_pinctrl_request, | |
646 | .get_periph_id = rk3036_pinctrl_get_periph_id, | |
647 | }; | |
648 | ||
649 | static int rk3036_pinctrl_probe(struct udevice *dev) | |
650 | { | |
651 | struct rk3036_pinctrl_priv *priv = dev_get_priv(dev); | |
652 | ||
653 | priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); | |
654 | debug("%s: grf=%p\n", __func__, priv->grf); | |
655 | return 0; | |
656 | } | |
657 | ||
658 | static const struct udevice_id rk3036_pinctrl_ids[] = { | |
659 | { .compatible = "rockchip,rk3036-pinctrl" }, | |
660 | { } | |
661 | }; | |
662 | ||
663 | U_BOOT_DRIVER(pinctrl_rk3036) = { | |
664 | .name = "pinctrl_rk3036", | |
665 | .id = UCLASS_PINCTRL, | |
666 | .of_match = rk3036_pinctrl_ids, | |
667 | .priv_auto_alloc_size = sizeof(struct rk3036_pinctrl_priv), | |
668 | .ops = &rk3036_pinctrl_ops, | |
91195485 | 669 | .bind = dm_scan_fdt_dev, |
49ecaa92 | 670 | .probe = rk3036_pinctrl_probe, |
671 | }; |