[u-boot.git] / drivers / pci / pci.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Andreas Heppel <[email protected]>
 *
 * (C) Copyright 2002, 2003
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 */

/*
 * Old PCI routines
 *
 * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
 * and change pci-uclass.c.
 */

#include <common.h>

#include <command.h>
#include <errno.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>

DECLARE_GLOBAL_DATA_PTR;

#define PCI_HOSE_OP(rw, size, type)					\
int pci_hose_##rw##_config_##size(struct pci_controller *hose,		\
				  pci_dev_t dev,			\
				  int offset, type value)		\
{									\
	return hose->rw##_##size(hose, dev, offset, value);		\
}

PCI_HOSE_OP(read, byte, u8 *)
PCI_HOSE_OP(read, word, u16 *)
PCI_HOSE_OP(read, dword, u32 *)
PCI_HOSE_OP(write, byte, u8)
PCI_HOSE_OP(write, word, u16)
PCI_HOSE_OP(write, dword, u32)

#define PCI_OP(rw, size, type, error_code)				\
int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value)	\
{									\
	struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev));	\
									\
	if (!hose)							\
	{								\
		error_code;						\
		return -1;						\
	}								\
									\
	return pci_hose_##rw##_config_##size(hose, dev, offset, value);	\
}

PCI_OP(read, byte, u8 *, *value = 0xff)
PCI_OP(read, word, u16 *, *value = 0xffff)
PCI_OP(read, dword, u32 *, *value = 0xffffffff)
PCI_OP(write, byte, u8, )
PCI_OP(write, word, u16, )
PCI_OP(write, dword, u32, )

#define PCI_READ_VIA_DWORD_OP(size, type, off_mask)			\
int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
					pci_dev_t dev,			\
					int offset, type val)		\
{									\
	u32 val32;							\
									\
	if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) {	\
		*val = -1;						\
		return -1;						\
	}								\
									\
	*val = (val32 >> ((offset & (int)off_mask) * 8));		\
									\
	return 0;							\
}

#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask)		\
int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
					     pci_dev_t dev,		\
					     int offset, type val)	\
{									\
	u32 val32, mask, ldata, shift;					\
									\
	if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
		return -1;						\
									\
	shift = ((offset & (int)off_mask) * 8);				\
	ldata = (((unsigned long)val) & val_mask) << shift;		\
	mask = val_mask << shift;					\
	val32 = (val32 & ~mask) | ldata;				\
									\
	if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
		return -1;						\
									\
	return 0;							\
}

PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)

/*
 *
 */

static struct pci_controller* hose_head;

struct pci_controller *pci_get_hose_head(void)
{
	if (gd->hose)
		return gd->hose;

	return hose_head;
}

void pci_register_hose(struct pci_controller* hose)
{
	struct pci_controller **phose = &hose_head;

	while(*phose)
		phose = &(*phose)->next;

	hose->next = NULL;

	*phose = hose;
}

struct pci_controller *pci_bus_to_hose(int bus)
{
	struct pci_controller *hose;

	for (hose = pci_get_hose_head(); hose; hose = hose->next) {
		if (bus >= hose->first_busno && bus <= hose->last_busno)
			return hose;
	}

	printf("pci_bus_to_hose() failed\n");
	return NULL;
}

struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
{
	struct pci_controller *hose;

	for (hose = pci_get_hose_head(); hose; hose = hose->next) {
		if (hose->cfg_addr == cfg_addr)
			return hose;
	}

	return NULL;
}

int pci_last_busno(void)
{
	struct pci_controller *hose = pci_get_hose_head();

	if (!hose)
		return -1;

	while (hose->next)
		hose = hose->next;

	return hose->last_busno;
}

pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
{
	struct pci_controller * hose;
	pci_dev_t bdf;
	int bus;

	for (hose = pci_get_hose_head(); hose; hose = hose->next) {
		for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
			bdf = pci_hose_find_devices(hose, bus, ids, &index);
			if (bdf != -1)
				return bdf;
		}
	}

	return -1;
}

int pci_hose_config_device(struct pci_controller *hose,
			   pci_dev_t dev,
			   unsigned long io,
			   pci_addr_t mem,
			   unsigned long command)
{
	u32 bar_response;
	unsigned int old_command;
	pci_addr_t bar_value;
	pci_size_t bar_size;
	unsigned char pin;
	int bar, found_mem64;

	debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
		(u64)mem, command);

	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);

	for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
		pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
		pci_hose_read_config_dword(hose, dev, bar, &bar_response);

		if (!bar_response)
			continue;

		found_mem64 = 0;

		/* Check the BAR type and set our address mask */
		if (bar_response & PCI_BASE_ADDRESS_SPACE) {
			bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
			/* round up region base address to a multiple of size */
			io = ((io - 1) | (bar_size - 1)) + 1;
			bar_value = io;
			/* compute new region base address */
			io = io + bar_size;
		} else {
			if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
				PCI_BASE_ADDRESS_MEM_TYPE_64) {
				u32 bar_response_upper;
				u64 bar64;
				pci_hose_write_config_dword(hose, dev, bar + 4,
					0xffffffff);
				pci_hose_read_config_dword(hose, dev, bar + 4,
					&bar_response_upper);

				bar64 = ((u64)bar_response_upper << 32) | bar_response;

				bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
				found_mem64 = 1;
			} else {
				bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
			}

			/* round up region base address to multiple of size */
			mem = ((mem - 1) | (bar_size - 1)) + 1;
			bar_value = mem;
			/* compute new region base address */
			mem = mem + bar_size;
		}

		/* Write it out and update our limit */
		pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);

		if (found_mem64) {
			bar += 4;
#ifdef CONFIG_SYS_PCI_64BIT
			pci_hose_write_config_dword(hose, dev, bar,
				(u32)(bar_value >> 32));
#else
			pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
#endif
		}
	}

	/* Configure Cache Line Size Register */
	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);

	/* Configure Latency Timer */
	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);

	/* Disable interrupt line, if device says it wants to use interrupts */
	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
	if (pin != 0) {
		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
					   PCI_INTERRUPT_LINE_DISABLE);
	}

	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
	pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
				     (old_command & 0xffff0000) | command);

	return 0;
}

/*
 *
 */

struct pci_config_table *pci_find_config(struct pci_controller *hose,
					 unsigned short class,
					 unsigned int vendor,
					 unsigned int device,
					 unsigned int bus,
					 unsigned int dev,
					 unsigned int func)
{
	struct pci_config_table *table;

	for (table = hose->config_table; table && table->vendor; table++) {
		if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
		    (table->device == PCI_ANY_ID || table->device == device) &&
		    (table->class  == PCI_ANY_ID || table->class  == class)  &&
		    (table->bus    == PCI_ANY_ID || table->bus    == bus)    &&
		    (table->dev    == PCI_ANY_ID || table->dev    == dev)    &&
		    (table->func   == PCI_ANY_ID || table->func   == func)) {
			return table;
		}
	}

	return NULL;
}

void pci_cfgfunc_config_device(struct pci_controller *hose,
			       pci_dev_t dev,
			       struct pci_config_table *entry)
{
	pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
		entry->priv[2]);
}

void pci_cfgfunc_do_nothing(struct pci_controller *hose,
			    pci_dev_t dev, struct pci_config_table *entry)
{
}

/*
 * HJF: Changed this to return int. I think this is required
 * to get the correct result when scanning bridges
 */
extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);

#ifdef CONFIG_PCI_SCAN_SHOW
__weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
{
	if (dev == PCI_BDF(hose->first_busno, 0, 0))
		return 0;

	return 1;
}
#endif /* CONFIG_PCI_SCAN_SHOW */

int pci_hose_scan_bus(struct pci_controller *hose, int bus)
{
	unsigned int sub_bus, found_multi = 0;
	unsigned short vendor, device, class;
	unsigned char header_type;
#ifndef CONFIG_PCI_PNP
	struct pci_config_table *cfg;
#endif
	pci_dev_t dev;
#ifdef CONFIG_PCI_SCAN_SHOW
	static int indent = 0;
#endif

	sub_bus = bus;

	for (dev =  PCI_BDF(bus,0,0);
	     dev <  PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
				PCI_MAX_PCI_FUNCTIONS - 1);
	     dev += PCI_BDF(0, 0, 1)) {

		if (pci_skip_dev(hose, dev))
			continue;

		if (PCI_FUNC(dev) && !found_multi)
			continue;

		pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);

		pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);

		if (vendor == 0xffff || vendor == 0x0000)
			continue;

		if (!PCI_FUNC(dev))
			found_multi = header_type & 0x80;

		debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
			PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));

		pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
		pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);

#ifdef CONFIG_PCI_FIXUP_DEV
		board_pci_fixup_dev(hose, dev, vendor, device, class);
#endif

#ifdef CONFIG_PCI_SCAN_SHOW
		indent++;

		/* Print leading space, including bus indentation */
		printf("%*c", indent + 1, ' ');

		if (pci_print_dev(hose, dev)) {
			printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
			       PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
			       vendor, device, pci_class_str(class >> 8));
		}
#endif

#ifdef CONFIG_PCI_PNP
		sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
			      sub_bus);
#else
		cfg = pci_find_config(hose, class, vendor, device,
				      PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
		if (cfg) {
			cfg->config_device(hose, dev, cfg);
			sub_bus = max(sub_bus,
				      (unsigned int)hose->current_busno);
		}
#endif

#ifdef CONFIG_PCI_SCAN_SHOW
		indent--;
#endif

		if (hose->fixup_irq)
			hose->fixup_irq(hose, dev);
	}

	return sub_bus;
}

int pci_hose_scan(struct pci_controller *hose)
{
#if defined(CONFIG_PCI_BOOTDELAY)
	char *s;
	int i;

	if (!gd->pcidelay_done) {
		/* wait "pcidelay" ms (if defined)... */
		s = env_get("pcidelay");
		if (s) {
			int val = simple_strtoul(s, NULL, 10);
			for (i = 0; i < val; i++)
				udelay(1000);
		}
		gd->pcidelay_done = 1;
	}
#endif /* CONFIG_PCI_BOOTDELAY */

#ifdef CONFIG_PCI_SCAN_SHOW
	puts("PCI:\n");
#endif

	/*
	 * Start scan at current_busno.
	 * PCIe will start scan at first_busno+1.
	 */
	/* For legacy support, ensure current >= first */
	if (hose->first_busno > hose->current_busno)
		hose->current_busno = hose->first_busno;
#ifdef CONFIG_PCI_PNP
	pciauto_config_init(hose);
#endif
	return pci_hose_scan_bus(hose, hose->current_busno);
}

void pci_init(void)
{
	hose_head = NULL;

	/* allow env to disable pci init/enum */
	if (env_get("pcidisable") != NULL)
		return;

	/* now call board specific pci_init()... */
	pci_init_board();
}

/* Returns the address of the requested capability structure within the
 * device's PCI configuration space or 0 in case the device does not
 * support it.
 * */
int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
			     int cap)
{
	int pos;
	u8 hdr_type;

	pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);

	pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);

	if (pos)
		pos = pci_find_cap(hose, dev, pos, cap);

	return pos;
}

/* Find the header pointer to the Capabilities*/
int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
			    u8 hdr_type)
{
	u16 status;

	pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);

	if (!(status & PCI_STATUS_CAP_LIST))
		return 0;

	switch (hdr_type) {
	case PCI_HEADER_TYPE_NORMAL:
	case PCI_HEADER_TYPE_BRIDGE:
		return PCI_CAPABILITY_LIST;
	case PCI_HEADER_TYPE_CARDBUS:
		return PCI_CB_CAPABILITY_LIST;
	default:
		return 0;
	}
}

int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
{
	int ttl = PCI_FIND_CAP_TTL;
	u8 id;
	u8 next_pos;

	while (ttl--) {
		pci_hose_read_config_byte(hose, dev, pos, &next_pos);
		if (next_pos < CAP_START_POS)
			break;
		next_pos &= ~3;
		pos = (int) next_pos;
		pci_hose_read_config_byte(hose, dev,
					  pos + PCI_CAP_LIST_ID, &id);
		if (id == 0xff)
			break;
		if (id == cap)
			return pos;
		pos += PCI_CAP_LIST_NEXT;
	}
	return 0;
}

/**
 * pci_find_next_ext_capability - Find an extended capability
 *
 * Returns the address of the next matching extended capability structure
 * within the device's PCI configuration space or 0 if the device does
 * not support it.  Some capabilities can occur several times, e.g., the
 * vendor-specific capability, and this provides a way to find them all.
 */
int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev,
				 int start, int cap)
{
	u32 header;
	int ttl, pos = PCI_CFG_SPACE_SIZE;

	/* minimum 8 bytes per capability */
	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;

	if (start)
		pos = start;

	pci_hose_read_config_dword(hose, dev, pos, &header);
	if (header == 0xffffffff || header == 0)
		return 0;

	while (ttl-- > 0) {
		if (PCI_EXT_CAP_ID(header) == cap && pos != start)
			return pos;

		pos = PCI_EXT_CAP_NEXT(header);
		if (pos < PCI_CFG_SPACE_SIZE)
			break;

		pci_hose_read_config_dword(hose, dev, pos, &header);
		if (header == 0xffffffff || header == 0)
			break;
	}

	return 0;
}

/**
 * pci_hose_find_ext_capability - Find an extended capability
 *
 * Returns the address of the requested extended capability structure
 * within the device's PCI configuration space or 0 if the device does
 * not support it.
 */
int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev,
				 int cap)
{
	return pci_find_next_ext_capability(hose, dev, 0, cap);
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
c609719b WD	2	/*
	3	* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	4	* Andreas Heppel <[email protected]>
	5	*
f07771cc	6	* (C) Copyright 2002, 2003
c609719b	7	* Wolfgang Denk, DENX Software Engineering, [email protected].
c609719b WD	8	*/
	9
	10	/*
2b81e8a3 SG	11	* Old PCI routines
	12	*
	13	* Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
	14	* and change pci-uclass.c.
c609719b WD	15	*/
	16
	17	#include <common.h>
	18
c609719b	19	#include <command.h>
250e039d	20	#include <errno.h>
c609719b WD	21	#include <asm/processor.h>
	22	#include <asm/io.h>
	23	#include <pci.h>
	24
8f9052fd BM	25	DECLARE_GLOBAL_DATA_PTR;
8f9052fd BM	26
f07771cc	27	#define PCI_HOSE_OP(rw, size, type) \
53677ef1 WD	28	int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
53677ef1 WD	29	pci_dev_t dev, \
f07771cc WD	30	int offset, type value) \
	31	{ \
	32	return hose->rw##_##size(hose, dev, offset, value); \
c609719b WD	33	}
	34
	35	PCI_HOSE_OP(read, byte, u8 *)
	36	PCI_HOSE_OP(read, word, u16 *)
	37	PCI_HOSE_OP(read, dword, u32 *)
	38	PCI_HOSE_OP(write, byte, u8)
	39	PCI_HOSE_OP(write, word, u16)
	40	PCI_HOSE_OP(write, dword, u32)
	41
f07771cc WD	42	#define PCI_OP(rw, size, type, error_code) \
	43	int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
	44	{ \
	45	struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
	46	\
	47	if (!hose) \
	48	{ \
	49	error_code; \
	50	return -1; \
	51	} \
	52	\
	53	return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
c609719b WD	54	}
	55
	56	PCI_OP(read, byte, u8 , value = 0xff)
	57	PCI_OP(read, word, u16 , value = 0xffff)
	58	PCI_OP(read, dword, u32 , value = 0xffffffff)
	59	PCI_OP(write, byte, u8, )
	60	PCI_OP(write, word, u16, )
	61	PCI_OP(write, dword, u32, )
	62
f07771cc WD	63	#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
f07771cc WD	64	int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
53677ef1	65	pci_dev_t dev, \
f07771cc WD	66	int offset, type val) \
	67	{ \
	68	u32 val32; \
	69	\
815b5bd5 SK	70	if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
815b5bd5 SK	71	*val = -1; \
f07771cc	72	return -1; \
815b5bd5	73	} \
f07771cc WD	74	\
	75	val = (val32 >> ((offset & (int)off_mask) 8)); \
	76	\
	77	return 0; \
c609719b WD	78	}
c609719b WD	79
f07771cc WD	80	#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
f07771cc WD	81	int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
53677ef1	82	pci_dev_t dev, \
f07771cc WD	83	int offset, type val) \
f07771cc WD	84	{ \
498b8db7	85	u32 val32, mask, ldata, shift; \
f07771cc WD	86	\
	87	if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
	88	return -1; \
	89	\
498b8db7 WD	90	shift = ((offset & (int)off_mask) * 8); \
	91	ldata = (((unsigned long)val) & val_mask) << shift; \
	92	mask = val_mask << shift; \
f07771cc WD	93	val32 = (val32 & ~mask) \| ldata; \
	94	\
	95	if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
	96	return -1; \
	97	\
	98	return 0; \
c609719b WD	99	}
	100
	101	PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
	102	PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
	103	PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
	104	PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
	105
	106	/*
	107	*
	108	*/
	109
96d61603	110	static struct pci_controller* hose_head;
c609719b	111
8f9052fd BM	112	struct pci_controller *pci_get_hose_head(void)
	113	{
	114	if (gd->hose)
	115	return gd->hose;
	116
	117	return hose_head;
	118	}
	119
c609719b WD	120	void pci_register_hose(struct pci_controller* hose)
	121	{
	122	struct pci_controller **phose = &hose_head;
	123
	124	while(*phose)
	125	phose = &(*phose)->next;
	126
	127	hose->next = NULL;
	128
	129	*phose = hose;
	130	}
	131
cb2bf931	132	struct pci_controller *pci_bus_to_hose(int bus)
c609719b WD	133	{
	134	struct pci_controller *hose;
	135
8f9052fd	136	for (hose = pci_get_hose_head(); hose; hose = hose->next) {
f07771cc	137	if (bus >= hose->first_busno && bus <= hose->last_busno)
c609719b	138	return hose;
cb2bf931	139	}
c609719b	140
6902df56	141	printf("pci_bus_to_hose() failed\n");
c609719b WD	142	return NULL;
	143	}
	144
3a0e3c27 KG	145	struct pci_controller find_hose_by_cfg_addr(void cfg_addr)
	146	{
	147	struct pci_controller *hose;
	148
8f9052fd	149	for (hose = pci_get_hose_head(); hose; hose = hose->next) {
3a0e3c27 KG	150	if (hose->cfg_addr == cfg_addr)
	151	return hose;
	152	}
	153
	154	return NULL;
	155	}
	156
cc2a8c77 AV	157	int pci_last_busno(void)
cc2a8c77 AV	158	{
8f9052fd	159	struct pci_controller *hose = pci_get_hose_head();
cc2a8c77 AV	160
	161	if (!hose)
	162	return -1;
	163
	164	while (hose->next)
	165	hose = hose->next;
	166
	167	return hose->last_busno;
	168	}
	169
c609719b WD	170	pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
	171	{
	172	struct pci_controller * hose;
c609719b	173	pci_dev_t bdf;
aab6724c	174	int bus;
c609719b	175
8f9052fd	176	for (hose = pci_get_hose_head(); hose; hose = hose->next) {
aab6724c	177	for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
aab6724c SG	178	bdf = pci_hose_find_devices(hose, bus, ids, &index);
aab6724c SG	179	if (bdf != -1)
250e039d	180	return bdf;
250e039d SG	181	}
	182	}
	183
aab6724c	184	return -1;
c609719b WD	185	}
c609719b WD	186
c609719b WD	187	int pci_hose_config_device(struct pci_controller *hose,
	188	pci_dev_t dev,
	189	unsigned long io,
30e76d5e	190	pci_addr_t mem,
c609719b WD	191	unsigned long command)
c609719b WD	192	{
cf5787f2	193	u32 bar_response;
af778c6d	194	unsigned int old_command;
30e76d5e KG	195	pci_addr_t bar_value;
30e76d5e KG	196	pci_size_t bar_size;
c609719b WD	197	unsigned char pin;
	198	int bar, found_mem64;
	199
cb2bf931 AS	200	debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
cb2bf931 AS	201	(u64)mem, command);
c609719b	202
cb2bf931	203	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
c609719b	204
252b404d	205	for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
cb2bf931 AS	206	pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
cb2bf931 AS	207	pci_hose_read_config_dword(hose, dev, bar, &bar_response);
c609719b WD	208
	209	if (!bar_response)
	210	continue;
	211
	212	found_mem64 = 0;
	213
	214	/* Check the BAR type and set our address mask */
f07771cc	215	if (bar_response & PCI_BASE_ADDRESS_SPACE) {
c609719b	216	bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
f07771cc	217	/* round up region base address to a multiple of size */
c609719b	218	io = ((io - 1) \| (bar_size - 1)) + 1;
f07771cc WD	219	bar_value = io;
	220	/* compute new region base address */
	221	io = io + bar_size;
	222	} else {
	223	if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
30e76d5e KG	224	PCI_BASE_ADDRESS_MEM_TYPE_64) {
	225	u32 bar_response_upper;
	226	u64 bar64;
cb2bf931 AS	227	pci_hose_write_config_dword(hose, dev, bar + 4,
	228	0xffffffff);
	229	pci_hose_read_config_dword(hose, dev, bar + 4,
	230	&bar_response_upper);
30e76d5e KG	231
30e76d5e KG	232	bar64 = ((u64)bar_response_upper << 32) \| bar_response;
c609719b	233
30e76d5e KG	234	bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
	235	found_mem64 = 1;
	236	} else {
	237	bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
	238	}
c609719b	239
f07771cc	240	/* round up region base address to multiple of size */
c609719b	241	mem = ((mem - 1) \| (bar_size - 1)) + 1;
f07771cc WD	242	bar_value = mem;
	243	/* compute new region base address */
	244	mem = mem + bar_size;
c609719b WD	245	}
	246
	247	/* Write it out and update our limit */
30e76d5e	248	pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
c609719b	249
f07771cc	250	if (found_mem64) {
c609719b	251	bar += 4;
30e76d5e	252	#ifdef CONFIG_SYS_PCI_64BIT
cb2bf931 AS	253	pci_hose_write_config_dword(hose, dev, bar,
cb2bf931 AS	254	(u32)(bar_value >> 32));
30e76d5e	255	#else
cb2bf931	256	pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
30e76d5e	257	#endif
c609719b WD	258	}
	259	}
	260
	261	/* Configure Cache Line Size Register */
cb2bf931	262	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
c609719b WD	263
c609719b WD	264	/* Configure Latency Timer */
cb2bf931	265	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
c609719b WD	266
c609719b WD	267	/* Disable interrupt line, if device says it wants to use interrupts */
cb2bf931	268	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
f07771cc	269	if (pin != 0) {
5f48d798 SG	270	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
5f48d798 SG	271	PCI_INTERRUPT_LINE_DISABLE);
c609719b WD	272	}
c609719b WD	273
cb2bf931 AS	274	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
cb2bf931 AS	275	pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
f07771cc	276	(old_command & 0xffff0000) \| command);
c609719b WD	277
	278	return 0;
	279	}
	280
	281	/*
	282	*
	283	*/
	284
	285	struct pci_config_table pci_find_config(struct pci_controller hose,
	286	unsigned short class,
	287	unsigned int vendor,
	288	unsigned int device,
	289	unsigned int bus,
	290	unsigned int dev,
	291	unsigned int func)
	292	{
	293	struct pci_config_table *table;
	294
f07771cc	295	for (table = hose->config_table; table && table->vendor; table++) {
c609719b WD	296	if ((table->vendor == PCI_ANY_ID \|\| table->vendor == vendor) &&
	297	(table->device == PCI_ANY_ID \|\| table->device == device) &&
	298	(table->class == PCI_ANY_ID \|\| table->class == class) &&
	299	(table->bus == PCI_ANY_ID \|\| table->bus == bus) &&
	300	(table->dev == PCI_ANY_ID \|\| table->dev == dev) &&
f07771cc	301	(table->func == PCI_ANY_ID \|\| table->func == func)) {
c609719b WD	302	return table;
	303	}
	304	}
	305
	306	return NULL;
	307	}
	308
	309	void pci_cfgfunc_config_device(struct pci_controller *hose,
	310	pci_dev_t dev,
	311	struct pci_config_table *entry)
	312	{
cb2bf931 AS	313	pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
cb2bf931 AS	314	entry->priv[2]);
c609719b WD	315	}
	316
	317	void pci_cfgfunc_do_nothing(struct pci_controller *hose,
	318	pci_dev_t dev, struct pci_config_table *entry)
	319	{
	320	}
	321
	322	/*
cb2bf931	323	* HJF: Changed this to return int. I think this is required
c7de829c WD	324	* to get the correct result when scanning bridges
	325	*/
	326	extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
c609719b	327
dc1da42f	328	#ifdef CONFIG_PCI_SCAN_SHOW
7b19fd6d	329	__weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
dc1da42f SR	330	{
	331	if (dev == PCI_BDF(hose->first_busno, 0, 0))
	332	return 0;
	333
	334	return 1;
	335	}
dc1da42f SR	336	#endif /* CONFIG_PCI_SCAN_SHOW */
dc1da42f SR	337
c609719b WD	338	int pci_hose_scan_bus(struct pci_controller *hose, int bus)
c609719b WD	339	{
cb2bf931	340	unsigned int sub_bus, found_multi = 0;
c609719b WD	341	unsigned short vendor, device, class;
c609719b WD	342	unsigned char header_type;
03992ac2	343	#ifndef CONFIG_PCI_PNP
c609719b	344	struct pci_config_table *cfg;
03992ac2	345	#endif
c609719b	346	pci_dev_t dev;
009884ae PT	347	#ifdef CONFIG_PCI_SCAN_SHOW
	348	static int indent = 0;
	349	#endif
c609719b WD	350
	351	sub_bus = bus;
	352
	353	for (dev = PCI_BDF(bus,0,0);
cb2bf931 AS	354	dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
	355	PCI_MAX_PCI_FUNCTIONS - 1);
	356	dev += PCI_BDF(0, 0, 1)) {
dc1da42f SR	357
	358	if (pci_skip_dev(hose, dev))
	359	continue;
c609719b WD	360
	361	if (PCI_FUNC(dev) && !found_multi)
	362	continue;
	363
	364	pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
	365
	366	pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
	367
983eb9d1 PT	368	if (vendor == 0xffff \|\| vendor == 0x0000)
983eb9d1 PT	369	continue;
c609719b	370
983eb9d1 PT	371	if (!PCI_FUNC(dev))
983eb9d1 PT	372	found_multi = header_type & 0x80;
c609719b	373
cb2bf931 AS	374	debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
cb2bf931 AS	375	PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
c609719b	376
983eb9d1 PT	377	pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
983eb9d1 PT	378	pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
c609719b	379
0991866c TH	380	#ifdef CONFIG_PCI_FIXUP_DEV
	381	board_pci_fixup_dev(hose, dev, vendor, device, class);
	382	#endif
	383
a38d216e	384	#ifdef CONFIG_PCI_SCAN_SHOW
009884ae PT	385	indent++;
	386
	387	/* Print leading space, including bus indentation */
	388	printf("%*c", indent + 1, ' ');
	389
a38d216e	390	if (pci_print_dev(hose, dev)) {
009884ae PT	391	printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
009884ae PT	392	PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
a38d216e PT	393	vendor, device, pci_class_str(class >> 8));
	394	}
	395	#endif
	396
03992ac2	397	#ifdef CONFIG_PCI_PNP
b4141195 MY	398	sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
b4141195 MY	399	sub_bus);
03992ac2	400	#else
983eb9d1 PT	401	cfg = pci_find_config(hose, class, vendor, device,
	402	PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
	403	if (cfg) {
	404	cfg->config_device(hose, dev, cfg);
b4141195 MY	405	sub_bus = max(sub_bus,
b4141195 MY	406	(unsigned int)hose->current_busno);
983eb9d1	407	}
03992ac2	408	#endif
a38d216e	409
009884ae PT	410	#ifdef CONFIG_PCI_SCAN_SHOW
	411	indent--;
	412	#endif
	413
983eb9d1 PT	414	if (hose->fixup_irq)
983eb9d1 PT	415	hose->fixup_irq(hose, dev);
c609719b WD	416	}
	417
	418	return sub_bus;
	419	}
	420
	421	int pci_hose_scan(struct pci_controller *hose)
	422	{
0da1fb03	423	#if defined(CONFIG_PCI_BOOTDELAY)
0da1fb03 AG	424	char *s;
	425	int i;
	426
8f9052fd	427	if (!gd->pcidelay_done) {
0da1fb03	428	/* wait "pcidelay" ms (if defined)... */
00caae6d	429	s = env_get("pcidelay");
0da1fb03 AG	430	if (s) {
	431	int val = simple_strtoul(s, NULL, 10);
	432	for (i = 0; i < val; i++)
	433	udelay(1000);
	434	}
8f9052fd	435	gd->pcidelay_done = 1;
0da1fb03 AG	436	}
	437	#endif /* CONFIG_PCI_BOOTDELAY */
	438
0373a7e9 TH	439	#ifdef CONFIG_PCI_SCAN_SHOW
	440	puts("PCI:\n");
	441	#endif
	442
cb2bf931 AS	443	/*
cb2bf931 AS	444	* Start scan at current_busno.
40e81add ES	445	* PCIe will start scan at first_busno+1.
40e81add ES	446	*/
cb2bf931	447	/* For legacy support, ensure current >= first */
40e81add ES	448	if (hose->first_busno > hose->current_busno)
40e81add ES	449	hose->current_busno = hose->first_busno;
c609719b WD	450	#ifdef CONFIG_PCI_PNP
	451	pciauto_config_init(hose);
	452	#endif
40e81add	453	return pci_hose_scan_bus(hose, hose->current_busno);
c609719b WD	454	}
c609719b WD	455
ad10dd9a SR	456	void pci_init(void)
ad10dd9a SR	457	{
96d61603 JS	458	hose_head = NULL;
96d61603 JS	459
ec21aee6	460	/* allow env to disable pci init/enum */
00caae6d	461	if (env_get("pcidisable") != NULL)
ec21aee6 TH	462	return;
ec21aee6 TH	463
ad10dd9a SR	464	/* now call board specific pci_init()... */
	465	pci_init_board();
	466	}
287df01e ZQ	467
	468	/* Returns the address of the requested capability structure within the
	469	* device's PCI configuration space or 0 in case the device does not
	470	* support it.
	471	* */
	472	int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
	473	int cap)
	474	{
	475	int pos;
	476	u8 hdr_type;
	477
	478	pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
	479
	480	pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
	481
	482	if (pos)
	483	pos = pci_find_cap(hose, dev, pos, cap);
	484
	485	return pos;
	486	}
	487
	488	/* Find the header pointer to the Capabilities*/
	489	int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
	490	u8 hdr_type)
	491	{
	492	u16 status;
	493
	494	pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
	495
	496	if (!(status & PCI_STATUS_CAP_LIST))
	497	return 0;
	498
	499	switch (hdr_type) {
	500	case PCI_HEADER_TYPE_NORMAL:
	501	case PCI_HEADER_TYPE_BRIDGE:
	502	return PCI_CAPABILITY_LIST;
	503	case PCI_HEADER_TYPE_CARDBUS:
	504	return PCI_CB_CAPABILITY_LIST;
	505	default:
	506	return 0;
	507	}
	508	}
	509
	510	int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
	511	{
	512	int ttl = PCI_FIND_CAP_TTL;
	513	u8 id;
	514	u8 next_pos;
	515
	516	while (ttl--) {
	517	pci_hose_read_config_byte(hose, dev, pos, &next_pos);
	518	if (next_pos < CAP_START_POS)
	519	break;
	520	next_pos &= ~3;
	521	pos = (int) next_pos;
	522	pci_hose_read_config_byte(hose, dev,
	523	pos + PCI_CAP_LIST_ID, &id);
	524	if (id == 0xff)
	525	break;
	526	if (id == cap)
	527	return pos;
	528	pos += PCI_CAP_LIST_NEXT;
	529	}
	530	return 0;
531	}
ed5b580b ML	532
	533	/**
	534	* pci_find_next_ext_capability - Find an extended capability
	535	*
	536	* Returns the address of the next matching extended capability structure
	537	* within the device's PCI configuration space or 0 if the device does
	538	* not support it. Some capabilities can occur several times, e.g., the
	539	* vendor-specific capability, and this provides a way to find them all.
	540	*/
	541	int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev,
	542	int start, int cap)
	543	{
	544	u32 header;
	545	int ttl, pos = PCI_CFG_SPACE_SIZE;
	546
	547	/* minimum 8 bytes per capability */
	548	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
	549
	550	if (start)
	551	pos = start;
	552
	553	pci_hose_read_config_dword(hose, dev, pos, &header);
	554	if (header == 0xffffffff \|\| header == 0)
	555	return 0;
	556
	557	while (ttl-- > 0) {
	558	if (PCI_EXT_CAP_ID(header) == cap && pos != start)
	559	return pos;
	560
	561	pos = PCI_EXT_CAP_NEXT(header);
	562	if (pos < PCI_CFG_SPACE_SIZE)
	563	break;
	564
	565	pci_hose_read_config_dword(hose, dev, pos, &header);
	566	if (header == 0xffffffff \|\| header == 0)
	567	break;
	568	}
	569
	570	return 0;
	571	}
	572
	573	/**
	574	* pci_hose_find_ext_capability - Find an extended capability
	575	*
	576	* Returns the address of the requested extended capability structure
	577	* within the device's PCI configuration space or 0 if the device does
	578	* not support it.
	579	*/
	580	int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev,
	581	int cap)
	582	{
	583	return pci_find_next_ext_capability(hose, dev, 0, cap);
	584	}