[u-boot.git] / drivers / i2c / sh_i2c.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2011, 2013 Renesas Solutions Corp.
 * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <[email protected]>
 *
 * NOTE: This driver should be converted to driver model before June 2017.
 * Please see doc/driver-model/i2c-howto.txt for instructions.
 */

#include <common.h>
#include <i2c.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

/* Every register is 32bit aligned, but only 8bits in size */
#define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1;
struct sh_i2c {
	ureg(icdr);
	ureg(iccr);
	ureg(icsr);
	ureg(icic);
	ureg(iccl);
	ureg(icch);
};
#undef ureg

/* ICCR */
#define SH_I2C_ICCR_ICE		(1 << 7)
#define SH_I2C_ICCR_RACK	(1 << 6)
#define SH_I2C_ICCR_RTS		(1 << 4)
#define SH_I2C_ICCR_BUSY	(1 << 2)
#define SH_I2C_ICCR_SCP		(1 << 0)

/* ICSR / ICIC */
#define SH_IC_BUSY	(1 << 4)
#define SH_IC_TACK	(1 << 2)
#define SH_IC_WAIT	(1 << 1)
#define SH_IC_DTE	(1 << 0)

#ifdef CONFIG_SH_I2C_8BIT
/* store 8th bit of iccl and icch in ICIC register */
#define SH_I2C_ICIC_ICCLB8	(1 << 7)
#define SH_I2C_ICIC_ICCHB8	(1 << 6)
#endif

static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = {
	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0,
#ifdef CONFIG_SYS_I2C_SH_BASE1
	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1,
#endif
#ifdef CONFIG_SYS_I2C_SH_BASE2
	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2,
#endif
#ifdef CONFIG_SYS_I2C_SH_BASE3
	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3,
#endif
#ifdef CONFIG_SYS_I2C_SH_BASE4
	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4,
#endif
};

static u16 iccl, icch;

#define IRQ_WAIT 1000

static void sh_irq_dte(struct sh_i2c *dev)
{
	int i;

	for (i = 0; i < IRQ_WAIT; i++) {
		if (SH_IC_DTE & readb(&dev->icsr))
			break;
		udelay(10);
	}
}

static int sh_irq_dte_with_tack(struct sh_i2c *dev)
{
	int i;

	for (i = 0; i < IRQ_WAIT; i++) {
		if (SH_IC_DTE & readb(&dev->icsr))
			break;
		if (SH_IC_TACK & readb(&dev->icsr))
			return -1;
		udelay(10);
	}
	return 0;
}

static void sh_irq_busy(struct sh_i2c *dev)
{
	int i;

	for (i = 0; i < IRQ_WAIT; i++) {
		if (!(SH_IC_BUSY & readb(&dev->icsr)))
			break;
		udelay(10);
	}
}

static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop)
{
	u8 icic = SH_IC_TACK;

	debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n",
				__func__, chip, addr, iccl, icch);
	clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
	setbits_8(&dev->iccr, SH_I2C_ICCR_ICE);

	writeb(iccl & 0xff, &dev->iccl);
	writeb(icch & 0xff, &dev->icch);
#ifdef CONFIG_SH_I2C_8BIT
	if (iccl > 0xff)
		icic |= SH_I2C_ICIC_ICCLB8;
	if (icch > 0xff)
		icic |= SH_I2C_ICIC_ICCHB8;
#endif
	writeb(icic, &dev->icic);

	writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
	sh_irq_dte(dev);

	clrbits_8(&dev->icsr, SH_IC_TACK);
	writeb(chip << 1, &dev->icdr);
	if (sh_irq_dte_with_tack(dev) != 0)
		return -1;

	writeb(addr, &dev->icdr);
	if (stop)
		writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr);

	if (sh_irq_dte_with_tack(dev) != 0)
		return -1;
	return 0;
}

static void sh_i2c_finish(struct sh_i2c *dev)
{
	writeb(0, &dev->icsr);
	clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
}

static int
sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val)
{
	int ret = -1;
	if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
		goto exit0;
	udelay(10);

	writeb(val, &dev->icdr);
	if (sh_irq_dte_with_tack(dev) != 0)
		goto exit0;

	writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr);
	if (sh_irq_dte_with_tack(dev) != 0)
		goto exit0;
	sh_irq_busy(dev);
	ret = 0;

exit0:
	sh_i2c_finish(dev);
	return ret;
}

static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr)
{
	int ret = -1;

#if defined(CONFIG_SH73A0)
	if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
		goto exit0;
#else
	if (sh_i2c_set_addr(dev, chip, addr, 1) != 0)
		goto exit0;
	udelay(100);
#endif

	writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
	sh_irq_dte(dev);

	writeb(chip << 1 | 0x01, &dev->icdr);
	if (sh_irq_dte_with_tack(dev) != 0)
		goto exit0;

	writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr);
	if (sh_irq_dte_with_tack(dev) != 0)
		goto exit0;

	ret = readb(&dev->icdr) & 0xff;

	writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr);
	readb(&dev->icdr); /* Dummy read */
	sh_irq_busy(dev);

exit0:
	sh_i2c_finish(dev);

	return ret;
}

static void
sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
	int num, denom, tmp;

	/* No i2c support prior to relocation */
	if (!(gd->flags & GD_FLG_RELOC))
		return;

	/*
	 * Calculate the value for iccl. From the data sheet:
	 * iccl = (p-clock / transfer-rate) * (L / (L + H))
	 * where L and H are the SCL low and high ratio.
	 */
	num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW;
	denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
	tmp = num * 10 / denom;
	if (tmp % 10 >= 5)
		iccl = (u16)((num/denom) + 1);
	else
		iccl = (u16)(num/denom);

	/* Calculate the value for icch. From the data sheet:
	   icch = (p clock / transfer rate) * (H / (L + H)) */
	num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
	tmp = num * 10 / denom;
	if (tmp % 10 >= 5)
		icch = (u16)((num/denom) + 1);
	else
		icch = (u16)(num/denom);

	debug("clock: %d, speed %d, iccl: %x, icch: %x\n",
			CONFIG_SH_I2C_CLOCK, speed, iccl, icch);
}

static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip,
				uint addr, int alen, u8 *data, int len)
{
	int ret, i;
	struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];

	for (i = 0; i < len; i++) {
		ret = sh_i2c_raw_read(dev, chip, addr + i);
		if (ret < 0)
			return -1;

		data[i] = ret & 0xff;
		debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
	}

	return 0;
}

static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
				int alen, u8 *data, int len)
{
	struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
	int i;

	for (i = 0; i < len; i++) {
		debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
		if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0)
			return -1;
	}
	return 0;
}

static int
sh_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
	u8 dummy[1];

	return sh_i2c_read(adap, dev, 0, 0, dummy, sizeof dummy);
}

static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap,
			unsigned int speed)
{
	struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];

	sh_i2c_finish(dev);
	sh_i2c_init(adap, speed, 0);

	return 0;
}

/*
 * Register RCAR i2c adapters
 */
U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0)
#ifdef CONFIG_SYS_I2C_SH_BASE1
U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1)
#endif
#ifdef CONFIG_SYS_I2C_SH_BASE2
U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2)
#endif
#ifdef CONFIG_SYS_I2C_SH_BASE3
U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3)
#endif
#ifdef CONFIG_SYS_I2C_SH_BASE4
U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4)
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
3dab3e0e	2	/*
b55b8eef NI	3	* Copyright (C) 2011, 2013 Renesas Solutions Corp.
b55b8eef NI	4	* Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <[email protected]>
3dab3e0e	5	*
28527096 SG	6	* NOTE: This driver should be converted to driver model before June 2017.
28527096 SG	7	* Please see doc/driver-model/i2c-howto.txt for instructions.
3dab3e0e NI	8	*/
	9
	10	#include <common.h>
2035d77d	11	#include <i2c.h>
3dab3e0e NI	12	#include <asm/io.h>
3dab3e0e NI	13
b55b8eef NI	14	DECLARE_GLOBAL_DATA_PTR;
b55b8eef NI	15
3dab3e0e NI	16	/* Every register is 32bit aligned, but only 8bits in size */
	17	#define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1;
	18	struct sh_i2c {
	19	ureg(icdr);
	20	ureg(iccr);
	21	ureg(icsr);
	22	ureg(icic);
	23	ureg(iccl);
	24	ureg(icch);
	25	};
	26	#undef ureg
	27
3dab3e0e NI	28	/* ICCR */
	29	#define SH_I2C_ICCR_ICE (1 << 7)
	30	#define SH_I2C_ICCR_RACK (1 << 6)
	31	#define SH_I2C_ICCR_RTS (1 << 4)
	32	#define SH_I2C_ICCR_BUSY (1 << 2)
	33	#define SH_I2C_ICCR_SCP (1 << 0)
	34
	35	/* ICSR / ICIC */
57d7c804	36	#define SH_IC_BUSY (1 << 4)
3dab3e0e NI	37	#define SH_IC_TACK (1 << 2)
	38	#define SH_IC_WAIT (1 << 1)
	39	#define SH_IC_DTE (1 << 0)
	40
b1af67fe TK	41	#ifdef CONFIG_SH_I2C_8BIT
	42	/* store 8th bit of iccl and icch in ICIC register */
	43	#define SH_I2C_ICIC_ICCLB8 (1 << 7)
	44	#define SH_I2C_ICIC_ICCHB8 (1 << 6)
	45	#endif
	46
2035d77d NI	47	static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = {
	48	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0,
	49	#ifdef CONFIG_SYS_I2C_SH_BASE1
	50	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1,
	51	#endif
	52	#ifdef CONFIG_SYS_I2C_SH_BASE2
	53	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2,
	54	#endif
	55	#ifdef CONFIG_SYS_I2C_SH_BASE3
	56	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3,
	57	#endif
	58	#ifdef CONFIG_SYS_I2C_SH_BASE4
	59	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4,
	60	#endif
	61	};
	62
b1af67fe	63	static u16 iccl, icch;
3dab3e0e NI	64
	65	#define IRQ_WAIT 1000
	66
2035d77d	67	static void sh_irq_dte(struct sh_i2c *dev)
3dab3e0e NI	68	{
	69	int i;
	70
2035d77d NI	71	for (i = 0; i < IRQ_WAIT; i++) {
2035d77d NI	72	if (SH_IC_DTE & readb(&dev->icsr))
3dab3e0e NI	73	break;
	74	udelay(10);
	75	}
	76	}
	77
2035d77d	78	static int sh_irq_dte_with_tack(struct sh_i2c *dev)
d042d712 TK	79	{
	80	int i;
	81
2035d77d NI	82	for (i = 0; i < IRQ_WAIT; i++) {
2035d77d NI	83	if (SH_IC_DTE & readb(&dev->icsr))
d042d712	84	break;
2035d77d	85	if (SH_IC_TACK & readb(&dev->icsr))
d042d712 TK	86	return -1;
	87	udelay(10);
	88	}
	89	return 0;
	90	}
	91
2035d77d	92	static void sh_irq_busy(struct sh_i2c *dev)
3dab3e0e NI	93	{
	94	int i;
	95
2035d77d NI	96	for (i = 0; i < IRQ_WAIT; i++) {
2035d77d NI	97	if (!(SH_IC_BUSY & readb(&dev->icsr)))
3dab3e0e NI	98	break;
	99	udelay(10);
	100	}
	101	}
	102
2035d77d	103	static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop)
3dab3e0e	104	{
d042d712	105	u8 icic = SH_IC_TACK;
b1af67fe	106
2035d77d NI	107	debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n",
	108	__func__, chip, addr, iccl, icch);
	109	clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
	110	setbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
3dab3e0e	111
2035d77d NI	112	writeb(iccl & 0xff, &dev->iccl);
2035d77d NI	113	writeb(icch & 0xff, &dev->icch);
b1af67fe TK	114	#ifdef CONFIG_SH_I2C_8BIT
	115	if (iccl > 0xff)
	116	icic \|= SH_I2C_ICIC_ICCLB8;
	117	if (icch > 0xff)
	118	icic \|= SH_I2C_ICIC_ICCHB8;
	119	#endif
2035d77d	120	writeb(icic, &dev->icic);
3dab3e0e	121
2035d77d NI	122	writeb((SH_I2C_ICCR_ICE\|SH_I2C_ICCR_RTS\|SH_I2C_ICCR_BUSY), &dev->iccr);
2035d77d NI	123	sh_irq_dte(dev);
3dab3e0e	124
2035d77d NI	125	clrbits_8(&dev->icsr, SH_IC_TACK);
	126	writeb(chip << 1, &dev->icdr);
	127	if (sh_irq_dte_with_tack(dev) != 0)
d042d712	128	return -1;
3dab3e0e	129
2035d77d	130	writeb(addr, &dev->icdr);
3dab3e0e	131	if (stop)
2035d77d	132	writeb((SH_I2C_ICCR_ICE\|SH_I2C_ICCR_RTS), &dev->iccr);
3dab3e0e	133
2035d77d	134	if (sh_irq_dte_with_tack(dev) != 0)
d042d712 TK	135	return -1;
d042d712 TK	136	return 0;
3dab3e0e NI	137	}
3dab3e0e NI	138
2035d77d	139	static void sh_i2c_finish(struct sh_i2c *dev)
3dab3e0e	140	{
2035d77d NI	141	writeb(0, &dev->icsr);
2035d77d NI	142	clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
3dab3e0e NI	143	}
3dab3e0e NI	144
2035d77d NI	145	static int
2035d77d NI	146	sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val)
3dab3e0e	147	{
0e5fb33c	148	int ret = -1;
2035d77d	149	if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
0e5fb33c	150	goto exit0;
3dab3e0e NI	151	udelay(10);
3dab3e0e NI	152
2035d77d NI	153	writeb(val, &dev->icdr);
2035d77d NI	154	if (sh_irq_dte_with_tack(dev) != 0)
0e5fb33c	155	goto exit0;
3dab3e0e	156
2035d77d NI	157	writeb((SH_I2C_ICCR_ICE \| SH_I2C_ICCR_RTS), &dev->iccr);
2035d77d NI	158	if (sh_irq_dte_with_tack(dev) != 0)
0e5fb33c	159	goto exit0;
2035d77d	160	sh_irq_busy(dev);
0e5fb33c	161	ret = 0;
2035d77d	162
0e5fb33c	163	exit0:
2035d77d	164	sh_i2c_finish(dev);
0e5fb33c	165	return ret;
3dab3e0e NI	166	}
3dab3e0e NI	167
2035d77d	168	static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr)
3dab3e0e	169	{
0e5fb33c	170	int ret = -1;
3dab3e0e	171
3ce2703d	172	#if defined(CONFIG_SH73A0)
2035d77d	173	if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
0e5fb33c	174	goto exit0;
3ce2703d	175	#else
2035d77d	176	if (sh_i2c_set_addr(dev, chip, addr, 1) != 0)
0e5fb33c	177	goto exit0;
3dab3e0e	178	udelay(100);
3ce2703d	179	#endif
3dab3e0e	180
2035d77d NI	181	writeb((SH_I2C_ICCR_ICE\|SH_I2C_ICCR_RTS\|SH_I2C_ICCR_BUSY), &dev->iccr);
2035d77d NI	182	sh_irq_dte(dev);
3dab3e0e	183
2035d77d NI	184	writeb(chip << 1 \| 0x01, &dev->icdr);
2035d77d NI	185	if (sh_irq_dte_with_tack(dev) != 0)
0e5fb33c	186	goto exit0;
3dab3e0e	187
2035d77d NI	188	writeb((SH_I2C_ICCR_ICE\|SH_I2C_ICCR_SCP), &dev->iccr);
2035d77d NI	189	if (sh_irq_dte_with_tack(dev) != 0)
0e5fb33c	190	goto exit0;
3dab3e0e	191
2035d77d NI	192	ret = readb(&dev->icdr) & 0xff;
	193
	194	writeb((SH_I2C_ICCR_ICE\|SH_I2C_ICCR_RACK), &dev->iccr);
	195	readb(&dev->icdr); /* Dummy read */
	196	sh_irq_busy(dev);
3dab3e0e	197
0e5fb33c	198	exit0:
2035d77d	199	sh_i2c_finish(dev);
3dab3e0e NI	200
	201	return ret;
	202	}
	203
2035d77d NI	204	static void
2035d77d NI	205	sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
3dab3e0e NI	206	{
	207	int num, denom, tmp;
	208
b55b8eef NI	209	/* No i2c support prior to relocation */
	210	if (!(gd->flags & GD_FLG_RELOC))
	211	return;
	212
3dab3e0e NI	213	/*
	214	* Calculate the value for iccl. From the data sheet:
	215	* iccl = (p-clock / transfer-rate) * (L / (L + H))
	216	* where L and H are the SCL low and high ratio.
	217	*/
	218	num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW;
	219	denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
	220	tmp = num * 10 / denom;
	221	if (tmp % 10 >= 5)
b1af67fe	222	iccl = (u16)((num/denom) + 1);
3dab3e0e	223	else
b1af67fe	224	iccl = (u16)(num/denom);
3dab3e0e NI	225
	226	/* Calculate the value for icch. From the data sheet:
	227	icch = (p clock / transfer rate) * (H / (L + H)) */
	228	num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
	229	tmp = num * 10 / denom;
	230	if (tmp % 10 >= 5)
b1af67fe	231	icch = (u16)((num/denom) + 1);
3dab3e0e	232	else
b1af67fe	233	icch = (u16)(num/denom);
2035d77d NI	234
	235	debug("clock: %d, speed %d, iccl: %x, icch: %x\n",
	236	CONFIG_SH_I2C_CLOCK, speed, iccl, icch);
3dab3e0e NI	237	}
3dab3e0e NI	238
2035d77d NI	239	static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip,
2035d77d NI	240	uint addr, int alen, u8 *data, int len)
3dab3e0e	241	{
2035d77d NI	242	int ret, i;
	243	struct sh_i2c dev = (struct sh_i2c )i2c_dev[adap->hwadapnr];
	244
	245	for (i = 0; i < len; i++) {
	246	ret = sh_i2c_raw_read(dev, chip, addr + i);
0e5fb33c TK	247	if (ret < 0)
0e5fb33c TK	248	return -1;
2035d77d NI	249
	250	data[i] = ret & 0xff;
	251	debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
0e5fb33c	252	}
2035d77d	253
3dab3e0e NI	254	return 0;
	255	}
	256
2035d77d NI	257	static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
2035d77d NI	258	int alen, u8 *data, int len)
3dab3e0e	259	{
2035d77d NI	260	struct sh_i2c dev = (struct sh_i2c )i2c_dev[adap->hwadapnr];
	261	int i;
	262
	263	for (i = 0; i < len; i++) {
	264	debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
	265	if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0)
0e5fb33c	266	return -1;
2035d77d	267	}
3dab3e0e NI	268	return 0;
	269	}
	270
2035d77d NI	271	static int
2035d77d NI	272	sh_i2c_probe(struct i2c_adapter *adap, u8 dev)
3dab3e0e	273	{
7a657689 TK	274	u8 dummy[1];
	275
	276	return sh_i2c_read(adap, dev, 0, 0, dummy, sizeof dummy);
2035d77d	277	}
d042d712	278
2035d77d NI	279	static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap,
	280	unsigned int speed)
	281	{
	282	struct sh_i2c dev = (struct sh_i2c )i2c_dev[adap->hwadapnr];
	283
	284	sh_i2c_finish(dev);
	285	sh_i2c_init(adap, speed, 0);
	286
	287	return 0;
3dab3e0e	288	}
2035d77d NI	289
	290	/*
	291	* Register RCAR i2c adapters
	292	*/
	293	U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
	294	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0)
	295	#ifdef CONFIG_SYS_I2C_SH_BASE1
	296	U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
	297	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1)
	298	#endif
	299	#ifdef CONFIG_SYS_I2C_SH_BASE2
	300	U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
	301	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2)
	302	#endif
	303	#ifdef CONFIG_SYS_I2C_SH_BASE3
	304	U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
	305	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3)
	306	#endif
	307	#ifdef CONFIG_SYS_I2C_SH_BASE4
	308	U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
	309	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4)
	310	#endif