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[u-boot.git] / drivers / i2c / mv_i2c.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
43d9616c
WD
2/*
3 * (C) Copyright 2000
4 * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
5 *
6 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2003 Pengutronix e.K.
10 * Robert Schwebel <r.schwebel@pengutronix.de>
11 *
3df619ec
LW
12 * (C) Copyright 2011 Marvell Inc.
13 * Lei Wen <leiwen@marvell.com>
14 *
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15 * Back ported to the 8xx platform (from the 8260 platform) by
16 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
17 */
18
43d9616c 19#include <common.h>
0c0f719a 20#include <dm.h>
43d9616c 21#include <i2c.h>
7b46ee52 22#include <asm/io.h>
3df619ec 23#include "mv_i2c.h"
43d9616c 24
43d9616c 25/* All transfers are described by this data structure */
fffff726 26struct mv_i2c_msg {
43d9616c 27 u8 condition;
8bde7f77
WD
28 u8 acknack;
29 u8 direction;
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30 u8 data;
31};
32
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SR
33#ifdef CONFIG_ARMADA_3700
34/* Armada 3700 has no padding between the registers */
35struct mv_i2c {
36 u32 ibmr;
37 u32 idbr;
38 u32 icr;
39 u32 isr;
40 u32 isar;
41};
42#else
3df619ec
LW
43struct mv_i2c {
44 u32 ibmr;
45 u32 pad0;
46 u32 idbr;
47 u32 pad1;
48 u32 icr;
49 u32 pad2;
50 u32 isr;
51 u32 pad3;
52 u32 isar;
53};
0c0f719a
SR
54#endif
55
56/*
57 * Dummy implementation that can be overwritten by a board
58 * specific function
59 */
60__weak void i2c_clk_enable(void)
61{
62}
3df619ec 63
68432c27 64/*
3df619ec 65 * i2c_reset: - reset the host controller
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66 *
67 */
7b46ee52 68static void i2c_reset(struct mv_i2c *base)
43d9616c 69{
9ad5a007
SR
70 u32 icr_mode;
71
72 /* Save bus mode (standard or fast speed) for later use */
73 icr_mode = readl(&base->icr) & ICR_MODE_MASK;
3df619ec
LW
74 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
75 writel(readl(&base->icr) | ICR_UR, &base->icr); /* reset the unit */
8bde7f77 76 udelay(100);
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LW
77 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
78
79 i2c_clk_enable();
80
81 writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */
9ad5a007
SR
82 /* set control reg values */
83 writel(I2C_ICR_INIT | icr_mode, &base->icr);
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LW
84 writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */
85 writel(readl(&base->icr) | ICR_IUE, &base->icr); /* enable unit */
8bde7f77 86 udelay(100);
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87}
88
68432c27 89/*
8bde7f77 90 * i2c_isr_set_cleared: - wait until certain bits of the I2C status register
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91 * are set and cleared
92 *
ba70d6a4 93 * @return: 1 in case of success, 0 means timeout (no match within 10 ms).
43d9616c 94 */
7b46ee52 95static int i2c_isr_set_cleared(struct mv_i2c *base, unsigned long set_mask,
68432c27 96 unsigned long cleared_mask)
43d9616c 97{
3df619ec 98 int timeout = 1000, isr;
43d9616c 99
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LW
100 do {
101 isr = readl(&base->isr);
68432c27
LW
102 udelay(10);
103 if (timeout-- < 0)
104 return 0;
3df619ec
LW
105 } while (((isr & set_mask) != set_mask)
106 || ((isr & cleared_mask) != 0));
43d9616c 107
8bde7f77 108 return 1;
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109}
110
68432c27 111/*
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112 * i2c_transfer: - Transfer one byte over the i2c bus
113 *
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114 * This function can tranfer a byte over the i2c bus in both directions.
115 * It is used by the public API functions.
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116 *
117 * @return: 0: transfer successful
118 * -1: message is empty
119 * -2: transmit timeout
120 * -3: ACK missing
121 * -4: receive timeout
122 * -5: illegal parameters
123 * -6: bus is busy and couldn't be aquired
8bde7f77 124 */
7b46ee52 125static int i2c_transfer(struct mv_i2c *base, struct mv_i2c_msg *msg)
43d9616c
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126{
127 int ret;
128
8bde7f77 129 if (!msg)
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130 goto transfer_error_msg_empty;
131
68432c27 132 switch (msg->direction) {
43d9616c 133 case I2C_WRITE:
43d9616c 134 /* check if bus is not busy */
7b46ee52 135 if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
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136 goto transfer_error_bus_busy;
137
138 /* start transmission */
3df619ec
LW
139 writel(readl(&base->icr) & ~ICR_START, &base->icr);
140 writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
141 writel(msg->data, &base->idbr);
3ba8bf7c 142 if (msg->condition == I2C_COND_START)
3df619ec 143 writel(readl(&base->icr) | ICR_START, &base->icr);
3ba8bf7c 144 if (msg->condition == I2C_COND_STOP)
3df619ec 145 writel(readl(&base->icr) | ICR_STOP, &base->icr);
3ba8bf7c 146 if (msg->acknack == I2C_ACKNAK_SENDNAK)
3df619ec 147 writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
3ba8bf7c 148 if (msg->acknack == I2C_ACKNAK_SENDACK)
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LW
149 writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
150 writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
151 writel(readl(&base->icr) | ICR_TB, &base->icr);
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152
153 /* transmit register empty? */
7b46ee52 154 if (!i2c_isr_set_cleared(base, ISR_ITE, 0))
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155 goto transfer_error_transmit_timeout;
156
157 /* clear 'transmit empty' state */
3df619ec 158 writel(readl(&base->isr) | ISR_ITE, &base->isr);
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159
160 /* wait for ACK from slave */
161 if (msg->acknack == I2C_ACKNAK_WAITACK)
7b46ee52 162 if (!i2c_isr_set_cleared(base, 0, ISR_ACKNAK))
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163 goto transfer_error_ack_missing;
164 break;
165
166 case I2C_READ:
167
168 /* check if bus is not busy */
7b46ee52 169 if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
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170 goto transfer_error_bus_busy;
171
172 /* start receive */
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LW
173 writel(readl(&base->icr) & ~ICR_START, &base->icr);
174 writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
3ba8bf7c 175 if (msg->condition == I2C_COND_START)
3df619ec 176 writel(readl(&base->icr) | ICR_START, &base->icr);
3ba8bf7c 177 if (msg->condition == I2C_COND_STOP)
3df619ec 178 writel(readl(&base->icr) | ICR_STOP, &base->icr);
3ba8bf7c 179 if (msg->acknack == I2C_ACKNAK_SENDNAK)
3df619ec 180 writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
3ba8bf7c 181 if (msg->acknack == I2C_ACKNAK_SENDACK)
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LW
182 writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
183 writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
184 writel(readl(&base->icr) | ICR_TB, &base->icr);
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185
186 /* receive register full? */
7b46ee52 187 if (!i2c_isr_set_cleared(base, ISR_IRF, 0))
8bde7f77 188 goto transfer_error_receive_timeout;
43d9616c 189
3df619ec 190 msg->data = readl(&base->idbr);
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191
192 /* clear 'receive empty' state */
3df619ec 193 writel(readl(&base->isr) | ISR_IRF, &base->isr);
43d9616c 194 break;
43d9616c 195 default:
43d9616c 196 goto transfer_error_illegal_param;
43d9616c
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197 }
198
8bde7f77 199 return 0;
43d9616c 200
8bde7f77 201transfer_error_msg_empty:
8eff909a
SR
202 debug("i2c_transfer: error: 'msg' is empty\n");
203 ret = -1;
204 goto i2c_transfer_finish;
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205
206transfer_error_transmit_timeout:
8eff909a
SR
207 debug("i2c_transfer: error: transmit timeout\n");
208 ret = -2;
209 goto i2c_transfer_finish;
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210
211transfer_error_ack_missing:
8eff909a
SR
212 debug("i2c_transfer: error: ACK missing\n");
213 ret = -3;
214 goto i2c_transfer_finish;
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215
216transfer_error_receive_timeout:
8eff909a
SR
217 debug("i2c_transfer: error: receive timeout\n");
218 ret = -4;
219 goto i2c_transfer_finish;
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220
221transfer_error_illegal_param:
8eff909a
SR
222 debug("i2c_transfer: error: illegal parameters\n");
223 ret = -5;
224 goto i2c_transfer_finish;
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225
226transfer_error_bus_busy:
8eff909a
SR
227 debug("i2c_transfer: error: bus is busy\n");
228 ret = -6;
229 goto i2c_transfer_finish;
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230
231i2c_transfer_finish:
8eff909a 232 debug("i2c_transfer: ISR: 0x%04x\n", readl(&base->isr));
7b46ee52 233 i2c_reset(base);
8eff909a 234 return ret;
43d9616c
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235}
236
0c0f719a 237static int __i2c_read(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
7b46ee52 238 uchar *buffer, int len)
43d9616c 239{
fffff726 240 struct mv_i2c_msg msg;
43d9616c 241
8eff909a 242 debug("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
0c0f719a 243 "len=0x%02x)\n", chip, *addr, alen, len);
43d9616c 244
85f03f0e 245 if (len == 0) {
246 printf("reading zero byte is invalid\n");
247 return -EINVAL;
248 }
249
7b46ee52 250 i2c_reset(base);
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251
252 /* dummy chip address write */
8eff909a 253 debug("i2c_read: dummy chip address write\n");
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254 msg.condition = I2C_COND_START;
255 msg.acknack = I2C_ACKNAK_WAITACK;
256 msg.direction = I2C_WRITE;
68432c27
LW
257 msg.data = (chip << 1);
258 msg.data &= 0xFE;
7b46ee52 259 if (i2c_transfer(base, &msg))
68432c27 260 return -1;
8bde7f77 261
43d9616c 262 /*
8bde7f77
WD
263 * send memory address bytes;
264 * alen defines how much bytes we have to send.
43d9616c 265 */
43d9616c 266 while (--alen >= 0) {
0c0f719a
SR
267 debug("i2c_read: send address byte %02x (alen=%d)\n",
268 *addr, alen);
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WD
269 msg.condition = I2C_COND_NORMAL;
270 msg.acknack = I2C_ACKNAK_WAITACK;
271 msg.direction = I2C_WRITE;
77466267 272 msg.data = addr[alen];
7b46ee52 273 if (i2c_transfer(base, &msg))
68432c27 274 return -1;
43d9616c 275 }
8bde7f77 276
43d9616c 277 /* start read sequence */
8eff909a 278 debug("i2c_read: start read sequence\n");
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279 msg.condition = I2C_COND_START;
280 msg.acknack = I2C_ACKNAK_WAITACK;
281 msg.direction = I2C_WRITE;
282 msg.data = (chip << 1);
283 msg.data |= 0x01;
7b46ee52 284 if (i2c_transfer(base, &msg))
68432c27 285 return -1;
43d9616c
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286
287 /* read bytes; send NACK at last byte */
288 while (len--) {
68432c27 289 if (len == 0) {
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290 msg.condition = I2C_COND_STOP;
291 msg.acknack = I2C_ACKNAK_SENDNAK;
292 } else {
293 msg.condition = I2C_COND_NORMAL;
294 msg.acknack = I2C_ACKNAK_SENDACK;
295 }
296
297 msg.direction = I2C_READ;
298 msg.data = 0x00;
7b46ee52 299 if (i2c_transfer(base, &msg))
68432c27 300 return -1;
43d9616c 301
ba70d6a4 302 *buffer = msg.data;
0c0f719a
SR
303 debug("i2c_read: reading byte (%p)=0x%02x\n",
304 buffer, *buffer);
ba70d6a4 305 buffer++;
43d9616c
WD
306 }
307
7b46ee52 308 i2c_reset(base);
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309
310 return 0;
311}
312
0c0f719a 313static int __i2c_write(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
7b46ee52 314 uchar *buffer, int len)
43d9616c 315{
fffff726 316 struct mv_i2c_msg msg;
43d9616c 317
8eff909a 318 debug("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
0c0f719a 319 "len=0x%02x)\n", chip, *addr, alen, len);
43d9616c 320
7b46ee52 321 i2c_reset(base);
43d9616c
WD
322
323 /* chip address write */
8eff909a 324 debug("i2c_write: chip address write\n");
43d9616c
WD
325 msg.condition = I2C_COND_START;
326 msg.acknack = I2C_ACKNAK_WAITACK;
327 msg.direction = I2C_WRITE;
68432c27
LW
328 msg.data = (chip << 1);
329 msg.data &= 0xFE;
7b46ee52 330 if (i2c_transfer(base, &msg))
68432c27 331 return -1;
8bde7f77 332
43d9616c 333 /*
8bde7f77
WD
334 * send memory address bytes;
335 * alen defines how much bytes we have to send.
43d9616c 336 */
43d9616c 337 while (--alen >= 0) {
0c0f719a
SR
338 debug("i2c_read: send address byte %02x (alen=%d)\n",
339 *addr, alen);
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WD
340 msg.condition = I2C_COND_NORMAL;
341 msg.acknack = I2C_ACKNAK_WAITACK;
342 msg.direction = I2C_WRITE;
77466267 343 msg.data = addr[alen];
7b46ee52 344 if (i2c_transfer(base, &msg))
68432c27 345 return -1;
43d9616c 346 }
8bde7f77 347
43d9616c
WD
348 /* write bytes; send NACK at last byte */
349 while (len--) {
0c0f719a
SR
350 debug("i2c_write: writing byte (%p)=0x%02x\n",
351 buffer, *buffer);
43d9616c 352
68432c27 353 if (len == 0)
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WD
354 msg.condition = I2C_COND_STOP;
355 else
356 msg.condition = I2C_COND_NORMAL;
357
358 msg.acknack = I2C_ACKNAK_WAITACK;
359 msg.direction = I2C_WRITE;
360 msg.data = *(buffer++);
8bde7f77 361
7b46ee52 362 if (i2c_transfer(base, &msg))
68432c27 363 return -1;
43d9616c
WD
364 }
365
7b46ee52 366 i2c_reset(base);
43d9616c
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367
368 return 0;
43d9616c 369}
7b46ee52 370
0c0f719a
SR
371#ifndef CONFIG_DM_I2C
372
7b46ee52
SR
373static struct mv_i2c *base_glob;
374
375static void i2c_board_init(struct mv_i2c *base)
376{
377#ifdef CONFIG_SYS_I2C_INIT_BOARD
378 u32 icr;
379 /*
380 * call board specific i2c bus reset routine before accessing the
381 * environment, which might be in a chip on that bus. For details
382 * about this problem see doc/I2C_Edge_Conditions.
383 *
384 * disable I2C controller first, otherwhise it thinks we want to
385 * talk to the slave port...
386 */
387 icr = readl(&base->icr);
388 writel(readl(&base->icr) & ~(ICR_SCLE | ICR_IUE), &base->icr);
389
390 i2c_init_board();
391
392 writel(icr, &base->icr);
393#endif
394}
395
396#ifdef CONFIG_I2C_MULTI_BUS
397static unsigned long i2c_regs[CONFIG_MV_I2C_NUM] = CONFIG_MV_I2C_REG;
398static unsigned int bus_initialized[CONFIG_MV_I2C_NUM];
399static unsigned int current_bus;
400
401int i2c_set_bus_num(unsigned int bus)
402{
403 if ((bus < 0) || (bus >= CONFIG_MV_I2C_NUM)) {
404 printf("Bad bus: %d\n", bus);
405 return -1;
406 }
407
408 base_glob = (struct mv_i2c *)i2c_regs[bus];
409 current_bus = bus;
410
411 if (!bus_initialized[current_bus]) {
412 i2c_board_init(base_glob);
413 bus_initialized[current_bus] = 1;
414 }
415
416 return 0;
417}
418
419unsigned int i2c_get_bus_num(void)
420{
421 return current_bus;
422}
423#endif
424
425/* API Functions */
426void i2c_init(int speed, int slaveaddr)
427{
9ad5a007
SR
428 u32 val;
429
7b46ee52
SR
430#ifdef CONFIG_I2C_MULTI_BUS
431 current_bus = 0;
432 base_glob = (struct mv_i2c *)i2c_regs[current_bus];
433#else
434 base_glob = (struct mv_i2c *)CONFIG_MV_I2C_REG;
435#endif
436
9ad5a007
SR
437 if (speed > 100000)
438 val = ICR_FM;
439 else
440 val = ICR_SM;
441 clrsetbits_le32(&base_glob->icr, ICR_MODE_MASK, val);
442
7b46ee52
SR
443 i2c_board_init(base_glob);
444}
445
0c0f719a
SR
446static int __i2c_probe_chip(struct mv_i2c *base, uchar chip)
447{
448 struct mv_i2c_msg msg;
449
450 i2c_reset(base);
451
452 msg.condition = I2C_COND_START;
453 msg.acknack = I2C_ACKNAK_WAITACK;
454 msg.direction = I2C_WRITE;
455 msg.data = (chip << 1) + 1;
456 if (i2c_transfer(base, &msg))
457 return -1;
458
459 msg.condition = I2C_COND_STOP;
460 msg.acknack = I2C_ACKNAK_SENDNAK;
461 msg.direction = I2C_READ;
462 msg.data = 0x00;
463 if (i2c_transfer(base, &msg))
464 return -1;
465
466 return 0;
467}
468
7b46ee52
SR
469/*
470 * i2c_probe: - Test if a chip answers for a given i2c address
471 *
472 * @chip: address of the chip which is searched for
473 * @return: 0 if a chip was found, -1 otherwhise
474 */
475int i2c_probe(uchar chip)
476{
477 return __i2c_probe_chip(base_glob, chip);
478}
479
480/*
481 * i2c_read: - Read multiple bytes from an i2c device
482 *
483 * The higher level routines take into account that this function is only
484 * called with len < page length of the device (see configuration file)
485 *
486 * @chip: address of the chip which is to be read
487 * @addr: i2c data address within the chip
488 * @alen: length of the i2c data address (1..2 bytes)
489 * @buffer: where to write the data
490 * @len: how much byte do we want to read
491 * @return: 0 in case of success
492 */
493int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
494{
0c0f719a
SR
495 u8 addr_bytes[4];
496
497 addr_bytes[0] = (addr >> 0) & 0xFF;
498 addr_bytes[1] = (addr >> 8) & 0xFF;
499 addr_bytes[2] = (addr >> 16) & 0xFF;
500 addr_bytes[3] = (addr >> 24) & 0xFF;
501
502 return __i2c_read(base_glob, chip, addr_bytes, alen, buffer, len);
7b46ee52
SR
503}
504
505/*
506 * i2c_write: - Write multiple bytes to an i2c device
507 *
508 * The higher level routines take into account that this function is only
509 * called with len < page length of the device (see configuration file)
510 *
511 * @chip: address of the chip which is to be written
512 * @addr: i2c data address within the chip
513 * @alen: length of the i2c data address (1..2 bytes)
514 * @buffer: where to find the data to be written
515 * @len: how much byte do we want to read
516 * @return: 0 in case of success
517 */
518int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
519{
0c0f719a
SR
520 u8 addr_bytes[4];
521
522 addr_bytes[0] = (addr >> 0) & 0xFF;
523 addr_bytes[1] = (addr >> 8) & 0xFF;
524 addr_bytes[2] = (addr >> 16) & 0xFF;
525 addr_bytes[3] = (addr >> 24) & 0xFF;
526
527 return __i2c_write(base_glob, chip, addr_bytes, alen, buffer, len);
528}
529
530#else /* CONFIG_DM_I2C */
531
532struct mv_i2c_priv {
533 struct mv_i2c *base;
534};
535
536static int mv_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
537{
538 struct mv_i2c_priv *i2c = dev_get_priv(bus);
539 struct i2c_msg *dmsg, *omsg, dummy;
540
541 memset(&dummy, 0, sizeof(struct i2c_msg));
542
543 /*
544 * We expect either two messages (one with an offset and one with the
545 * actual data) or one message (just data or offset/data combined)
546 */
547 if (nmsgs > 2 || nmsgs == 0) {
548 debug("%s: Only one or two messages are supported.", __func__);
549 return -1;
550 }
551
552 omsg = nmsgs == 1 ? &dummy : msg;
553 dmsg = nmsgs == 1 ? msg : msg + 1;
554
555 if (dmsg->flags & I2C_M_RD)
556 return __i2c_read(i2c->base, dmsg->addr, omsg->buf,
557 omsg->len, dmsg->buf, dmsg->len);
558 else
559 return __i2c_write(i2c->base, dmsg->addr, omsg->buf,
560 omsg->len, dmsg->buf, dmsg->len);
7b46ee52 561}
0c0f719a 562
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563static int mv_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
564{
565 struct mv_i2c_priv *priv = dev_get_priv(bus);
566 u32 val;
567
568 if (speed > 100000)
569 val = ICR_FM;
570 else
571 val = ICR_SM;
572 clrsetbits_le32(&priv->base->icr, ICR_MODE_MASK, val);
573
574 return 0;
575}
576
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577static int mv_i2c_probe(struct udevice *bus)
578{
579 struct mv_i2c_priv *priv = dev_get_priv(bus);
580
a821c4af 581 priv->base = (void *)devfdt_get_addr_ptr(bus);
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582
583 return 0;
584}
585
586static const struct dm_i2c_ops mv_i2c_ops = {
587 .xfer = mv_i2c_xfer,
9ad5a007 588 .set_bus_speed = mv_i2c_set_bus_speed,
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589};
590
591static const struct udevice_id mv_i2c_ids[] = {
592 { .compatible = "marvell,armada-3700-i2c" },
593 { }
594};
595
596U_BOOT_DRIVER(i2c_mv) = {
597 .name = "i2c_mv",
598 .id = UCLASS_I2C,
599 .of_match = mv_i2c_ids,
600 .probe = mv_i2c_probe,
601 .priv_auto_alloc_size = sizeof(struct mv_i2c_priv),
602 .ops = &mv_i2c_ops,
603};
604#endif /* CONFIG_DM_I2C */
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