projects / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 0f83b365 | 2 | /* |
| 2a4058c2 | 3 | * Aries M53 DRAM init values |
| 0f83b365 MV |
4 | * Copyright (C) 2012-2013 Marek Vasut <[email protected]> |
| 5 | * | |
| 03bf9d58 | 6 | * Refer doc/README.imximage for more details about how-to configure |
| 0f83b365 MV |
7 | * and create imximage boot image |
| 8 | * | |
| 9 | * The syntax is taken as close as possible with the kwbimage | |
| 10 | */ | |
| 552a848e | 11 | #include <asm/mach-imx/imximage.cfg> |
| 0f83b365 MV |
12 | |
| 13 | /* image version */ | |
| 14 | IMAGE_VERSION 2 | |
| 15 | ||
| 16 | ||
| 17 | /* Boot Offset 0x400, valid for both SD and NAND boot. */ | |
| 18 | BOOT_OFFSET FLASH_OFFSET_STANDARD | |
| 19 | ||
| 20 | /* | |
| 21 | * Device Configuration Data (DCD) | |
| 22 | * | |
| 23 | * Each entry must have the format: | |
| 24 | * Addr-type Address Value | |
| 25 | * | |
| 26 | * where: | |
| 27 | * Addr-type register length (1,2 or 4 bytes) | |
| 28 | * Address absolute address of the register | |
| 29 | * value value to be stored in the register | |
| 30 | */ | |
| 31 | DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */ | |
| 32 | DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */ | |
| 33 | DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */ | |
| 34 | DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */ | |
| 35 | ||
| 36 | DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */ | |
| 37 | DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */ | |
| 38 | DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */ | |
| 39 | ||
| 40 | DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */ | |
| 41 | DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */ | |
| 42 | DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */ | |
| 43 | ||
| 44 | DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS */ | |
| 45 | DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1 */ | |
| 46 | DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */ | |
| 47 | ||
| 48 | DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS */ | |
| 49 | DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0 */ | |
| 50 | DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */ | |
| 51 | ||
| 52 | DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK_0 */ | |
| 53 | DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK_1 */ | |
| 54 | ||
| 55 | DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS */ | |
| 56 | DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS */ | |
| 57 | DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDDS */ | |
| 58 | DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */ | |
| 59 | ||
| 60 | DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */ | |
| 61 | DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */ | |
| 62 | ||
| 63 | /* ESDCTL */ | |
| 64 | DATA 4 0x63fd9088 0x32383535 | |
| 65 | DATA 4 0x63fd9090 0x40383538 | |
| 66 | DATA 4 0x63fd907c 0x0136014d | |
| 67 | DATA 4 0x63fd9080 0x01510141 | |
| 68 | ||
| 69 | DATA 4 0x63fd9018 0x00011740 | |
| 70 | DATA 4 0x63fd9000 0xc3190000 | |
| 71 | DATA 4 0x63fd900c 0x555952e3 | |
| 72 | DATA 4 0x63fd9010 0xb68e8b63 | |
| 73 | DATA 4 0x63fd9014 0x01ff00db | |
| 74 | DATA 4 0x63fd902c 0x000026d2 | |
| 75 | DATA 4 0x63fd9030 0x009f0e21 | |
| 76 | DATA 4 0x63fd9008 0x12273030 | |
| 77 | DATA 4 0x63fd9004 0x0002002d | |
| 78 | DATA 4 0x63fd901c 0x00008032 | |
| 79 | DATA 4 0x63fd901c 0x00008033 | |
| 80 | DATA 4 0x63fd901c 0x00028031 | |
| 81 | DATA 4 0x63fd901c 0x092080b0 | |
| 82 | DATA 4 0x63fd901c 0x04008040 | |
| 83 | DATA 4 0x63fd901c 0x0000803a | |
| 84 | DATA 4 0x63fd901c 0x0000803b | |
| 85 | DATA 4 0x63fd901c 0x00028039 | |
| 86 | DATA 4 0x63fd901c 0x09208138 | |
| 87 | DATA 4 0x63fd901c 0x04008048 | |
| 88 | DATA 4 0x63fd9020 0x00001800 | |
| 89 | DATA 4 0x63fd9040 0x04b80003 | |
| 90 | DATA 4 0x63fd9058 0x00022227 | |
| 91 | DATA 4 0x63fd901c 0x00000000 |