[u-boot.git] / board / CarMediaLab / flea3 / flea3.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2007, Guennadi Liakhovetski <[email protected]>
 *
 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
 *
 * Copyright (C) 2011, Stefano Babic <[email protected]>
 */

#include <common.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux-mx35.h>
#include <i2c.h>
#include <linux/types.h>
#include <asm/gpio.h>
#include <asm/arch/sys_proto.h>
#include <netdev.h>
#include <fdt_support.h>
#include <mtd_node.h>
#include <jffs2/load_kernel.h>

#ifndef CONFIG_BOARD_EARLY_INIT_F
#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
#endif

#define CCM_CCMR_CONFIG		0x003F4208

#define ESDCTL_DDR2_CONFIG	0x007FFC3F

static inline void dram_wait(unsigned int count)
{
	volatile unsigned int wait = count;

	while (wait--)
		;
}

DECLARE_GLOBAL_DATA_PTR;

int dram_init(void)
{
	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
		PHYS_SDRAM_1_SIZE);

	return 0;
}

static void board_setup_sdram(void)
{
	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;

	/* Initialize with default values both CSD0/1 */
	writel(0x2000, &esdc->esdctl0);
	writel(0x2000, &esdc->esdctl1);


	mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
			     13, 10, 2, 0x8080);
}

static void setup_iomux_uart3(void)
{
	static const iomux_v3_cfg_t uart3_pads[] = {
		MX35_PAD_RTS2__UART3_RXD_MUX,
		MX35_PAD_CTS2__UART3_TXD_MUX,
	};

	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
}

#define I2C_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)

static void setup_iomux_i2c(void)
{
	static const iomux_v3_cfg_t i2c_pads[] = {
		NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
		NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),

		NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL),
		NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL),
	};

	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
}


static void setup_iomux_spi(void)
{
	static const iomux_v3_cfg_t spi_pads[] = {
		MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
		MX35_PAD_CSPI1_MISO__CSPI1_MISO,
		MX35_PAD_CSPI1_SS0__CSPI1_SS0,
		MX35_PAD_CSPI1_SS1__CSPI1_SS1,
		MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
	};

	imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
}

static void setup_iomux_fec(void)
{
	static const iomux_v3_cfg_t fec_pads[] = {
		MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
		MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
		MX35_PAD_FEC_RX_DV__FEC_RX_DV,
		MX35_PAD_FEC_COL__FEC_COL,
		MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
		MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
		MX35_PAD_FEC_TX_EN__FEC_TX_EN,
		MX35_PAD_FEC_MDC__FEC_MDC,
		MX35_PAD_FEC_MDIO__FEC_MDIO,
		MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
		MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
		MX35_PAD_FEC_CRS__FEC_CRS,
		MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
		MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
		MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
		MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
		MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
		MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
		/* GPIO used to power off ethernet */
		MX35_PAD_STXFS4__GPIO2_31,
	};

	/* setup pins for FEC */
	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}

int board_early_init_f(void)
{
	struct ccm_regs *ccm =
		(struct ccm_regs *)IMX_CCM_BASE;

	/* setup GPIO3_1 to set HighVCore signal */
	imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1);
	gpio_direction_output(65, 1);

	/* initialize PLL and clock configuration */
	writel(CCM_CCMR_CONFIG, &ccm->ccmr);

	writel(CCM_MPLL_532_HZ, &ccm->mpctl);
	writel(CCM_PPLL_300_HZ, &ccm->ppctl);

	/* Set the core to run at 532 Mhz */
	writel(0x00001000, &ccm->pdr0);

	/* Set-up RAM */
	board_setup_sdram();

	/* enable clocks */
	writel(readl(&ccm->cgr0) |
		MXC_CCM_CGR0_EMI_MASK |
		MXC_CCM_CGR0_EDIO_MASK |
		MXC_CCM_CGR0_EPIT1_MASK,
		&ccm->cgr0);

	writel(readl(&ccm->cgr1) |
		MXC_CCM_CGR1_FEC_MASK |
		MXC_CCM_CGR1_GPIO1_MASK |
		MXC_CCM_CGR1_GPIO2_MASK |
		MXC_CCM_CGR1_GPIO3_MASK |
		MXC_CCM_CGR1_I2C1_MASK |
		MXC_CCM_CGR1_I2C2_MASK |
		MXC_CCM_CGR1_I2C3_MASK,
		&ccm->cgr1);

	/* Set-up NAND */
	__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);

	/* Set pinmux for the required peripherals */
	setup_iomux_uart3();
	setup_iomux_i2c();
	setup_iomux_fec();
	setup_iomux_spi();

	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;

	/* Enable power for ethernet */
	gpio_direction_output(63, 0);

	udelay(2000);

	return 0;
}

u32 get_board_rev(void)
{
	int rev = 0;

	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
}

/*
 * called prior to booting kernel or by 'fdt boardsetup' command
 *
 */
int ft_board_setup(void *blob, bd_t *bd)
{
	struct node_info nodes[] = {
		{ "physmap-flash.0", MTD_DEV_TYPE_NOR, },  /* NOR flash */
		{ "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
	};

	if (env_get("fdt_noauto")) {
		puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
		return 0;
	}

	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));

	return 0;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
deb53483 SB	2	/*
	3	* Copyright (C) 2007, Guennadi Liakhovetski <[email protected]>
	4	*
	5	* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
	6	*
	7	* Copyright (C) 2011, Stefano Babic <[email protected]>
deb53483 SB	8	*/
	9
	10	#include <common.h>
	11	#include <asm/io.h>
1221ce45	12	#include <linux/errno.h>
deb53483 SB	13	#include <asm/arch/imx-regs.h>
deb53483 SB	14	#include <asm/arch/crm_regs.h>
686e1448	15	#include <asm/arch/iomux-mx35.h>
deb53483 SB	16	#include <i2c.h>
	17	#include <linux/types.h>
	18	#include <asm/gpio.h>
	19	#include <asm/arch/sys_proto.h>
	20	#include <netdev.h>
72c10153 HS	21	#include <fdt_support.h>
	22	#include <mtd_node.h>
	23	#include <jffs2/load_kernel.h>
deb53483 SB	24
	25	#ifndef CONFIG_BOARD_EARLY_INIT_F
	26	#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
	27	#endif
	28
	29	#define CCM_CCMR_CONFIG 0x003F4208
	30
	31	#define ESDCTL_DDR2_CONFIG 0x007FFC3F
deb53483 SB	32
	33	static inline void dram_wait(unsigned int count)
	34	{
	35	volatile unsigned int wait = count;
	36
	37	while (wait--)
	38	;
	39	}
	40
	41	DECLARE_GLOBAL_DATA_PTR;
	42
	43	int dram_init(void)
	44	{
	45	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
	46	PHYS_SDRAM_1_SIZE);
	47
	48	return 0;
	49	}
	50
deb53483 SB	51	static void board_setup_sdram(void)
	52	{
	53	struct esdc_regs esdc = (struct esdc_regs )ESDCTL_BASE_ADDR;
	54
	55	/* Initialize with default values both CSD0/1 */
	56	writel(0x2000, &esdc->esdctl0);
	57	writel(0x2000, &esdc->esdctl1);
	58
146fff34 SB	59
	60	mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
	61	13, 10, 2, 0x8080);
deb53483 SB	62	}
	63
	64	static void setup_iomux_uart3(void)
	65	{
686e1448 BT	66	static const iomux_v3_cfg_t uart3_pads[] = {
	67	MX35_PAD_RTS2__UART3_RXD_MUX,
	68	MX35_PAD_CTS2__UART3_TXD_MUX,
	69	};
	70
	71	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
deb53483 SB	72	}
deb53483 SB	73
686e1448 BT	74	#define I2C_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_100K_DOWN \| PAD_CTL_ODE)
686e1448 BT	75
deb53483 SB	76	static void setup_iomux_i2c(void)
deb53483 SB	77	{
686e1448 BT	78	static const iomux_v3_cfg_t i2c_pads[] = {
	79	NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
	80	NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
deb53483	81
686e1448 BT	82	NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL),
	83	NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL),
	84	};
deb53483	85
686e1448	86	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
deb53483 SB	87	}
	88
	89
	90	static void setup_iomux_spi(void)
	91	{
686e1448 BT	92	static const iomux_v3_cfg_t spi_pads[] = {
	93	MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
	94	MX35_PAD_CSPI1_MISO__CSPI1_MISO,
	95	MX35_PAD_CSPI1_SS0__CSPI1_SS0,
	96	MX35_PAD_CSPI1_SS1__CSPI1_SS1,
	97	MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
	98	};
	99
	100	imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
deb53483 SB	101	}
	102
	103	static void setup_iomux_fec(void)
	104	{
686e1448 BT	105	static const iomux_v3_cfg_t fec_pads[] = {
	106	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
	107	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
	108	MX35_PAD_FEC_RX_DV__FEC_RX_DV,
	109	MX35_PAD_FEC_COL__FEC_COL,
	110	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
	111	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
	112	MX35_PAD_FEC_TX_EN__FEC_TX_EN,
	113	MX35_PAD_FEC_MDC__FEC_MDC,
	114	MX35_PAD_FEC_MDIO__FEC_MDIO,
	115	MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
	116	MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
	117	MX35_PAD_FEC_CRS__FEC_CRS,
	118	MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
	119	MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
	120	MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
	121	MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
	122	MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
	123	MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
322ac5f1 SB	124	/* GPIO used to power off ethernet */
322ac5f1 SB	125	MX35_PAD_STXFS4__GPIO2_31,
686e1448	126	};
deb53483	127
686e1448 BT	128	/* setup pins for FEC */
686e1448 BT	129	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
deb53483 SB	130	}
	131
	132	int board_early_init_f(void)
	133	{
	134	struct ccm_regs *ccm =
	135	(struct ccm_regs *)IMX_CCM_BASE;
	136
	137	/* setup GPIO3_1 to set HighVCore signal */
686e1448	138	imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1);
deb53483 SB	139	gpio_direction_output(65, 1);
	140
	141	/* initialize PLL and clock configuration */
	142	writel(CCM_CCMR_CONFIG, &ccm->ccmr);
	143
	144	writel(CCM_MPLL_532_HZ, &ccm->mpctl);
	145	writel(CCM_PPLL_300_HZ, &ccm->ppctl);
	146
	147	/* Set the core to run at 532 Mhz */
	148	writel(0x00001000, &ccm->pdr0);
	149
	150	/* Set-up RAM */
	151	board_setup_sdram();
	152
	153	/* enable clocks */
	154	writel(readl(&ccm->cgr0) \|
	155	MXC_CCM_CGR0_EMI_MASK \|
34a31bf5	156	MXC_CCM_CGR0_EDIO_MASK \|
deb53483 SB	157	MXC_CCM_CGR0_EPIT1_MASK,
	158	&ccm->cgr0);
	159
	160	writel(readl(&ccm->cgr1) \|
	161	MXC_CCM_CGR1_FEC_MASK \|
	162	MXC_CCM_CGR1_GPIO1_MASK \|
	163	MXC_CCM_CGR1_GPIO2_MASK \|
	164	MXC_CCM_CGR1_GPIO3_MASK \|
	165	MXC_CCM_CGR1_I2C1_MASK \|
	166	MXC_CCM_CGR1_I2C2_MASK \|
	167	MXC_CCM_CGR1_I2C3_MASK,
	168	&ccm->cgr1);
	169
	170	/* Set-up NAND */
	171	__raw_writel(readl(&ccm->rcsr) \| MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
	172
	173	/* Set pinmux for the required peripherals */
	174	setup_iomux_uart3();
	175	setup_iomux_i2c();
	176	setup_iomux_fec();
	177	setup_iomux_spi();
	178
	179	return 0;
	180	}
	181
	182	int board_init(void)
	183	{
	184	/* address of boot parameters */
	185	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
	186
322ac5f1 SB	187	/* Enable power for ethernet */
	188	gpio_direction_output(63, 0);
	189
	190	udelay(2000);
	191
deb53483 SB	192	return 0;
	193	}
	194
	195	u32 get_board_rev(void)
	196	{
	197	int rev = 0;
	198
	199	return (get_cpu_rev() & ~(0xF << 8)) \| (rev & 0xF) << 8;
	200	}
72c10153 HS	201
	202	/*
	203	* called prior to booting kernel or by 'fdt boardsetup' command
	204	*
	205	*/
	206	int ft_board_setup(void blob, bd_t bd)
	207	{
	208	struct node_info nodes[] = {
	209	{ "physmap-flash.0", MTD_DEV_TYPE_NOR, }, /* NOR flash */
	210	{ "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
	211	};
	212
00caae6d	213	if (env_get("fdt_noauto")) {
72c10153 HS	214	puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
	215	return 0;
	216	}
	217
	218	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
	219
	220	return 0;
	221	}