]> Git Repo - u-boot.git/blame - arch/arm/mach-tegra/cpu.h
SPDX: Convert all of our single license tags to Linux Kernel style
[u-boot.git] / arch / arm / mach-tegra / cpu.h
CommitLineData
83d290c5 1/* SPDX-License-Identifier: GPL-2.0+ */
c037c93b 2/*
7aaa5a60 3 * (C) Copyright 2010-2015
c037c93b 4 * NVIDIA Corporation <www.nvidia.com>
c037c93b
AM
5 */
6#include <asm/types.h>
7
8/* Stabilization delays, in usec */
9#define PLL_STABILIZATION_DELAY (300)
10#define IO_STABILIZATION_DELAY (1000)
11
4040ec10 12#if defined(CONFIG_TEGRA20)
a4bcd67c
SW
13#define NVBL_PLLP_KHZ 216000
14#define CSITE_KHZ 144000
32edd2ed 15#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \
7aaa5a60 16 defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
a4bcd67c 17#define NVBL_PLLP_KHZ 408000
027638d3 18#define CSITE_KHZ 136000
4040ec10
TW
19#else
20#error "Unknown Tegra chip!"
1b245fee 21#endif
c037c93b
AM
22
23#define PLLX_ENABLED (1 << 30)
24#define CCLK_BURST_POLICY 0x20008888
25#define SUPER_CCLK_DIVIDER 0x80000000
26
27/* Calculate clock fractional divider value from ref and target frequencies */
28#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
29
30/* Calculate clock frequency value from reference and clock divider value */
31#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
32
33/* AVP/CPU ID */
34#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
35#define PG_UP_TAG_0 0x0
36
7aaa5a60 37#define CORESIGHT_UNLOCK 0xC5ACCE55
c037c93b 38
c037c93b
AM
39#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
40#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
41#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
1b245fee
TW
42#define CSITE_CPU_DBG2_LAR (NV_PA_CSITE_BASE + 0x14FB0)
43#define CSITE_CPU_DBG3_LAR (NV_PA_CSITE_BASE + 0x16FB0)
c037c93b
AM
44
45#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
46#define FLOW_MODE_STOP 2
47#define HALT_COP_EVENT_JTAG (1 << 28)
48#define HALT_COP_EVENT_IRQ_1 (1 << 11)
49#define HALT_COP_EVENT_FIQ_1 (1 << 9)
50
1b245fee
TW
51#define FLOW_MODE_NONE 0
52
53#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
54
7aaa5a60
TW
55/* SB_AA64_RESET_LOW and _HIGH defines for CPU reset vector */
56#define SB_AA64_RESET_LOW 0x6000C230
57#define SB_AA64_RESET_HIGH 0x6000C234
58
1b245fee
TW
59struct clk_pll_table {
60 u16 n;
61 u16 m;
62 u8 p;
63 u8 cpcon;
64};
65
66void clock_enable_coresight(int enable);
67void enable_cpu_clock(int enable);
c037c93b 68void halt_avp(void) __attribute__ ((noreturn));
1b245fee
TW
69void init_pllx(void);
70void powerup_cpu(void);
71void reset_A9_cpu(int reset);
72void start_cpu(u32 reset_vector);
49493cb7
TW
73int tegra_get_chip(void);
74int tegra_get_sku_info(void);
75int tegra_get_chip_sku(void);
1b245fee 76void adjust_pllp_out_freqs(void);
32edd2ed 77void pmic_enable_cpu_vdd(void);
This page took 0.225801 seconds and 4 git commands to generate.