]>
Commit | Line | Data |
---|---|---|
83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
4efb77d4 PW |
2 | /* |
3 | * Copyright (C) Marvell International Ltd. and its affiliates | |
4 | * Written-by: Prafulla Wadaskar <[email protected]> | |
5 | * | |
2fbc18fe | 6 | * Copyright (C) 2015 Stefan Roese <[email protected]> |
4efb77d4 PW |
7 | */ |
8 | ||
9 | #include <common.h> | |
a7efd719 | 10 | #include <asm/io.h> |
3dc23f78 | 11 | #include <asm/arch/soc.h> |
4efb77d4 | 12 | |
2fbc18fe | 13 | #define TIMER_LOAD_VAL 0xffffffff |
4efb77d4 | 14 | |
2fbc18fe | 15 | static int init_done __attribute__((section(".data"))) = 0; |
4efb77d4 PW |
16 | |
17 | /* | |
2fbc18fe | 18 | * Timer initialization |
4efb77d4 PW |
19 | */ |
20 | int timer_init(void) | |
21 | { | |
ade741b3 SR |
22 | /* Only init the timer once */ |
23 | if (init_done) | |
24 | return 0; | |
25 | init_done = 1; | |
26 | ||
4efb77d4 | 27 | /* load value into timer */ |
2fbc18fe SR |
28 | writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x10); |
29 | writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x14); | |
4efb77d4 | 30 | |
81e33f4b | 31 | #if defined(CONFIG_ARCH_MVEBU) |
2fbc18fe SR |
32 | /* On Armada XP / 38x ..., the 25MHz clock source needs to be enabled */ |
33 | setbits_le32(MVEBU_TIMER_BASE + 0x00, BIT(11)); | |
34 | #endif | |
4efb77d4 | 35 | /* enable timer in auto reload mode */ |
2fbc18fe | 36 | setbits_le32(MVEBU_TIMER_BASE + 0x00, 0x3); |
4efb77d4 PW |
37 | |
38 | return 0; | |
39 | } |