Commit | Line | Data |
---|---|---|
83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
edb47025 SR |
2 | /* |
3 | * Copyright (C) Marvell International Ltd. and its affiliates | |
edb47025 SR |
4 | */ |
5 | ||
6 | #ifndef _HIGH_SPEED_ENV_SPEC_H | |
7 | #define _HIGH_SPEED_ENV_SPEC_H | |
8 | ||
9 | #include "seq_exec.h" | |
10 | ||
11 | /* | |
12 | * For setting or clearing a certain bit (bit is a number between 0 and 31) | |
13 | * in the data | |
14 | */ | |
15 | #define SET_BIT(data, bit) ((data) | (0x1 << (bit))) | |
16 | #define CLEAR_BIT(data, bit) ((data) & (~(0x1 << (bit)))) | |
17 | ||
18 | #define MAX_SERDES_LANES 7 /* as in a39x */ | |
19 | ||
20 | /* Serdes revision */ | |
21 | /* Serdes revision 1.2 (for A38x-Z1) */ | |
22 | #define MV_SERDES_REV_1_2 0x0 | |
23 | /* Serdes revision 2.1 (for A39x-Z1, A38x-A0) */ | |
24 | #define MV_SERDES_REV_2_1 0x1 | |
25 | #define MV_SERDES_REV_NA 0xff | |
26 | ||
27 | #define SERDES_REGS_LANE_BASE_OFFSET(lane) (0x800 * (lane)) | |
28 | ||
29 | #define PEX_X4_ENABLE_OFFS \ | |
30 | (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2 ? 18 : 31) | |
31 | ||
32 | /* Serdes lane types */ | |
33 | enum serdes_type { | |
34 | PEX0, | |
35 | PEX1, | |
36 | PEX2, | |
37 | PEX3, | |
38 | SATA0, | |
39 | SATA1, | |
40 | SATA2, | |
41 | SATA3, | |
42 | SGMII0, | |
43 | SGMII1, | |
44 | SGMII2, | |
45 | QSGMII, | |
46 | USB3_HOST0, | |
47 | USB3_HOST1, | |
48 | USB3_DEVICE, | |
49 | SGMII3, | |
50 | XAUI, | |
51 | RXAUI, | |
52 | DEFAULT_SERDES, | |
53 | LAST_SERDES_TYPE | |
54 | }; | |
55 | ||
56 | /* Serdes baud rates */ | |
57 | enum serdes_speed { | |
58 | SERDES_SPEED_1_25_GBPS, | |
59 | SERDES_SPEED_1_5_GBPS, | |
60 | SERDES_SPEED_2_5_GBPS, | |
61 | SERDES_SPEED_3_GBPS, | |
62 | SERDES_SPEED_3_125_GBPS, | |
63 | SERDES_SPEED_5_GBPS, | |
64 | SERDES_SPEED_6_GBPS, | |
65 | SERDES_SPEED_6_25_GBPS, | |
66 | LAST_SERDES_SPEED | |
67 | }; | |
68 | ||
69 | /* Serdes modes */ | |
70 | enum serdes_mode { | |
71 | PEX_ROOT_COMPLEX_X1, | |
72 | PEX_ROOT_COMPLEX_X4, | |
73 | PEX_END_POINT_X1, | |
74 | PEX_END_POINT_X4, | |
75 | ||
76 | SERDES_DEFAULT_MODE, /* not pex */ | |
77 | ||
78 | SERDES_LAST_MODE | |
79 | }; | |
80 | ||
81 | struct serdes_map { | |
82 | enum serdes_type serdes_type; | |
83 | enum serdes_speed serdes_speed; | |
84 | enum serdes_mode serdes_mode; | |
85 | int swap_rx; | |
86 | int swap_tx; | |
87 | }; | |
88 | ||
89 | /* Serdes ref clock options */ | |
90 | enum ref_clock { | |
91 | REF_CLOCK_25MHZ, | |
92 | REF_CLOCK_100MHZ, | |
93 | REF_CLOCK_40MHZ, | |
94 | REF_CLOCK_UNSUPPORTED | |
95 | }; | |
96 | ||
97 | /* Serdes sequences */ | |
98 | enum serdes_seq { | |
99 | SATA_PORT_0_ONLY_POWER_UP_SEQ, | |
100 | SATA_PORT_1_ONLY_POWER_UP_SEQ, | |
101 | SATA_POWER_UP_SEQ, | |
102 | SATA_1_5_SPEED_CONFIG_SEQ, | |
103 | SATA_3_SPEED_CONFIG_SEQ, | |
104 | SATA_6_SPEED_CONFIG_SEQ, | |
105 | SATA_ELECTRICAL_CONFIG_SEQ, | |
106 | SATA_TX_CONFIG_SEQ1, | |
107 | SATA_PORT_0_ONLY_TX_CONFIG_SEQ, | |
108 | SATA_PORT_1_ONLY_TX_CONFIG_SEQ, | |
109 | SATA_TX_CONFIG_SEQ2, | |
110 | ||
111 | SGMII_POWER_UP_SEQ, | |
112 | SGMII_1_25_SPEED_CONFIG_SEQ, | |
113 | SGMII_3_125_SPEED_CONFIG_SEQ, | |
114 | SGMII_ELECTRICAL_CONFIG_SEQ, | |
115 | SGMII_TX_CONFIG_SEQ1, | |
116 | SGMII_TX_CONFIG_SEQ2, | |
117 | ||
118 | PEX_POWER_UP_SEQ, | |
119 | PEX_2_5_SPEED_CONFIG_SEQ, | |
120 | PEX_5_SPEED_CONFIG_SEQ, | |
121 | PEX_ELECTRICAL_CONFIG_SEQ, | |
122 | PEX_TX_CONFIG_SEQ1, | |
123 | PEX_TX_CONFIG_SEQ2, | |
124 | PEX_TX_CONFIG_SEQ3, | |
125 | PEX_BY_4_CONFIG_SEQ, | |
126 | PEX_CONFIG_REF_CLOCK_25MHZ_SEQ, | |
127 | PEX_CONFIG_REF_CLOCK_100MHZ_SEQ, | |
128 | PEX_CONFIG_REF_CLOCK_40MHZ_SEQ, | |
129 | ||
130 | USB3_POWER_UP_SEQ, | |
131 | USB3_HOST_SPEED_CONFIG_SEQ, | |
132 | USB3_DEVICE_SPEED_CONFIG_SEQ, | |
133 | USB3_ELECTRICAL_CONFIG_SEQ, | |
134 | USB3_TX_CONFIG_SEQ1, | |
135 | USB3_TX_CONFIG_SEQ2, | |
136 | USB3_TX_CONFIG_SEQ3, | |
137 | USB3_DEVICE_CONFIG_SEQ, | |
138 | ||
139 | USB2_POWER_UP_SEQ, | |
140 | ||
141 | SERDES_POWER_DOWN_SEQ, | |
142 | ||
143 | SGMII3_POWER_UP_SEQ, | |
144 | SGMII3_1_25_SPEED_CONFIG_SEQ, | |
145 | SGMII3_TX_CONFIG_SEQ1, | |
146 | SGMII3_TX_CONFIG_SEQ2, | |
147 | ||
148 | QSGMII_POWER_UP_SEQ, | |
149 | QSGMII_5_SPEED_CONFIG_SEQ, | |
150 | QSGMII_ELECTRICAL_CONFIG_SEQ, | |
151 | QSGMII_TX_CONFIG_SEQ1, | |
152 | QSGMII_TX_CONFIG_SEQ2, | |
153 | ||
154 | XAUI_POWER_UP_SEQ, | |
155 | XAUI_3_125_SPEED_CONFIG_SEQ, | |
156 | XAUI_ELECTRICAL_CONFIG_SEQ, | |
157 | XAUI_TX_CONFIG_SEQ1, | |
158 | XAUI_TX_CONFIG_SEQ2, | |
159 | ||
160 | RXAUI_POWER_UP_SEQ, | |
161 | RXAUI_6_25_SPEED_CONFIG_SEQ, | |
162 | RXAUI_ELECTRICAL_CONFIG_SEQ, | |
163 | RXAUI_TX_CONFIG_SEQ1, | |
164 | RXAUI_TX_CONFIG_SEQ2, | |
165 | ||
166 | SERDES_LAST_SEQ | |
167 | }; | |
168 | ||
169 | /* The different sequence types for PEX and USB3 */ | |
170 | enum { | |
171 | PEX, | |
172 | USB3, | |
173 | LAST_PEX_USB_SEQ_TYPE | |
174 | }; | |
175 | ||
176 | enum { | |
177 | PEXSERDES_SPEED_2_5_GBPS, | |
178 | PEXSERDES_SPEED_5_GBPS, | |
179 | USB3SERDES_SPEED_5_GBPS_HOST, | |
180 | USB3SERDES_SPEED_5_GBPS_DEVICE, | |
181 | LAST_PEX_USB_SPEED_SEQ_TYPE | |
182 | }; | |
183 | ||
184 | /* The different sequence types for SATA and SGMII */ | |
185 | enum { | |
186 | SATA, | |
187 | SGMII, | |
188 | SGMII_3_125, | |
189 | LAST_SATA_SGMII_SEQ_TYPE | |
190 | }; | |
191 | ||
192 | enum { | |
193 | QSGMII_SEQ_IDX, | |
194 | LAST_QSGMII_SEQ_TYPE | |
195 | }; | |
196 | ||
197 | enum { | |
198 | XAUI_SEQ_IDX, | |
199 | RXAUI_SEQ_IDX, | |
200 | LAST_XAUI_RXAUI_SEQ_TYPE | |
201 | }; | |
202 | ||
203 | enum { | |
204 | SATASERDES_SPEED_1_5_GBPS, | |
205 | SATASERDES_SPEED_3_GBPS, | |
206 | SATASERDES_SPEED_6_GBPS, | |
207 | SGMIISERDES_SPEED_1_25_GBPS, | |
208 | SGMIISERDES_SPEED_3_125_GBPS, | |
209 | LAST_SATA_SGMII_SPEED_SEQ_TYPE | |
210 | }; | |
211 | ||
212 | extern u8 selectors_serdes_rev1_map[LAST_SERDES_TYPE][MAX_SERDES_LANES]; | |
213 | extern u8 selectors_serdes_rev2_map[LAST_SERDES_TYPE][MAX_SERDES_LANES]; | |
214 | ||
215 | u8 hws_ctrl_serdes_rev_get(void); | |
216 | int mv_update_serdes_select_phy_mode_seq(void); | |
490753ac | 217 | int hws_board_topology_load(struct serdes_map **serdes_map, u8 *count); |
edb47025 SR |
218 | enum serdes_seq serdes_type_and_speed_to_speed_seq(enum serdes_type serdes_type, |
219 | enum serdes_speed baud_rate); | |
220 | int hws_serdes_seq_init(void); | |
221 | int hws_serdes_seq_db_init(void); | |
490753ac | 222 | int hws_power_up_serdes_lanes(struct serdes_map *serdes_map, u8 count); |
edb47025 SR |
223 | int hws_ctrl_high_speed_serdes_phy_config(void); |
224 | int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up, | |
225 | enum serdes_type serdes_type, | |
226 | enum serdes_speed baud_rate, | |
227 | enum serdes_mode serdes_mode, | |
228 | enum ref_clock ref_clock); | |
229 | int serdes_power_up_ctrl_ext(u32 serdes_num, int serdes_power_up, | |
230 | enum serdes_type serdes_type, | |
231 | enum serdes_speed baud_rate, | |
232 | enum serdes_mode serdes_mode, | |
233 | enum ref_clock ref_clock); | |
234 | u32 hws_serdes_silicon_ref_clock_get(void); | |
235 | int hws_serdes_pex_ref_clock_get(enum serdes_type serdes_type, | |
236 | enum ref_clock *ref_clock); | |
237 | int hws_ref_clock_set(u32 serdes_num, enum serdes_type serdes_type, | |
238 | enum ref_clock ref_clock); | |
490753ac | 239 | int hws_update_serdes_phy_selectors(struct serdes_map *serdes_map, u8 count); |
edb47025 SR |
240 | u32 hws_serdes_get_phy_selector_val(int serdes_num, |
241 | enum serdes_type serdes_type); | |
242 | u32 hws_serdes_get_ref_clock_val(enum serdes_type serdes_type); | |
243 | u32 hws_serdes_get_max_lane(void); | |
244 | int hws_get_ext_base_addr(u32 serdes_num, u32 base_addr, u32 unit_base_offset, | |
245 | u32 *unit_base_reg, u32 *unit_offset); | |
490753ac | 246 | int hws_pex_tx_config_seq(const struct serdes_map *serdes_map, u8 count); |
edb47025 SR |
247 | u32 hws_get_physical_serdes_num(u32 serdes_num); |
248 | int hws_is_serdes_active(u8 lane_num); | |
249 | ||
250 | #endif /* _HIGH_SPEED_ENV_SPEC_H */ |