[u-boot.git] / arch / arm / cpu / arm926ejs / spear / spr600_mt47h32m16_333_cl5_psync.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2000-2009
 * Vipin Kumar, ST Microelectronics, [email protected]
 */

#include <common.h>

#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)

const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
#if (CONFIG_DDR_PLL2)
	0x00000001,
	0x00000000,
#elif (CONFIG_DDR_2HCLK)
	0x02020201,
	0x02020202,
#endif
	0x01000000,
	0x00000101,
	0x00000101,
	0x01000000,
	0x00010001,
	0x00000100,
	0x01010001,
	0x00000201,
	0x01000101,
	0x06000002,
	0x06060106,
	0x03050502,
	0x03040404,
	0x02020503,
	0x02010106,
	0x03000405,
	0x03040202,
	0x04000305,
	0x0707073f,
	0x07070707,
	0x06060607,
	0x06060606,
	0x05050506,
	0x05050505,
	0x04040405,
	0x04040404,
	0x03030304,
	0x03030303,
	0x02020203,
	0x02020202,
	0x01010102,
	0x01010101,
	0x0a0a0a01,
	0x0000023f,
	0x00050a00,
	0x11000000,
	0x00001302,
	0x00000A0A,
	0x72000000,
	0x00550000,
	0x2b050e86,
	0x00640064,
	0x00640064,
	0x00640064,
	0x00000064,
	0x00200020,
	0x00200020,
	0x00200020,
	0x00200020,
	0x00200020,
	0x00200020,
	0x00200020,
	0x00000a24,
	0x43C20000,
	0x5b1c00c8,
	0x00c8002e,
	0x00000000,
	0x0001046b,
	0x00000000,
	0x03030100,
	0x03030303,
	0x03030303,
	0x03030303,
	0x00210000,
	0x00010021,
	0x00200000,
	0x006c0090,
	0x003fffff,
	0x003fffff,
	0x00000000,
	0x00000000,
	0x003fffff,
	0x003fffff,
	0x00000000,
	0x00000000,
	0x003fffff,
	0x003fffff,
	0x00000000,
	0x00000000,
	0x003fffff,
	0x003fffff,
	0x00000000,
	0x00000000,
	0x003fffff,
	0x003fffff,
	0x00000000,
	0x00000000,
	0x003fffff,
	0x003fffff,
	0x00000000,
	0x00000000,
	0x003fffff,
	0x003fffff,
	0x00000000,
	0x00000000,
	0x00000000,
	0x00000000,
	0x00000000
};
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
4ae8bc43 SR	2	/*
	3	* (C) Copyright 2000-2009
	4	* Vipin Kumar, ST Microelectronics, [email protected]
4ae8bc43 SR	5	*/
	6
	7	#include <common.h>
	8
	9	#if (CONFIG_DDR_PLL2 \|\| CONFIG_DDR_2HCLK)
	10
	11	const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
	12	#if (CONFIG_DDR_PLL2)
	13	0x00000001,
	14	0x00000000,
	15	#elif (CONFIG_DDR_2HCLK)
	16	0x02020201,
	17	0x02020202,
	18	#endif
	19	0x01000000,
	20	0x00000101,
	21	0x00000101,
	22	0x01000000,
	23	0x00010001,
	24	0x00000100,
	25	0x01010001,
	26	0x00000201,
	27	0x01000101,
	28	0x06000002,
	29	0x06060106,
	30	0x03050502,
	31	0x03040404,
	32	0x02020503,
	33	0x02010106,
	34	0x03000405,
	35	0x03040202,
	36	0x04000305,
	37	0x0707073f,
	38	0x07070707,
	39	0x06060607,
	40	0x06060606,
	41	0x05050506,
	42	0x05050505,
	43	0x04040405,
	44	0x04040404,
	45	0x03030304,
	46	0x03030303,
	47	0x02020203,
	48	0x02020202,
	49	0x01010102,
	50	0x01010101,
	51	0x0a0a0a01,
	52	0x0000023f,
	53	0x00050a00,
	54	0x11000000,
	55	0x00001302,
	56	0x00000A0A,
	57	0x72000000,
	58	0x00550000,
	59	0x2b050e86,
	60	0x00640064,
	61	0x00640064,
	62	0x00640064,
	63	0x00000064,
	64	0x00200020,
	65	0x00200020,
	66	0x00200020,
	67	0x00200020,
	68	0x00200020,
69	0x00200020,
70	0x00200020,
71	0x00000a24,
72	0x43C20000,
73	0x5b1c00c8,
74	0x00c8002e,
75	0x00000000,
76	0x0001046b,
77	0x00000000,
78	0x03030100,
79	0x03030303,
80	0x03030303,
81	0x03030303,
82	0x00210000,
83	0x00010021,
84	0x00200000,
85	0x006c0090,
86	0x003fffff,
87	0x003fffff,
88	0x00000000,
89	0x00000000,
90	0x003fffff,
91	0x003fffff,
92	0x00000000,
93	0x00000000,
94	0x003fffff,
95	0x003fffff,
96	0x00000000,
97	0x00000000,
98	0x003fffff,
99	0x003fffff,
100	0x00000000,
101	0x00000000,
102	0x003fffff,
103	0x003fffff,
104	0x00000000,
105	0x00000000,
106	0x003fffff,
107	0x003fffff,
108	0x00000000,
109	0x00000000,
110	0x003fffff,
111	0x003fffff,
112	0x00000000,
113	0x00000000,
114	0x00000000,
115	0x00000000,
116	0x00000000
117	};
118	#endif