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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
412ae53a AA |
2 | /* |
3 | * LPC32xx dram init | |
4 | * | |
5 | * (C) Copyright 2014 DENX Software Engineering GmbH | |
6 | * Written-by: Albert ARIBAUD <[email protected]> | |
7 | * | |
8 | * This is called by SPL to gain access to the SDR DRAM. | |
9 | * | |
10 | * This code runs from SRAM. | |
11 | * | |
12 | * Actual CONFIG_LPC32XX_SDRAM_* parameters must be provided | |
13 | * by the board configuration file. | |
412ae53a AA |
14 | */ |
15 | ||
16 | #include <common.h> | |
17 | #include <netdev.h> | |
18 | #include <asm/arch/cpu.h> | |
19 | #include <asm/arch/clk.h> | |
20 | #include <asm/arch/wdt.h> | |
21 | #include <asm/arch/emc.h> | |
22 | #include <asm/io.h> | |
23 | ||
24 | static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; | |
25 | static struct emc_regs *emc = (struct emc_regs *)EMC_BASE; | |
26 | ||
27 | void ddr_init(struct emc_dram_settings *dram) | |
28 | { | |
29 | uint32_t ck; | |
30 | ||
31 | /* Enable EMC interface and choose little endian mode */ | |
32 | writel(1, &emc->ctrl); | |
33 | writel(0, &emc->config); | |
34 | /* Select maximum EMC Dynamic Memory Refresh Time */ | |
35 | writel(0x7FF, &emc->refresh); | |
36 | /* Determine CLK */ | |
37 | ck = get_sdram_clk_rate(); | |
38 | /* Configure SDRAM */ | |
39 | writel(dram->cmddelay, &clk->sdramclk_ctrl); | |
40 | writel(dram->config0, &emc->config0); | |
41 | writel(dram->rascas0, &emc->rascas0); | |
42 | writel(dram->rdconfig, &emc->read_config); | |
43 | /* Set timings */ | |
44 | writel((ck / dram->trp) & 0x0000000F, &emc->t_rp); | |
45 | writel((ck / dram->tras) & 0x0000000F, &emc->t_ras); | |
46 | writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex); | |
47 | writel((ck / dram->twr) & 0x0000000F, &emc->t_wr); | |
48 | writel((ck / dram->trc) & 0x0000001F, &emc->t_rc); | |
49 | writel((ck / dram->trfc) & 0x0000001F, &emc->t_rfc); | |
50 | writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr); | |
51 | writel(dram->trrd, &emc->t_rrd); | |
52 | writel(dram->tmrd, &emc->t_mrd); | |
53 | writel(dram->tcdlr, &emc->t_cdlr); | |
54 | /* Dynamic refresh */ | |
55 | writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh); | |
56 | udelay(10); | |
57 | /* Force all clocks, enable inverted ck, issue NOP command */ | |
58 | writel(0x00000193, &emc->control); | |
59 | udelay(100); | |
60 | /* Keep all clocks enabled, issue a PRECHARGE ALL command */ | |
61 | writel(0x00000113, &emc->control); | |
62 | /* Fast dynamic refresh for at least a few SDRAM ck cycles */ | |
63 | writel((((128) >> 4) & 0x7FF), &emc->refresh); | |
64 | udelay(10); | |
65 | /* set correct dynamic refresh timing */ | |
66 | writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh); | |
67 | udelay(10); | |
68 | /* set normal mode to CAS=3 */ | |
69 | writel(0x00000093, &emc->control); | |
70 | readl(EMC_DYCS0_BASE | dram->mode); | |
71 | /* set extended mode to all zeroes */ | |
72 | writel(0x00000093, &emc->control); | |
73 | readl(EMC_DYCS0_BASE | dram->emode); | |
74 | /* stop forcing clocks, keep inverted clock, issue normal mode */ | |
75 | writel(0x00000010, &emc->control); | |
76 | } |