[u-boot.git] / cmd / fpga.c

/*
 * (C) Copyright 2000, 2001
 * Rich Ireland, Enterasys Networks, [email protected].
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 *  FPGA support
 */
#include <common.h>
#include <command.h>
#include <fpga.h>
#include <fs.h>
#include <malloc.h>

/* Local functions */
static int fpga_get_op(char *opstr);

/* Local defines */
enum {
	FPGA_NONE = -1,
	FPGA_INFO,
	FPGA_LOAD,
	FPGA_LOADB,
	FPGA_DUMP,
	FPGA_LOADMK,
	FPGA_LOADP,
	FPGA_LOADBP,
	FPGA_LOADFS,
};

/* ------------------------------------------------------------------------- */
/* command form:
 *   fpga <op> <device number> <data addr> <datasize>
 * where op is 'load', 'dump', or 'info'
 * If there is no device number field, the fpga environment variable is used.
 * If there is no data addr field, the fpgadata environment variable is used.
 * The info command requires no data address field.
 */
int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
	int op, dev = FPGA_INVALID_DEVICE;
	size_t data_size = 0;
	void *fpga_data = NULL;
	char *devstr = env_get("fpga");
	char *datastr = env_get("fpgadata");
	int rc = FPGA_FAIL;
	int wrong_parms = 0;
#if defined(CONFIG_FIT)
	const char *fit_uname = NULL;
	ulong fit_addr;
#endif
#if defined(CONFIG_CMD_FPGA_LOADFS)
	fpga_fs_info fpga_fsinfo;
	fpga_fsinfo.fstype = FS_TYPE_ANY;
#endif

	if (devstr)
		dev = (int) simple_strtoul(devstr, NULL, 16);
	if (datastr)
		fpga_data = (void *)simple_strtoul(datastr, NULL, 16);

	switch (argc) {
#if defined(CONFIG_CMD_FPGA_LOADFS)
	case 9:
		fpga_fsinfo.blocksize = (unsigned int)
					     simple_strtoul(argv[5], NULL, 16);
		fpga_fsinfo.interface = argv[6];
		fpga_fsinfo.dev_part = argv[7];
		fpga_fsinfo.filename = argv[8];
#endif
	case 5:		/* fpga <op> <dev> <data> <datasize> */
		data_size = simple_strtoul(argv[4], NULL, 16);

	case 4:		/* fpga <op> <dev> <data> */
#if defined(CONFIG_FIT)
		if (fit_parse_subimage(argv[3], (ulong)fpga_data,
				       &fit_addr, &fit_uname)) {
			fpga_data = (void *)fit_addr;
			debug("*  fpga: subimage '%s' from FIT image ",
			      fit_uname);
			debug("at 0x%08lx\n", fit_addr);
		} else
#endif
		{
			fpga_data = (void *)simple_strtoul(argv[3], NULL, 16);
			debug("*  fpga: cmdline image address = 0x%08lx\n",
			      (ulong)fpga_data);
		}
		debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);

	case 3:		/* fpga <op> <dev | data addr> */
		dev = (int)simple_strtoul(argv[2], NULL, 16);
		debug("%s: device = %d\n", __func__, dev);
		/* FIXME - this is a really weak test */
		if ((argc == 3) && (dev > fpga_count())) {
			/* must be buffer ptr */
			debug("%s: Assuming buffer pointer in arg 3\n",
			      __func__);

#if defined(CONFIG_FIT)
			if (fit_parse_subimage(argv[2], (ulong)fpga_data,
					       &fit_addr, &fit_uname)) {
				fpga_data = (void *)fit_addr;
				debug("*  fpga: subimage '%s' from FIT image ",
				      fit_uname);
				debug("at 0x%08lx\n", fit_addr);
			} else
#endif
			{
				fpga_data = (void *)(uintptr_t)dev;
				debug("*  fpga: cmdline image addr = 0x%08lx\n",
				      (ulong)fpga_data);
			}

			debug("%s: fpga_data = 0x%lx\n",
			      __func__, (ulong)fpga_data);
			dev = FPGA_INVALID_DEVICE;	/* reset device num */
		}

	case 2:		/* fpga <op> */
		op = (int)fpga_get_op(argv[1]);
		break;

	default:
		debug("%s: Too many or too few args (%d)\n", __func__, argc);
		op = FPGA_NONE;	/* force usage display */
		break;
	}

	if (dev == FPGA_INVALID_DEVICE) {
		puts("FPGA device not specified\n");
		op = FPGA_NONE;
	}

	switch (op) {
	case FPGA_NONE:
	case FPGA_INFO:
		break;
#if defined(CONFIG_CMD_FPGA_LOADFS)
	case FPGA_LOADFS:
		/* Blocksize can be zero */
		if (!fpga_fsinfo.interface || !fpga_fsinfo.dev_part ||
		    !fpga_fsinfo.filename)
			wrong_parms = 1;
#endif
	case FPGA_LOAD:
	case FPGA_LOADP:
	case FPGA_LOADB:
	case FPGA_LOADBP:
	case FPGA_DUMP:
		if (!fpga_data || !data_size)
			wrong_parms = 1;
		break;
#if defined(CONFIG_CMD_FPGA_LOADMK)
	case FPGA_LOADMK:
		if (!fpga_data)
			wrong_parms = 1;
		break;
#endif
	}

	if (wrong_parms) {
		puts("Wrong parameters for FPGA request\n");
		op = FPGA_NONE;
	}

	switch (op) {
	case FPGA_NONE:
		return CMD_RET_USAGE;

	case FPGA_INFO:
		rc = fpga_info(dev);
		break;

	case FPGA_LOAD:
		rc = fpga_load(dev, fpga_data, data_size, BIT_FULL);
		break;

#if defined(CONFIG_CMD_FPGA_LOADP)
	case FPGA_LOADP:
		rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL);
		break;
#endif

	case FPGA_LOADB:
		rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL);
		break;

#if defined(CONFIG_CMD_FPGA_LOADBP)
	case FPGA_LOADBP:
		rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL);
		break;
#endif

#if defined(CONFIG_CMD_FPGA_LOADFS)
	case FPGA_LOADFS:
		rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo);
		break;
#endif

#if defined(CONFIG_CMD_FPGA_LOADMK)
	case FPGA_LOADMK:
		switch (genimg_get_format(fpga_data)) {
#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
		case IMAGE_FORMAT_LEGACY:
			{
				image_header_t *hdr =
						(image_header_t *)fpga_data;
				ulong data;
				uint8_t comp;

				comp = image_get_comp(hdr);
				if (comp == IH_COMP_GZIP) {
#if defined(CONFIG_GZIP)
					ulong image_buf = image_get_data(hdr);
					data = image_get_load(hdr);
					ulong image_size = ~0UL;

					if (gunzip((void *)data, ~0UL,
						   (void *)image_buf,
						   &image_size) != 0) {
						puts("GUNZIP: error\n");
						return 1;
					}
					data_size = image_size;
#else
					puts("Gunzip image is not supported\n");
					return 1;
#endif
				} else {
					data = (ulong)image_get_data(hdr);
					data_size = image_get_data_size(hdr);
				}
				rc = fpga_load(dev, (void *)data, data_size,
					       BIT_FULL);
			}
			break;
#endif
#if defined(CONFIG_FIT)
		case IMAGE_FORMAT_FIT:
			{
				const void *fit_hdr = (const void *)fpga_data;
				int noffset;
				const void *fit_data;

				if (fit_uname == NULL) {
					puts("No FIT subimage unit name\n");
					return 1;
				}

				if (!fit_check_format(fit_hdr)) {
					puts("Bad FIT image format\n");
					return 1;
				}

				/* get fpga component image node offset */
				noffset = fit_image_get_node(fit_hdr,
							     fit_uname);
				if (noffset < 0) {
					printf("Can't find '%s' FIT subimage\n",
					       fit_uname);
					return 1;
				}

				/* verify integrity */
				if (!fit_image_verify(fit_hdr, noffset)) {
					puts ("Bad Data Hash\n");
					return 1;
				}

				/* get fpga subimage data address and length */
				if (fit_image_get_data(fit_hdr, noffset,
						       &fit_data, &data_size)) {
					puts("Fpga subimage data not found\n");
					return 1;
				}

				rc = fpga_load(dev, fit_data, data_size,
					       BIT_FULL);
			}
			break;
#endif
		default:
			puts("** Unknown image type\n");
			rc = FPGA_FAIL;
			break;
		}
		break;
#endif

	case FPGA_DUMP:
		rc = fpga_dump(dev, fpga_data, data_size);
		break;

	default:
		printf("Unknown operation\n");
		return CMD_RET_USAGE;
	}
	return rc;
}

/*
 * Map op to supported operations.  We don't use a table since we
 * would just have to relocate it from flash anyway.
 */
static int fpga_get_op(char *opstr)
{
	int op = FPGA_NONE;

	if (!strcmp("info", opstr))
		op = FPGA_INFO;
	else if (!strcmp("loadb", opstr))
		op = FPGA_LOADB;
	else if (!strcmp("load", opstr))
		op = FPGA_LOAD;
#if defined(CONFIG_CMD_FPGA_LOADP)
	else if (!strcmp("loadp", opstr))
		op = FPGA_LOADP;
#endif
#if defined(CONFIG_CMD_FPGA_LOADBP)
	else if (!strcmp("loadbp", opstr))
		op = FPGA_LOADBP;
#endif
#if defined(CONFIG_CMD_FPGA_LOADFS)
	else if (!strcmp("loadfs", opstr))
		op = FPGA_LOADFS;
#endif
#if defined(CONFIG_CMD_FPGA_LOADMK)
	else if (!strcmp("loadmk", opstr))
		op = FPGA_LOADMK;
#endif
	else if (!strcmp("dump", opstr))
		op = FPGA_DUMP;

	if (op == FPGA_NONE)
		printf("Unknown fpga operation \"%s\"\n", opstr);

	return op;
}

#if defined(CONFIG_CMD_FPGA_LOADFS)
U_BOOT_CMD(fpga, 9, 1, do_fpga,
#else
U_BOOT_CMD(fpga, 6, 1, do_fpga,
#endif
	   "loadable FPGA image support",
	   "[operation type] [device number] [image address] [image size]\n"
	   "fpga operations:\n"
	   "  dump\t[dev] [address] [size]\tLoad device to memory buffer\n"
	   "  info\t[dev]\t\t\tlist known device information\n"
	   "  load\t[dev] [address] [size]\tLoad device from memory buffer\n"
#if defined(CONFIG_CMD_FPGA_LOADP)
	   "  loadp\t[dev] [address] [size]\t"
	   "Load device from memory buffer with partial bitstream\n"
#endif
	   "  loadb\t[dev] [address] [size]\t"
	   "Load device from bitstream buffer (Xilinx only)\n"
#if defined(CONFIG_CMD_FPGA_LOADBP)
	   "  loadbp\t[dev] [address] [size]\t"
	   "Load device from bitstream buffer with partial bitstream"
	   "(Xilinx only)\n"
#endif
#if defined(CONFIG_CMD_FPGA_LOADFS)
	   "Load device from filesystem (FAT by default) (Xilinx only)\n"
	   "  loadfs [dev] [address] [image size] [blocksize] <interface>\n"
	   "        [<dev[:part]>] <filename>\n"
#endif
#if defined(CONFIG_CMD_FPGA_LOADMK)
	   "  loadmk [dev] [address]\tLoad device generated with mkimage"
#if defined(CONFIG_FIT)
	   "\n"
	   "\tFor loadmk operating on FIT format uImage address must include\n"
	   "\tsubimage unit name in the form of addr:<subimg_uname>"
#endif
#endif
);
Commit	Line	Data
4a9cbbe8 WD	1	/*
	2	* (C) Copyright 2000, 2001
	3	* Rich Ireland, Enterasys Networks, [email protected].
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
4a9cbbe8 WD	6	*/
	7
	8	/*
	9	* FPGA support
	10	*/
	11	#include <common.h>
	12	#include <command.h>
8bde7f77	13	#include <fpga.h>
1a897668	14	#include <fs.h>
c3d2b4b4	15	#include <malloc.h>
4a9cbbe8	16
4a9cbbe8	17	/* Local functions */
fc598412	18	static int fpga_get_op(char *opstr);
4a9cbbe8 WD	19
4a9cbbe8 WD	20	/* Local defines */
5cf22289 MS	21	enum {
	22	FPGA_NONE = -1,
	23	FPGA_INFO,
	24	FPGA_LOAD,
	25	FPGA_LOADB,
	26	FPGA_DUMP,
	27	FPGA_LOADMK,
	28	FPGA_LOADP,
	29	FPGA_LOADBP,
	30	FPGA_LOADFS,
	31	};
4a9cbbe8 WD	32
	33	/* ------------------------------------------------------------------------- */
	34	/* command form:
	35	* fpga <op> <device number> <data addr> <datasize>
	36	* where op is 'load', 'dump', or 'info'
	37	* If there is no device number field, the fpga environment variable is used.
	38	* If there is no data addr field, the fpgadata environment variable is used.
	39	* The info command requires no data address field.
	40	*/
fc598412	41	int do_fpga(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
4a9cbbe8	42	{
d4ca31c4 WD	43	int op, dev = FPGA_INVALID_DEVICE;
	44	size_t data_size = 0;
	45	void *fpga_data = NULL;
00caae6d SG	46	char *devstr = env_get("fpga");
00caae6d SG	47	char *datastr = env_get("fpgadata");
d4ca31c4	48	int rc = FPGA_FAIL;
a790b5b2	49	int wrong_parms = 0;
fc598412	50	#if defined(CONFIG_FIT)
c28c4d19 MB	51	const char *fit_uname = NULL;
	52	ulong fit_addr;
	53	#endif
1a897668 SDPP	54	#if defined(CONFIG_CMD_FPGA_LOADFS)
	55	fpga_fs_info fpga_fsinfo;
	56	fpga_fsinfo.fstype = FS_TYPE_ANY;
	57	#endif
d4ca31c4 WD	58
d4ca31c4 WD	59	if (devstr)
fc598412	60	dev = (int) simple_strtoul(devstr, NULL, 16);
d4ca31c4	61	if (datastr)
fc598412	62	fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
d4ca31c4 WD	63
d4ca31c4 WD	64	switch (argc) {
1a897668 SDPP	65	#if defined(CONFIG_CMD_FPGA_LOADFS)
	66	case 9:
	67	fpga_fsinfo.blocksize = (unsigned int)
	68	simple_strtoul(argv[5], NULL, 16);
	69	fpga_fsinfo.interface = argv[6];
	70	fpga_fsinfo.dev_part = argv[7];
	71	fpga_fsinfo.filename = argv[8];
	72	#endif
d4ca31c4	73	case 5: /* fpga <op> <dev> <data> <datasize> */
fc598412	74	data_size = simple_strtoul(argv[4], NULL, 16);
c28c4d19	75
d4ca31c4	76	case 4: /* fpga <op> <dev> <data> */
c28c4d19	77	#if defined(CONFIG_FIT)
fc598412 MS	78	if (fit_parse_subimage(argv[3], (ulong)fpga_data,
fc598412 MS	79	&fit_addr, &fit_uname)) {
c28c4d19	80	fpga_data = (void *)fit_addr;
fc598412 MS	81	debug("* fpga: subimage '%s' from FIT image ",
	82	fit_uname);
	83	debug("at 0x%08lx\n", fit_addr);
c28c4d19 MB	84	} else
	85	#endif
	86	{
fc598412	87	fpga_data = (void *)simple_strtoul(argv[3], NULL, 16);
06297db0	88	debug("* fpga: cmdline image address = 0x%08lx\n",
fc598412	89	(ulong)fpga_data);
c28c4d19	90	}
455ad585	91	debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
c28c4d19	92
d4ca31c4	93	case 3: /* fpga <op> <dev \| data addr> */
fc598412	94	dev = (int)simple_strtoul(argv[2], NULL, 16);
06297db0	95	debug("%s: device = %d\n", __func__, dev);
d4ca31c4	96	/* FIXME - this is a really weak test */
fc598412 MS	97	if ((argc == 3) && (dev > fpga_count())) {
fc598412 MS	98	/* must be buffer ptr */
06297db0	99	debug("%s: Assuming buffer pointer in arg 3\n",
fc598412	100	__func__);
c28c4d19 MB	101
c28c4d19 MB	102	#if defined(CONFIG_FIT)
fc598412 MS	103	if (fit_parse_subimage(argv[2], (ulong)fpga_data,
fc598412 MS	104	&fit_addr, &fit_uname)) {
c28c4d19	105	fpga_data = (void *)fit_addr;
fc598412 MS	106	debug("* fpga: subimage '%s' from FIT image ",
	107	fit_uname);
	108	debug("at 0x%08lx\n", fit_addr);
c28c4d19 MB	109	} else
	110	#endif
	111	{
455ad585	112	fpga_data = (void *)(uintptr_t)dev;
fc598412 MS	113	debug("* fpga: cmdline image addr = 0x%08lx\n",
fc598412 MS	114	(ulong)fpga_data);
c28c4d19 MB	115	}
c28c4d19 MB	116
455ad585 MS	117	debug("%s: fpga_data = 0x%lx\n",
455ad585 MS	118	__func__, (ulong)fpga_data);
d4ca31c4 WD	119	dev = FPGA_INVALID_DEVICE; /* reset device num */
d4ca31c4 WD	120	}
c28c4d19	121
d4ca31c4	122	case 2: /* fpga <op> */
fc598412	123	op = (int)fpga_get_op(argv[1]);
d4ca31c4	124	break;
c28c4d19	125
d4ca31c4	126	default:
fc598412	127	debug("%s: Too many or too few args (%d)\n", __func__, argc);
d4ca31c4 WD	128	op = FPGA_NONE; /* force usage display */
	129	break;
	130	}
	131
a790b5b2 SB	132	if (dev == FPGA_INVALID_DEVICE) {
	133	puts("FPGA device not specified\n");
	134	op = FPGA_NONE;
	135	}
	136
	137	switch (op) {
	138	case FPGA_NONE:
	139	case FPGA_INFO:
	140	break;
1a897668 SDPP	141	#if defined(CONFIG_CMD_FPGA_LOADFS)
	142	case FPGA_LOADFS:
	143	/* Blocksize can be zero */
	144	if (!fpga_fsinfo.interface \|\| !fpga_fsinfo.dev_part \|\|
	145	!fpga_fsinfo.filename)
	146	wrong_parms = 1;
	147	#endif
a790b5b2	148	case FPGA_LOAD:
67193864	149	case FPGA_LOADP:
a790b5b2	150	case FPGA_LOADB:
67193864	151	case FPGA_LOADBP:
a790b5b2 SB	152	case FPGA_DUMP:
	153	if (!fpga_data \|\| !data_size)
	154	wrong_parms = 1;
	155	break;
64e809af	156	#if defined(CONFIG_CMD_FPGA_LOADMK)
a790b5b2 SB	157	case FPGA_LOADMK:
	158	if (!fpga_data)
	159	wrong_parms = 1;
	160	break;
64e809af	161	#endif
a790b5b2 SB	162	}
	163
	164	if (wrong_parms) {
	165	puts("Wrong parameters for FPGA request\n");
	166	op = FPGA_NONE;
	167	}
	168
d4ca31c4 WD	169	switch (op) {
d4ca31c4 WD	170	case FPGA_NONE:
4c12eeb8	171	return CMD_RET_USAGE;
d4ca31c4 WD	172
d4ca31c4 WD	173	case FPGA_INFO:
fc598412	174	rc = fpga_info(dev);
d4ca31c4 WD	175	break;
	176
	177	case FPGA_LOAD:
7a78bd26	178	rc = fpga_load(dev, fpga_data, data_size, BIT_FULL);
d4ca31c4 WD	179	break;
d4ca31c4 WD	180
67193864 MS	181	#if defined(CONFIG_CMD_FPGA_LOADP)
	182	case FPGA_LOADP:
	183	rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL);
	184	break;
	185	#endif
	186
30ce5ab0	187	case FPGA_LOADB:
7a78bd26	188	rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL);
30ce5ab0 WD	189	break;
30ce5ab0 WD	190
67193864 MS	191	#if defined(CONFIG_CMD_FPGA_LOADBP)
	192	case FPGA_LOADBP:
	193	rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL);
	194	break;
	195	#endif
	196
1a897668 SDPP	197	#if defined(CONFIG_CMD_FPGA_LOADFS)
	198	case FPGA_LOADFS:
	199	rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo);
	200	break;
	201	#endif
	202
64e809af	203	#if defined(CONFIG_CMD_FPGA_LOADMK)
f0ff4692	204	case FPGA_LOADMK:
fc598412	205	switch (genimg_get_format(fpga_data)) {
21d29f7f	206	#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
d5934ad7 MB	207	case IMAGE_FORMAT_LEGACY:
d5934ad7 MB	208	{
fc598412 MS	209	image_header_t *hdr =
	210	(image_header_t *)fpga_data;
	211	ulong data;
32d7cdd3 MS	212	uint8_t comp;
	213
	214	comp = image_get_comp(hdr);
	215	if (comp == IH_COMP_GZIP) {
1b63aaa5	216	#if defined(CONFIG_GZIP)
32d7cdd3 MS	217	ulong image_buf = image_get_data(hdr);
	218	data = image_get_load(hdr);
	219	ulong image_size = ~0UL;
	220
	221	if (gunzip((void *)data, ~0UL,
	222	(void *)image_buf,
	223	&image_size) != 0) {
	224	puts("GUNZIP: error\n");
	225	return 1;
	226	}
	227	data_size = image_size;
1b63aaa5 MS	228	#else
	229	puts("Gunzip image is not supported\n");
	230	return 1;
	231	#endif
32d7cdd3 MS	232	} else {
	233	data = (ulong)image_get_data(hdr);
	234	data_size = image_get_data_size(hdr);
	235	}
7a78bd26 MS	236	rc = fpga_load(dev, (void *)data, data_size,
7a78bd26 MS	237	BIT_FULL);
f0ff4692	238	}
d5934ad7	239	break;
21d29f7f	240	#endif
d5934ad7 MB	241	#if defined(CONFIG_FIT)
d5934ad7 MB	242	case IMAGE_FORMAT_FIT:
c28c4d19 MB	243	{
	244	const void fit_hdr = (const void )fpga_data;
	245	int noffset;
e6a857da	246	const void *fit_data;
c28c4d19 MB	247
c28c4d19 MB	248	if (fit_uname == NULL) {
fc598412	249	puts("No FIT subimage unit name\n");
c28c4d19 MB	250	return 1;
	251	}
	252
fc598412 MS	253	if (!fit_check_format(fit_hdr)) {
fc598412 MS	254	puts("Bad FIT image format\n");
c28c4d19 MB	255	return 1;
	256	}
	257
	258	/* get fpga component image node offset */
fc598412 MS	259	noffset = fit_image_get_node(fit_hdr,
fc598412 MS	260	fit_uname);
c28c4d19	261	if (noffset < 0) {
fc598412 MS	262	printf("Can't find '%s' FIT subimage\n",
fc598412 MS	263	fit_uname);
c28c4d19 MB	264	return 1;
	265	}
	266
	267	/* verify integrity */
b8da8366	268	if (!fit_image_verify(fit_hdr, noffset)) {
c28c4d19 MB	269	puts ("Bad Data Hash\n");
	270	return 1;
	271	}
	272
	273	/* get fpga subimage data address and length */
fc598412 MS	274	if (fit_image_get_data(fit_hdr, noffset,
	275	&fit_data, &data_size)) {
	276	puts("Fpga subimage data not found\n");
c28c4d19 MB	277	return 1;
	278	}
	279
7a78bd26 MS	280	rc = fpga_load(dev, fit_data, data_size,
7a78bd26 MS	281	BIT_FULL);
c28c4d19	282	}
d5934ad7 MB	283	break;
	284	#endif
	285	default:
fc598412	286	puts("** Unknown image type\n");
d5934ad7 MB	287	rc = FPGA_FAIL;
d5934ad7 MB	288	break;
f0ff4692 SR	289	}
f0ff4692 SR	290	break;
64e809af	291	#endif
f0ff4692	292
d4ca31c4	293	case FPGA_DUMP:
fc598412	294	rc = fpga_dump(dev, fpga_data, data_size);
d4ca31c4 WD	295	break;
	296
	297	default:
fc598412	298	printf("Unknown operation\n");
4c12eeb8	299	return CMD_RET_USAGE;
d4ca31c4	300	}
fc598412	301	return rc;
4a9cbbe8 WD	302	}
4a9cbbe8 WD	303
4a9cbbe8 WD	304	/*
	305	* Map op to supported operations. We don't use a table since we
	306	* would just have to relocate it from flash anyway.
	307	*/
fc598412	308	static int fpga_get_op(char *opstr)
4a9cbbe8 WD	309	{
	310	int op = FPGA_NONE;
	311
fc598412	312	if (!strcmp("info", opstr))
4a9cbbe8	313	op = FPGA_INFO;
fc598412	314	else if (!strcmp("loadb", opstr))
30ce5ab0	315	op = FPGA_LOADB;
fc598412	316	else if (!strcmp("load", opstr))
4a9cbbe8	317	op = FPGA_LOAD;
67193864 MS	318	#if defined(CONFIG_CMD_FPGA_LOADP)
	319	else if (!strcmp("loadp", opstr))
	320	op = FPGA_LOADP;
	321	#endif
	322	#if defined(CONFIG_CMD_FPGA_LOADBP)
	323	else if (!strcmp("loadbp", opstr))
	324	op = FPGA_LOADBP;
	325	#endif
1a897668 SDPP	326	#if defined(CONFIG_CMD_FPGA_LOADFS)
	327	else if (!strcmp("loadfs", opstr))
	328	op = FPGA_LOADFS;
	329	#endif
64e809af	330	#if defined(CONFIG_CMD_FPGA_LOADMK)
fc598412	331	else if (!strcmp("loadmk", opstr))
f0ff4692	332	op = FPGA_LOADMK;
64e809af	333	#endif
fc598412	334	else if (!strcmp("dump", opstr))
4a9cbbe8	335	op = FPGA_DUMP;
4a9cbbe8	336
fc598412 MS	337	if (op == FPGA_NONE)
	338	printf("Unknown fpga operation \"%s\"\n", opstr);
	339
4a9cbbe8 WD	340	return op;
	341	}
	342
1a897668 SDPP	343	#if defined(CONFIG_CMD_FPGA_LOADFS)
	344	U_BOOT_CMD(fpga, 9, 1, do_fpga,
	345	#else
fc598412	346	U_BOOT_CMD(fpga, 6, 1, do_fpga,
1a897668	347	#endif
fc598412 MS	348	"loadable FPGA image support",
	349	"[operation type] [device number] [image address] [image size]\n"
	350	"fpga operations:\n"
2d73f0d6	351	" dump\t[dev] [address] [size]\tLoad device to memory buffer\n"
fc598412 MS	352	" info\t[dev]\t\t\tlist known device information\n"
fc598412 MS	353	" load\t[dev] [address] [size]\tLoad device from memory buffer\n"
67193864 MS	354	#if defined(CONFIG_CMD_FPGA_LOADP)
	355	" loadp\t[dev] [address] [size]\t"
	356	"Load device from memory buffer with partial bitstream\n"
	357	#endif
fc598412 MS	358	" loadb\t[dev] [address] [size]\t"
fc598412 MS	359	"Load device from bitstream buffer (Xilinx only)\n"
67193864 MS	360	#if defined(CONFIG_CMD_FPGA_LOADBP)
	361	" loadbp\t[dev] [address] [size]\t"
	362	"Load device from bitstream buffer with partial bitstream"
	363	"(Xilinx only)\n"
	364	#endif
1a897668 SDPP	365	#if defined(CONFIG_CMD_FPGA_LOADFS)
	366	"Load device from filesystem (FAT by default) (Xilinx only)\n"
	367	" loadfs [dev] [address] [image size] [blocksize] <interface>\n"
	368	" [<dev[:part]>] <filename>\n"
	369	#endif
64e809af	370	#if defined(CONFIG_CMD_FPGA_LOADMK)
fc598412	371	" loadmk [dev] [address]\tLoad device generated with mkimage"
c28c4d19	372	#if defined(CONFIG_FIT)
fc598412 MS	373	"\n"
	374	"\tFor loadmk operating on FIT format uImage address must include\n"
	375	"\tsubimage unit name in the form of addr:<subimg_uname>"
c28c4d19	376	#endif
64e809af	377	#endif
c28c4d19	378	);